JPS61286770A - Apparatus for diagnosing trouble - Google Patents

Abstract

PURPOSE:To accurately detect the trouble place in a digital signal processing system without imparting adverse effect to the essential function of the digital signal processing system, by mounting a reversible/non-reversible part arranged between digital circuits, a signal generation part and a trouble discrimination part. CONSTITUTION:A signal generation part 1 generates signals of a high level (1) and a low level (0) and a digital signal processing system 10 is constituted of first, second and third digital circuit 2, 4, 6. Reversible/non-reversible parts 3, 5 capable of changing over a signal state between reversible and non- reversible parts are respectively arranged so as to be connected between the circuits 2, 4 and between the circuits 4, 6 and a memory 7 can write the output of the circuit 6. A trouble discrimination part 8 performs not only the operational control of the signal generation part 1 and the reversible/non-reversible parts 3, 5 but also the discrimination of normality or abnormality from the memory content of the memory 7, that is, the state of the output terminal of the digital signal processing system 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a fault diagnosis device for detecting a fault location in a digital signal processing system.

[Technical background of the invention and its problems]

When an abnormality occurs in a digital signal processing system made up of multiple circuit blocks (boards), it is important to quickly detect which board is malfunctioning in order to reduce the downtime of equipment that includes that circuit block. This is very important.

By the way, detecting a faulty board is done by checking the input/output status of each board.
This can be done by making a determination using the PU (Central Processing Unit).

However, in order to detect a faulty board using the CPU, it is necessary to provide a dedicated bus for fault detection for each board. For example, the data handled between each board is 8
If it is a bit, an 8-bit dedicated bus must be provided for each board for failure detection. Therefore, not only does the device itself become expensive, but the board size becomes large.Also, since the dedicated bus is directly connected to the signal transmission path between each board, it is easily susceptible to external noise, and the normal use of the digital signal processing system There is a problem that sometimes the original functions of the processing system are adversely affected.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is inexpensive.
Another object of the present invention is to provide a fault diagnosis device that can accurately detect a fault location in a digital signal processing system without adversely affecting the original functions of the digital signal processing system.

[Summary of the invention]

The outline of the present invention for achieving the above object is to provide a digital signal processing system that is arranged in a signal transmission path between a plurality of digital circuits constituting a digital signal processing system, and that the signal state of the signal transmission path is inverted or non-inverted. a switchable inverting/non-inverting section;
a signal generating section capable of switching the state of the input terminal of the digital signal processing system between high level and low level, and controlling the operation of this signal generating section and the inverting/non-inverting section;
The digital signal processing system is characterized in that it includes a failure determination section that determines whether or not it is normal based on the state of the output end of the digital signal processing system.

[Embodiments of the invention]

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a failure diagnosis device according to an embodiment of the present invention. In the figure, 1 is a signal generating section, which generates high level (1) and low level (0) signals. 2, 4.6 are the 1st and 2nd, respectively. This is a third digital circuit, and this first, second, . A digital signal processing system 10 is constituted by the third digital circuit. 3 and 4
are respectively the above-mentioned No. 1. This is an inverting/non-inverting section connected between the second digital circuits 2 and 3 and between the second and third digital circuits. Reference numeral 7 denotes a memory into which the output of the third digital circuit 6 can be written, and 8 controls the operation of the signal generating section 1 and the inverting/non-inverting sections 3 and 5, and also controls the storage contents of the memory 7, that is, digital signal processing. Series 10
This is a failure determination section that determines whether the output terminal is normal or not based on the state of the output terminal. For example, a CPU (central processing unit) or the like is applied to this failure determination section 8. In addition, switches SWI, S
W2 is a switch for switching the digital signal processing system 10 between a normal use mode and a failure diagnosis mode;
The illustrated state is the failure diagnosis mode.

Next, referring also to FIG. 2, the inversion/non-inversion section 3,
The configuration of No. 5 will be explained.

FIG. 2 is a circuit diagram showing details of the inverting/non-inverting section in the device of this embodiment. As shown in the figure, this inverting/non-inverting section 3 (5) includes a plurality of exclusive OR circuits G+, Gz
, G3, . . . , G7.

The number of exclusive OR circuits G to GR is 1. 2nd゜3rd
It is equal to the number of bits of the signal transmission path between the digital circuits 2, 4, and 6. For example, if the signal transmission path has an 8-bit configuration, the number of exclusive OR circuits is eight. One input terminal Q, respectively, of the exclusive OR circuits G, G, 1, to Q7
is connected to the fault determination unit 8 via the control line CL, and the other input terminal P, to P, is connected to the output terminal of the first digital circuit 2 (the output terminal of the second digital circuit 4). Connected. In addition, exclusive OR circuits G to G7
The output terminals R1 to R7 are connected to the input terminal of the second digital circuit 4 (the input terminal of the third digital circuit 6).

Next, the operation of the embodiment device configured as above will be explained.

First, in the normal use mode of the digital signal processing system 1o, the switches SW1. Both SW2 are switched to the opposite side from the illustrated state, and a low level (0) signal is applied from the failure determination circuit 8 to the inverting/non-inverting section 3.5.

As is well known, when one input terminal of an exclusive OR circuit is at a low level, the state of the other input terminal is equal to the state of the output terminal.

Therefore, the inverting/non-inverting section 3.5 operates in a non-inverting manner, and transmits the state of the input end to the output end as is.

Next, in the failure diagnosis mode of the digital signal processing system 10, both the switches SWI and SW2 are in the illustrated state.

In this state, the failure determination unit 8 controls the signal generation unit 1 to
The state of the input terminal of the digital circuit 2 is alternately changed between high level and low level. At this time, the output of the third digital circuit 6 is written into the memory 7 via the switch SW2.

The written information is sequentially read out and provided to the failure determination section 8 for determination. In this determination, if the output state of the third digital circuit 6 changes in accordance with the change in the input state of the first digital circuit 2, the digital signal processing system 10 is determined to be "normal". However, in this determination, if the output state of the third digital circuit 6 is fixed at a high level or a low level even though the input state of the first digital circuit 2 is changing, the digital The signal processing system 10 is determined to be "abnormal".

When it is determined that the digital signal processing system 10 is "abnormal",
The failure determination unit 8 detects a failure circuit in the following manner.

First, a high level signal is applied to the inverting/non-inverting section 5 to cause the inverting/non-inverting section 5 to perform an inverting operation. This inverts the input state of the third digital circuit 6. At this time, if the output state of the third digital circuit 6 remains the previous state, the third digital circuit 6 is determined to be "faulty" and the output state of the third digital circuit 6 is reversed. Then, the third digital circuit 6 is determined to be "normal".

If the third digital circuit 6 is out of order, replace it with a normal one.

When the third digital circuit 6 is normal, the failure determining section 8 applies a high level signal to the inverting/non-inverting section 3 to cause the inverting/non-inverting section 3 to perform an inverting operation. This results in
The input state of the second digital circuit 4 is inverted. At this time, if the output state of the third digital circuit 6 remains the previous state, it is determined that the second digital circuit 4 has failed, and if the output of the third digital circuit 6 is reversed, the The second digital circuit 4 is determined to be normal.

If the second digital circuit 4 is out of order, replace it with a normal one.

When the second digital circuit 4 is normal, the failure determination section 8 controls the signal generation section 1 to invert the input state of the first digital circuit 20.

At this time, if the output state of the third digital circuit 6 remains the previous state, it means that the first digital circuit 2 has failed. In this case, the first digital circuit 2
Just replace it with a normal one.

In this way, in this embodiment, the signal generating section 1 and the inverting/
By controlling the operation with the non-inverting sections 3 and 5, the output state of the third digital circuit 6, that is, the output state of the digital signal processing system 10, is
The location of the failure can be detected accurately.

Moreover, as is clear from FIG. 2, the inversion/non-inversion part 3,
The control line CL of No. 5 is connected to the control line CL of No. 1. Second. Regardless of the number of bits in the signal transmission path between the third digital circuits 2 and 4.6, only one bus is required for each, and unlike in the past, a dedicated bus equal to the number of bits in the signal transmission path is not provided.
The cost of the device can be reduced, and the control line C
Since L is not directly connected to the signal transmission path, it is hardly susceptible to external noise, and does not adversely affect the original functions of the digital signal processing system in its normal use mode.

Although one embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above-mentioned embodiment, and can be modified as appropriate within the scope of the gist of the present invention.

For example, in the above embodiment, the first. Second. Although the digital signal processing system 10 has been described as having three circuits, the third digital circuits 2, 4, and 6, any number of digital circuits may be used as long as there are two or more circuits.

In this case, it is preferable to connect and arrange inverting/non-inverting circuits between all the digital circuits, but the object of the present invention can be sufficiently achieved even if the inverting/non-inverting circuits are connected and arranged between the main parts.

Furthermore, the individual digital circuits may be circuit blocks formed on each substrate, or may be functionally divided digital signal processing systems formed on the same substrate.

Further, in the above embodiment, the output state of the third digital circuit 6 is written in the memory 7 once, but the output state of the third digital circuit 6 can be used for failure determination without going through the memory 7. The information may be transmitted to the section 8.

〔Effect of the invention〕

As detailed above, according to the present invention, a fault diagnosis device capable of accurately detecting a fault location in a digital signal processing system without adversely affecting the original functions of the digital signal processing system is provided at a low cost. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a fault diagnosis device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing details of an inverting/non-inverting section in the device of this embodiment. DESCRIPTION OF SYMBOLS 1... Signal generation part, 2, 4.6... Digital circuit, 3.5... Inverting/non-inverting part, 8... Failure determination part,
10...Digital signal processing system. Agent Patent attorney Kensuke Chika (and 1 other person) Figure 2

Claims (1)

[Claims] an inverting/non-inverting section disposed in a signal transmission path between a plurality of digital circuits constituting a digital signal processing system and capable of switching the signal state of the signal transmission path between inversion and non-inversion; a signal generator capable of switching the state of the input end of the processing system between high level and low level;
The present invention is characterized by comprising a failure determining section that controls the operation of the signal generating section and the inverting/non-inverting section, and also determines whether or not the digital signal processing system is normal based on the state of the output end of the digital signal processing system. Fault diagnosis device.