JPH0535665A - Data transfer system - Google Patents

Abstract

PURPOSE:To simplify the processing and to improve the processing speed by lessening the processing in a central processing part when data are transferred from the central processing part to two external input output parts. CONSTITUTION:At the time of the data transfer between a central processing part 1 and two external input output parts 2 and 3, operation control circuits 23 and 33 to detect the condition of the self- and other external input output parts are provided in respective external input output parts, an operation signal is selectively outputted to the shared memory control circuit of respective external input output parts based on the detected result of the operation control circuit and the shared memory of respective external input output parts is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit for performing data communication with an external device, and more particularly to a data transfer system from a central processing unit to an external input / output unit.

[0002]

2. Description of the Related Art Conventionally, in a data transfer for transmitting data from a central processing unit to an external device, when the external device has a dual system external input / output unit, each external input / output unit is used for data transfer. A method is adopted in which shared memories are provided, these shared memories are used as different addresses, and the shared memories are selected to select the shared memory. in this case,
In order to select each shared memory, the central processing unit determines the state or load state of the external input / output unit to determine which of the two external input / output units to use by software.

[0003]

In such a conventional data transfer method to an external input / output unit, since the central processing unit determines the input / output unit to be used by software, the number of decision branches of software increases, There is a problem that the processing of the central processing unit increases and the processing becomes complicated, and the processing speed decreases. An object of the present invention is to provide a data transfer system that reduces the processing of the central processing unit, simplifies the processing, and improves the processing speed.

[0004]

According to the data transfer method of the present invention, an operation control circuit for detecting the states of self and the other external input / output unit is provided in two external input / output units to which data is transferred from a central processing unit. And is configured to selectively output an operation signal to the shared memory control circuit of each external input / output unit based on the detection result of this operation control circuit.

[0005]

According to the present invention, the operation control circuit detects the states of the two external input / output units, selects the shared memory of each external input / output unit based on the detection result, and executes the data transfer.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The central processing unit 1 of the central processing unit and the two external input / output units 2 and 3 of the external device are connected via a shared bus 4. The external input / output units 2 and 3 have the same configuration, and the shared memories 21 and 3 in which the data from the central processing unit 1 are written.
1 and the shared memory control circuits 22 and 32 that output the selection signal to the shared memories 21 and 31 when the higher address of the shared bus 4 and the self address are compared and coincide with each other, and the self is in an operating state. It is composed of operation control circuits 23 and 33 that perform exclusive control of addresses with the other external input / output unit and output operation signals to the shared memory control circuit.

Here, the operation control circuits 23 and 33 are configured to be able to input and output signals to each other, diagnose the operation state of each external input / output unit 2 and 3, and based on the result, the shared memory control circuit. An operation signal is output to 22 and 32. For example, the operation control circuit 23 of the external input / output unit 2 performs an abnormality diagnosis of the external input / output unit 2, outputs an operation signal when there is no abnormality and the operation control circuit 31 of the external input / output unit 3 is not in the operating state, By the switching command from the central processing unit 1, the operating state can be switched when both external input / output units are normal.

The data transfer operation in the above configuration is shown in FIG.
This will be described with reference to the flowchart of. In the initial state, the external input / output unit 2 is in the operating state (201), the external input / output unit 3 is in the non-operating state (301), and the shared memory data transfer (101) from the central processing unit 1 is to the external input / output unit 2. Then, data is transmitted from the external input / output unit 2 to the outside (202). After the shared memory data transfer is completed, the central processing unit 1 issues an operation state switching command (102), the external input / output unit 2 becomes non-operational state (203), and the external input / output unit 3 becomes operational state (302). The next shared memory data transfer (103) from the central processing unit 1 is performed to the external input / output unit 3, and data is transmitted from the external input / output unit 3 to the outside (303).

[0009]

As described above, according to the present invention, the operation control circuits provided in the two external input / output sections detect the states of the external input / output sections, and based on the detection results, the external input / output sections of the respective external input / output sections are detected. Since the shared memory is selected and the data transfer is executed, it is possible to select two external input / output units without the central processing unit making a determination, and it is possible to reduce the processing of the central processing unit.

[Brief description of drawings]

FIG. 1 is a block diagram of a data transfer configuration for executing a data transfer method of the present invention.

FIG. 2 is a flowchart showing a data transfer system of the present invention.

[Explanation of symbols]

 1 Central Processing Unit 2, 3 External Input / Output Unit 21, 31 Shared Memory 22, 32 Shared Memory Control Circuit 23, 33 Operation Control Circuit

Claims (1)

Claim: What is claimed is: 1. A data transfer system in which a central processing unit and two external input / output units are connected by a shared bus, and a shared memory provided in each external input / output unit is selected to transfer data. In the above, each of the external input / output units is provided with an operation control circuit that detects the state of self and the other external input / output unit, and based on the detection result of this operation control circuit, the shared memory control circuit of each external input / output unit is A data transfer method characterized in that an operation signal is selectively output.