JPH0612340A - Memory circuit - Google Patents

Abstract

PURPOSE:To shorten the diagnostic time of the memory circuit which has plural RAM elements. CONSTITUTION:The memory circuit has an operation mode switching signal generating circuit 3 which generates a signal for switching the operation of the memory circuit between diagnostic operation time and normal operation time, a chip selector circuit 4 which sends out a CS signal to all the RAM elements 7-10 at the same time, and a diagnostic result deciding circuit 6 which decides whether or not all data read out of all the RAM elements 7-10 at the same time match one another and also decides whether or not written data also match one other when the read data match one another; and the transmission destination of the data read out of the respective RAM elements 7-10 are switched to a connection with the diagnostic result deciding circuit 6 at the time of a diagnosis or a connection with a data base 12 at the time of normal operation, and then the RAM elements are diagnosed at the same time to shorten the diagnostic time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit using a plurality of RAM elements.

[0002]

2. Description of the Related Art Conventionally, in this type of memory circuit, read and write operations are switched by a WE (write enable) signal, a RAM element is selected by a CS (chip selector) signal, and a memory cell is selected by an address signal. ing.

At the time of write operation, the RAM selected by decoding the higher order of the address signal sent from the CPU
The CS signal is transmitted to the element, the lower order is transmitted to the RAM element to select the memory cell, and the CPU transmits the WE signal to the RAM element to write the data.

During the read operation, the RAM element and the memory cell are simultaneously selected, and the CPU sends the RE signal to the RAM element to read the data.

[0005]

In the above-mentioned conventional memory circuit, since the RAM element is selected by the CS signal, only one RAM element can be written by the write operation or the read operation at 1 o'clock. Memory cells.

For this reason, the memory diagnosis is performed by writing data to all memory cells of all RAM elements one by one, and then executing all R
A method of reading the data of all the memory cells of the AM element one by one and confirming the match between the write data and the read data has been adopted.

According to this method, the diagnosis time becomes longer as the memory capacity increases, and particularly, due to the recent introduction of a large scale memory, a huge diagnosis time is required.

An object of the present invention is to provide a memory circuit which can shorten the diagnosis time.

[0009]

In order to achieve the above object, a memory circuit according to the present invention comprises a plurality of RAM elements, and an address and data signal common to each RAM element is provided between each RAM element and a CPU. And a RE (read enable) signal and a WE (write enable) signal for controlling the read operation and the write operation of each RAM element,
Further, CS for selecting each RAM element individually
In a memory circuit having a (chip selector) signal, an operation mode switching signal generation circuit that transmits a signal for switching the operation of each circuit between diagnosis and normal time to each circuit, and a CS signal to all RAM elements at the same time during diagnosis. It is determined whether the chip selector circuit to be transmitted and the data read from each RAM element at the time of diagnosis all match, and if they match,
Further, it is determined whether or not the data matches the written data and the result of the diagnosis is sent to the CPU, and the destination of the data read from the RAM element is switched to the connection of the diagnosis result at the time of diagnosis. In some cases, it has a gate selection circuit for switching to connection with a data bus.

[0010]

By simultaneously diagnosing a plurality of RAM elements, the memory diagnosis time is shortened.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a memory circuit having a memory composed of four RAM elements according to an embodiment of the present invention.

In the figure, a CPU 1 and RAM elements 7-1 are provided.
0 are connected in parallel by an address bus 11 and a data bus 12, respectively, and the data bus 12 and the RAM elements 7 to
One gate selection circuit 26 to 29 is provided between 10 and each gate selection circuit 26 to 29 is connected to the diagnosis result determination circuit 6 by an independent signal line.

The WE signal and the RE signal sent from the CPU 1 are sent to the RAM element 7 by the signal lines 15 and 16, respectively.
10 are connected in parallel to each other, and an address signal sent from the CPU 1 is connected to the chip selector circuit 4 and the operation mode switching signal generation circuit 3 by a signal line branched from the address bus 11, and the chip selector circuit 4 is RA
The M elements 7 to 10 are connected by independent signal lines 17 to 20, respectively.

The operation mode switching signal generating circuit 3 is connected in parallel to the chip selector circuit 4, the gate selecting circuits 26 to 29, and the write data gate 22 by a signal line 14, respectively.

The diagnostic write data generation circuit 2 includes RAM elements 7-1 through the write data gate 22, the signal line 13, and the diagnostic result determination circuit 6 and the data bus 12.
0, and the diagnosis result judging circuit 6 is connected to the CPU 1 through the data bus 12.

The diagnostic write data generating circuit 2 and the operation mode switching signal generating circuit 3 have IOW 23 and IO, respectively.
W24 is connected.

Next, the operation will be described. When the diagnosis start signal is input from the IOW 24 to the operation mode switching signal generation circuit 3, the chip selector circuit 4 and the gate selection circuit 26 are input.
To 29 and the write data gate 22 are transmitted to the chip selector circuit 4, the chip selector circuit 4 sends CS signals to all the RAM elements regardless of the address signal from the CPU 1, and the gate selection circuit 26 to.
29 sends the data read from the RAM elements 7 to 10 to the diagnosis result judging circuit 6 instead of the data bus 12, and the write data gate 22 opens the gate and outputs from the diagnostic write data generating circuit 2. The signal of is transmitted to the RAM elements 7 to 10 and the diagnostic result determination circuit 6 in a transmittable state.

Next, when an address signal is sent from the CPU 1, the higher order of the address signal is sent to the chip selector circuit 4, and at the time of diagnosis, a CS signal is sent to all the RAM elements 7 to 10 via the signal lines 17 to 20. , Lower is RAM element 7-
10 are addressed to the memory cells that are common to all RAM elements.

At this time, the W from the CPU 1 is written to all the RAM elements.
When the E signal and the data from the diagnostic write data generating circuit 2 are transmitted, since the CS signal is transmitted to all the RAM elements, the same data is written in the same cell address of all the RAM elements 7-10.

When the writing operation to the RAM element is completed, C
The same address signal and RE signal are transmitted from PU1,
Data of a common cell address is read out from all the RAM elements at the same time and transmitted to the gate selection circuits 26 to 29.

In the gate selection circuits 26 to 29, the signal indicating the diagnostic mode is transmitted from the operation mode switching signal generation circuit 3, so the data read from the RAM elements 7 to 10 are transmitted to the diagnostic result determination circuit 6. To do.

In the diagnosis result judging circuit 6, the same data as the data written in all the RAM elements is transmitted,
When the data read out from all the RAM elements is transmitted while holding it, first of all, it is detected as a first judgment whether or not all the transmitted data are “0” or “1”. If they match, the next second determination is performed. If they do not match, a memory failure is detected, and a signal indicating a memory failure is transmitted to the CPU 1 via the data bus 12.

If all the data match in the first judgment, it is judged in the second judgment whether the data transmitted from the RAM element and the held write data match. If they match, a signal indicating that the diagnosis result is normal is detected. If they do not match, a failure in the common circuit is detected and a signal indicating the common circuit failure is sent via the data bus 12 to C
Send to PU12.

When the diagnosis is completed by simultaneously writing and reading the common cell addresses of the plurality of RAM elements, the IOW 24 inputs a diagnosis end signal to the operation mode switching signal generating circuit 3. . At this time, the operation mode switching signal generation circuit 3 transmits a signal instructing the operation in the normal state to the chip selector circuit 4, the gate selection circuits 26 to 29, and the write data gate 22, and the chip selector circuit 4 receives the address signal. The CS signal is transmitted only to the selected RAM element by decoding the upper part of the gate selection circuits 26 to 29.
The data read from the AM elements 7 to 10 is transmitted only to the data bus 12, and the write data gate 22 closes the gate to return the operation of this circuit to the normal state and complete the diagnosis.

[0025]

As described above, the present invention has the effect that the memory diagnosis time can be shortened by simultaneously diagnosing a plurality of RAM elements in the memory diagnosis.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 CPU 2 Diagnostic Write Data Generation Circuit 3 Operation Mode Switching Signal Generation Circuit 4 Chip Selector Circuit 5 Normal / Diagnostic Route Switching Circuit 6 Diagnostic Result Judgment Circuit 7 to 10 RAM Element Group 11 Address Bus 12 Data Bus 13 Diagnostic Write Data Bus 14 Operation mode switching signal line 15 WE (write enable) signal line 16 RE (read enable) signal line 17 to 20 CS (chip selector) signal line 21 Read / write switching gate 22 Write data gate 23 to 24 IOW 26 to 29 Gate selection circuit

Claims (1)

[Claims] 1. A RA comprising a plurality of RAM elements.
An address and data signal common to each RAM element between the M element and the CPU, an RE (read enable) signal for controlling the read operation and the write operation of each RAM element, and W
CS (chip selector) which has an E (write enable) signal and further selects each RAM element individually
In a memory circuit that has signals, an operation mode switching signal generation circuit that sends a signal to each circuit to switch the operation of each circuit between diagnostic and normal, and a chip selector that simultaneously sends a CS signal to all RAM elements during diagnostics The circuit and the data read from each RAM element at the time of diagnosis are checked to see if they all match, and if they match, it is judged whether they match the written data.
It has a diagnostic result judgment circuit for transmitting to U, and a gate selection circuit for switching the destination of the data read from the RAM element to the connection with the diagnostic result judgment circuit during diagnosis and to the connection with the data bus during normal operation. Memory circuit characterized by.