JPS60109100A - Bit system defect detection system of semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect automatically a defect of static type memory by generating high-potential and low-potential inspection signals in a semiconductor memory device, one by one, and detecting a defect of a bit system with the inspection signals. CONSTITUTION:An inspection signal generating circuit 8 sends a high-potential signal to an input circuit 5 through an information input/output line 9 with a signal from a timing generating circuit 7, and the circuit 5 drives respective bit lines of a static cell type memory array 2 at a time through a bit line selecting circuit 3. The bit lines when normal are at a high and a low potential alternately. A defect detecting circuit 1 uses twi exclusive OR circuits to detect a defect of a bit line. The signal from an information output circuit 4 is compared by a defect detecting circuit 6 with the signal from the line 9 to detect defect states of the circuits 4 and 5 and line 9. Then, when an inspection signal is at the high potential, whether the bit system is defect or not is detected on the basis of the detection results of the circuits 1 and 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for automatically detecting defects in a bit system within a semiconductor memory device that occur during the manufacturing process of the device.

Prior Art Conventionally, when detecting defects that occur during the manufacturing process of semiconductor memory devices, a test pattern is input from an external prototype device, the test data (9) is compared with the input test pattern, and the result is According to this method, it is necessary to test all bits of the memory, so as the bit capacity increases, the test time increases.
Further, there was a drawback that it was necessary to separately prepare a test drive device N for testing.

Furthermore, as the t6 capacity has increased in recent years, defects occurring during the manufacturing process can no longer be ignored in terms of manufacturing yield.

For this reason, a method has been adopted in which the memory array is switched to a spare memory array after the test, and there has been a desire for a method that can perform inspection and detection of defects automatically and easily.

OBJECTS OF THE INVENTION The present invention generates two test signals of high potential and low potential within a semiconductor memory device, and detects p-bit system defects using these test signals. Its purpose is to automatically detect defects in static memory.

Structure and operation of the invention The structure and operation of the present invention will be explained below along with examples.

FIG. 11 shows an embodiment of the present invention, in which 1 is a first defect detection circuit, 2 is a static cell type memory array, 6 is a bit line selection circuit, 4 is an information output circuit, 5 is an information input circuit, 6 is a second defect detection circuit, 7 is a timing generation circuit, 8 is an inspection signal generation circuit, 9 digits 11'] information input/output line, 1
0 is a bit ffD selection signal line group.

Although not shown in the figure, the timing generation circuit 7 sends a signal to a known address buffer circuit, etc., to stop word-related operations, that is, to deselect all word errors, and to The bit line selection circuit 6 is activated by the i-segment line group 10, and the label pin is selected.
Set the selection switch to the off position.

The test signal generation circuit 8 which receives the signal No. 45 from the timing generation circuit 7 outputs a high potential signal to the information input/output line 9.

The information input circuit 5 receives this signal and inputs information to the memory cells of the static cell type memory array 2.
Each bit line of the memory array is driven simultaneously via the bit line selection circuit 3.

At this time, if there are no defects in each circuit and bit line, the potential of every other bit line changes to high or low potential because the memory array is of a static cell type. These potential states are each input to the first defect detection circuit 1.

The first defect detection circuit 1 includes two sets each of an AND circuit and an OR circuit that use every other bit line as an input line, and a circuit that takes an exclusive OR of the outputs of these circuits. Defects can be detected by ORing the outputs of the exclusive OR circuit. That is, defects that fix the potential of the bit line, such as circuit malfunction, bit line disconnection, short circuit between lines, high potential short termination, and low potential short termination, can be detected (first defect detection signal a). In order to detect a short circuit between bit lines using this method, it is necessary to design the output stage of the information input circuit 5 to have a low potential with respect to a short circuit between lines. An example of the logic circuit of the first defect detection circuit 1 is shown in FIG. Numeral 11 is a logic circuit, 12 is a logical sum circuit, and 13 is a logical sum circuit, in which bits, bits, and %t are connected every other line.

Furthermore, the information input circuit 5 when the timing generating means sets the test signal of the test signal generating means to a high potential.
(originally a differential signal in which one is H and the other is L) is input to the alarm output circuit 4 via lines 11 and 12, and its output (i and the test signal generation circuit 8 By inputting the resulting signal of the information input/output line 9 to the second defect detection unit 11 and comparing it with an appropriate means such as an exclusive logic circuit, the information output circuit 4.1 signal input circuit 5 and the information input circuit 5 The defect state of the output line 9 can be detected (second defect detection No. 46 b). From this detection A:jj result and the detection result of the first defect detection circuit 1, when the inspection signal is high 111, The presence or absence of bit system defects can be detected (output C).

Continuing, even when the test signal is at a low potential, the above procedure 'f:
By repeating this, it is possible to detect the presence or absence of a defect when the inspection signal is at a low potential (sixth defect detection circuit, fourth defect detection No. 11).

It should be noted that it is clear that various changes can be made to rearrange the logic used for detection, change the timing sequence, etc. without departing from the spirit of the present invention.

As described in detail, the present invention has the great effect of being able to inspect and detect defects automatically within the semiconductor memory device without requiring a separate testing device. is obtained. Then, a memory device consisting of a plurality of memory arrays is configured by using the memory array described in the present invention and the bit system connected thereto as one repeating unit,
When a bit system defect is detected, the detection signal is used to transfer the defective memory array from memory array]b- to TB.
'A can be separated. Therefore, by having several spare memory arrays for the required memory capacity, it is possible to provide a memory device that always has a normal capacity system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a logic diagram of the first defect detection circuit shown in FIG. DESCRIPTION OF SYMBOLS 1... First defect detection circuit, 2... Static cell type memory array, 6... Bit line selection circuit, 4...
・Information output circuit, 5...information input circuit, 6...second
defect detection circuit, 7...timing generation circuit, 8...
・Inspection signal generation circuit, 9... Information input/output line, 10...
・Bit line selection signal line group, 11...AND circuit, 12
...Exclusive OR circuit, 16...OR circuit. Patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Gobe Tamaichi Mushiku (2 others) Figure 1 Figure 2 Figure 1

Claims (1)

[Claims] Static memory array, information input means, information output means connected to the memory array, P&R
selection means, test signal generation means, timing generation means, first
and the second defect detection means are respectively set to ``Iff'', the timing generation means makes all the selection switches of the bit line selection means conductive, and the test No. 46 of the inspection signal generation means is set to a high potential. A first defect detection signal obtained by inputting it to the information input means and inputting the potential state of each bit line of the memory array at this time to the first defect detection means, and the timing generation means. Inspection of the inspection signal generating means (H is set to high)
inputting the output of the information input means when the position is about fij into the information output means and the inspection signal of the inspection signal generation means, and inputting it into the second defect detection means;
(2) obtaining the defect detection signal of step 2, and inputting the inspection signal of the inspection signal generation means to a low potential by the timing generation means to the information input means; A third defect detection signal obtained by inputting the potential state to each of the first defect detection means, and an information input circuit when the timing generation means sets the inspection signal of the inspection signal generation means to a low potential. A fourth defect detection item No. 43 is obtained by inputting the output of the circuit to the information output circuit and inputting the output signal and the inspection signal of the inspection signal generating means to the second defect detection means. A human-based defect detection method for semiconductor memory devices.