JPS62128098A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the time needed for a test by executing a parallel processing to write and read it simultaneously to plural cell blocks in the internal part of a tip. CONSTITUTION:A memory array MA is divided into four logically independent cell blocks BL0-BL3, and to respective cell blocks, input/output lines IO0-IO3 and d0-d3 and amplifying circuits PA0-PA3 are provided. Cell blocks BL0 and BL2 without physical interference are integrated as one cell block group, and in the same way, BL1 and BL3 are another cell block group. Respectively, an input/output circuit, namely, input buffer circuits DIB0 and DIB1 and output buffer circuits DOB0 and DOB1 are provided, to respective cell block groups, independent input signals Din and Dinl are written and independent output signals Dout and Doutl can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for improving the efficiency of memory chip testing.

[Conventional technology]

A problem associated with increasing the capacity of semiconductor memories is an increase in test time required for chip operation tests performed during wafer inspection, shipping inspection, or acceptance inspection. For example, when considering a test using a simple write/read cycle, if the memory capacity quadruples, the test time also quadruples.

The more complex the test pattern, the greater the rate of increase in test time. An increase in test time leads to an increase in the cost required for testing, and thus an increase in the manufacturing cost of the chip. For these reasons, there is a strong desire to improve the efficiency of chip testing.

In contrast, conventionally, there is a multi-bit parallel test method as described in IEICE Technical Report, Vol. 85, No. 42 (May 1985), pages 7 to 12. This conventional method will be explained using FIG. 2.

FIG. 2 shows a circuit block diagram of a memory using a parallel test method for multiple bits (4 bits in the figure). This circuit configuration has write/read operations in two modes, a normal operation mode and a test mode, and switching between both modes is controlled by a test control signal TE.

First, read and write operations in normal operation mode will be explained. In the read cycle, one bit is read from each of the four cell blocks BLo=BLa constituting the memory array MA according to an address signal input from the outside.
A total of 4 bits of data is connected to 4 input/output lines l0o=I○δ
The amplified signal is read out to the input/output line do”d and amplified by the amplifier circuit P A o” P A a.
It is output to a. On the other hand, due to address signals Ai and Aj,
The input/output line selection circuit turns on one of the four selection switches SWO, and connects one of the four input/output lines do=d3, for example do, to the common input/output line d+a. In the normal operation mode, the switch SW2 is connected to the terminal 1 by the test control circuit TEC, and the data output to the common input/output line d+o is output as an output signal via the output buffer circuit DOB. It becomes ut. In this way, one bit of information in the memory array configuration is read out from the chip. In the write operation, the input buffer circuit DIB is activated by the write control signal WE via the write control circuit WRC, and the input signal DIIl is connected to the common input/output line dto and the switch SWO (one of the four is conductive as in the read operation). state), is written into one memory cell via input/output lines do and IOo.

Next, write/read operations in the test mode are performed as follows. First, in the write operation, all four switches of the selection switch SWO are made conductive via the input/output line selection circuit by the test control signal and the write control signal, and the input signal D111 is simultaneously written into the memory cells of each block. Therefore, in the sixth read operation in which the same data is written to four memory cells simultaneously and in one write cycle, 4-bit data is written to the input/output line do'' as in the normal operation mode.
These data are read out to the judgment circuit LO
It is input to G. The output A of this determination circuit is input to the output buffer circuit DOB via the switch SW2 connected to the terminal 2 by the test control signal TE,
An output signal Dout is output. 4-bit data input to the judgment circuit LOG and output signal. The relationship between ut is
In the above-mentioned literature, all 4-bit data is “H”.
When all the 4 bits of data are “Low”, Douc is also set to “Low”, and if even 1 bit of the 4 bits of data do not match, Dout is set to “High”. This setting allows a tester outside the chip to determine whether the 4-bit data is correct or incorrect.

In this test mode, externally applied data is simultaneously written to four cell blocks.

When reading, the same data written in these cell blocks is read out simultaneously. In other words, since four cell blocks are processed in parallel, the memory capacity is 1 from outside the chip.
It can be regarded as a /4 memory, reducing test time.

In FIG. 2, AB represents an address buffer circuit.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has been applied to the memory array configuration described in Japanese Patent Application Laid-Open No. 57-198592, that is, as shown in FIG. M A 1
), and data mDL and input/output a in each subarray.
Connect the connection switch SW3 with I○ to one end of the memory array.
When applied to a memory array configuration in which each subarray is commonly controlled by the output signal line YS of only one Y decoder YDEC, the following disadvantages arise. In this memory array configuration, as shown in FIG.
is not provided for each switch SW3, but one YS is provided for each two adjacent switches, and this one Y
A method is adopted in which two switches are controlled simultaneously by S.

This technique reduces the size of a part of the memory array by reducing the number of YSs passing through the memory array, thereby increasing the degree of integration, and is becoming an essential technique for obtaining a high-density memory chip.

In this method, 2 bits of data are simultaneously transmitted from each subarray to the input/output lines I, which are provided in each subarray.
Read out to O. Therefore from the two subarrays 4
Bit data can be read simultaneously, and conversely, 4-bit data can be written simultaneously.
Testing time can be reduced by processing bits in parallel using the conventional techniques described above. However, in this memory array configuration, among the four cell blocks, the cell blocks connected to the input/output lines IOo and I01 are each configured by memory cells connected to adjacent data lines in the layout, so they are logically independent. However, they are not physically independent cell blocks.

i.e. interference between adjacent memory cells and data lines.

This is because there is physical interference between cell blocks due to interference between input and output paths such as input and output lines, and short circuits. This interference between cell blocks similarly occurs between cell blocks connected to the input/output line 102°IOa. On the other hand, the above-mentioned interference does not occur between the cell blocks connected to the input/output lines IOo, IO2, and IOa, and between the cell blocks connected to the IO line and IO2°IOs, because each belongs to a subarray divided in terms of layout. When the conventional technique is applied to such a memory array configuration divided into cell blocks, the conventional technique of simultaneously writing the same data into four cell blocks cannot detect the above-mentioned interference between the cell blocks. In particular, even if the input/output path of a cell block is short-circuited, this short-circuit cannot be detected, and a defective chip may be determined as a non-defective chip.

An object of the present invention is to provide an optimal test method for a memory array configuration consisting of cell blocks that are logically independently divided as described above but are not independent due to some kind of physical interference. be.

[Means for solving the problem] The above purpose is to combine cell blocks that are independent from each other without physically interfering with each other out of a plurality of cell blocks constituting a memory array into one cell block group. This is achieved by dividing the memory array into a plurality of cell block groups, providing each cell block group with an independent input/output circuit, and performing parallel processing of writing/reading multiple bits for each cell block group.

[Effect]

In test mode, data is written to or read from each cell block simultaneously, but this writing and reading is performed by an input/output circuit provided for each cell block group, and independent data writing is performed between each cell block group. , performs reading. As a result, independent data writing between cell blocks with physical interference,
Since readout is possible, operational effects due to physical interference can be detected. Furthermore, as in the prior art, parallel processing for simultaneously writing and reading multiple bits is performed inside the chip, so the time required for testing can be reduced.

〔Example〕

The present invention will be explained below with reference to Examples.

FIG. 1 shows one embodiment of the present invention. Memory array MA
are four logically independent cell blocks BLo"BLg
Each cell block has input/output lines Zoo~IOs, do~d8 and amplifier circuit PAo.
``PA3 is installed.

Among these four cell blocks, cell blocks BLo and BLz, and BLz and BL3 are cell blocks with physical interference, respectively. The input/output line do=da is connected to the common input/output line d+o via the selection switch SwO. In addition, do and dz are input to one judgment circuit LOGo,
Also, ctl, da is another judgment circuit LOG!
becomes the input. Further, these pairs of input/output lines are connected to input buffer circuits D I Bo, D via switches SWI.
I Bz respectively. The output AO switch of the determination circuit is connected to the output buffer circuit D OB o via SW2.
and the other output A1 is also connected to the output buffer circuit D.
This is the input for OB t. The switch SWO connects one of the four input/output lines clO-da selected by the address signals Ai and A, and the common input/output line d+o in the normal operation mode. selection circuit l
Controlled by 0DECI. Switch SWI sets input/output lines do and dz to 1 during write operation in test mode.
one input buffer circuit DIBo, and another input buffer circuit dz and dδ.
It is connected to two input buffer circuits DIBz and is controlled by an input/output line selection circuit l0DHCI. Other parts with the same reference numerals as in FIG. 2 represent the same things.

In FIG. 1, cell blocks BLo and BL2 without physical interference are treated as one cell block group, and similarly BLr and B
L3 is another cell block group, and each has an input/output circuit, that is, an input buffer circuit DIBo, DIB1.
．． An output buffer circuit D OB o +D OB 1 is provided, and independent input signals D+n and DIl11 can be written to each cell block group, and independent output signals [1 oul and D out s can be obtained. The operation shown in FIG. 1 will be explained below.

First, write and read operations in the normal operation mode will be explained. In normal operating mode, the test control signal T
E causes switch SWI to become non-conductive and switch S
W2 is now connected to terminal 1. In a write operation, the input buffer circuit DIB is controlled by the write control signal WE.

is activated, and the input signal Dln is applied to the common input/output line d+.

is input. The data input to this dto is sent to the input/output line selection circuit l0DEC according to the address signals Ai and Aj.
is input to one of the input/output lines do=da through one switch SWo selected by I,
Further, the data is written into a memory cell selected by an address signal within one cell block via the amplifier circuit PA and the input/output lineman ○.

In the read operation, data is read out from the memory cell selected by the address signal to the input/output line for each cell block, and is sent to the input/output line via the amplifier circuit PA.
d is output to a. Of these four signals, address signal A
One input/output line corresponding to i, Aj is connected to the common input/output line dxo via SWO, and further connected to the output buffer circuit DOB0 via switch SW2, and the one input/output line corresponding to memory cells in one cell block is connected to the common input/output line dxo via SWO. Data is the output signal Do
It is output as ut.

Next, write and read operations in the test mode are performed as follows. In the test mode, all the switches SWO are rendered non-conductive and the switch SW2 is connected to the terminal 2 by the test control signal TE.

First, in a write operation, a write control signal activates the input buffer circuits DIBo and DIBr, turns on the switch SWI, and makes the input signal D
l n and D + n s as input/output lines do, respectively.
dz and dt, input to d3, and further input to the amplifier circuit PA,
Data is written to the memory cells selected by the address signals in each cell block via the input/output BTO. In this way, the memory cells in the four cell blocks are written simultaneously, but the input signal Dsn is applied to the memory cells in the cell blocks BLo and BLz.
, B The input signal DIr11 is written into the memory cell in La. Next, in a read operation, a signal is read from the memory cell in each cell block selected by the address signal to the input/output line IO, amplified by the amplifier circuit PA, and then output to the input/output line do=d3. . input/output line do
, d2 are written as the same data in a write operation, and must be the same data in a normal operation. The same applies to the data output to the input/output lines dx and da. These data are input to the judgment circuit LOG as explained in FIG. 2, and it is judged whether they match -a or not. , respectively output signal. Output as ut and Doutt. In this way, the data in the four cell blocks are read simultaneously.

According to this embodiment, writing or reading can be performed simultaneously on four logically independent cell blocks, thereby reducing test time. Moreover, two cell block groups (
BLO, BL2) and (B Ll.

A cell block BL in which independent data can be written into and read out from BLa) and there is physical interference.

Interference between and BLz or BL2 and BLa can be detected. Note that in the embodiment shown in FIG.
Writing to input/output lines do and d2 in test mode is as follows:
Input/output line selection circuit 10DEC without using switch SWL
By devising the control of I, it is also possible to perform this via the switch SWO. In this case, the switch SWI may be two switches connected to the input/output lines dt and ds. Further, in the embodiment shown in FIG. 1, the number of cell blocks is four and the number of cell block groups is two, but these numbers can be appropriately selected for the semiconductor memory device.

Furthermore, the cell blocks shown in the same figure are logically divided, and are not necessarily the same as the divided subarrays in terms of layout.
It is not a one-to-one correspondence. An example in which the present invention is applied to a more specific memory array configuration will be shown below.

FIG. 4 is a more specific example of the embodiment shown in FIG.
This is an example in which the present invention is applied to the memory array configuration shown in FIG. 3. In the memory array configuration shown in the figure, as described above, the cell block belonging to the input/output line IOo and the cell block belonging to the input/output line IOz are logically independent cell blocks due to the addresses A i and A j . , the memory cell MC data line DL and the amplifier circuit SA which are selected at the same time are arranged adjacently.
In addition to hard errors such as short circuits in data lines, physical interference such as interference between memory cells and capacitive coupling between data lines and input/output lines can be considered, and malfunctions may also occur due to these. Input/output line■02. The same applies to cell blocks belonging to IOs. Therefore, in this embodiment, the input/output line I
The cell blocks belonging to Oo and IO2 are set as one cell block group, and the cell blocks belonging to IO1 and 08 are set as another cell block group, and as explained in FIG.
It is now possible to write independent data into these cell block groups. Thereby, the above-mentioned physical interference between cell blocks can be detected. Although FIG. 4 shows an example in which an amplifier circuit SA is provided for each data line, it is also possible to omit this amplifier circuit and directly amplify the signal read out to the data line by the amplifier circuit PA.

FIG. 5 shows another embodiment of the invention. The embodiment shown in FIG. 4 shows an example in which one subarray is divided into two cell blocks, but in this embodiment, four cell blocks are connected to switch SW3 of each subarray using one Y decoder output signal line YS. An example is shown in which the switches are commonly controlled and each subarray is divided into four cell blocks. In this case, as shown in the figure, one cell block is taken out from each subarray and is made into one cell block group. For example, cell blocks belonging to input/output, &ll0o, and number 10 are set as one cell block group.

This is an example in which the number of cell block groups is four in this manner.

FIG. 6 shows another embodiment of the present invention in which the memory array is divided into four subarrays, and each subarray is further divided into two cell blocks. The case where the number of groups is two is shown.

FIG. 7 shows another embodiment of the invention. Memory array MA
The division and configuration of is similar to the embodiment shown in FIG.
The behavior is different. That is, in the embodiment shown in FIG.
There are one sub-array SM A.

One word line is selected in each of ~SMAs, and four subarrays are activated simultaneously.

Therefore, 8-bit data is simultaneously read from memory array MA. Conversely, 8-bit data is written simultaneously. In the embodiment shown in Figure 7, only two of the four subarrays are activated at the same time, and the remaining subarrays remain in a standby state. Such an operation can occur in a dynamic memory due to the relationship between the number of refresh cycles and the number of subarrays. For example, in the case of a 1M bit memory, if the number of refresh cycles is 512, the number of memory cells activated simultaneously is 2048. In the memory array configuration shown in FIG. 7, if the number of memory cells connected to one word line is 1024, only two word lines need to be selected at the same time. Therefore, 4-bit data is simultaneously read from memory array MA. FIG. 7 shows the present invention applied to a memory array configuration operating in this manner. In the figure, there are four subarrays S
M A o = Among S M A s, only SMAo and S M A z or S M A are activated at the same time.
s and S M A a. Switch SW 7 o
, S W 7 l is the input/output line selection circuit l0DEC2
Only the input/output lines connected to the two activated sub-arrays, ie, the four cell blocks, are connected to the switch swi and the determination circuit LOG. Switch 5W7o shown in FIG.

The status of SW 71 is subarray S MAI, S
This shows the case where MAll is activated, and d2. da+ d6. d7 is connected to the switch SWI and the determination circuits LOGo and LOG1.

In this way, the present invention can also be applied to a memory array configuration in which only some of the cell blocks constituting the memory array are activated at the same time.
The effects described in FIG. 1 can be obtained.

FIG. 8 shows another embodiment of the invention. Although the memory array configuration in which cell blocks are partially activated has been described in FIG. 7, in the embodiment shown in FIG. The aim was to increase the number of bits to be tested and further shorten test time. For this purpose, in this embodiment, the switches S W 8 o and S W 8 t controlled by the input/output line selection circuit l0DEC3 are used.
, SW 8 x , SW 8 a and SW9 are provided. Further, a second test control signal device is added as a signal for controlling the number of cell blocks activated in the test mode. The operation shown in FIG. 8 will be briefly explained below. First, as in Fig. 7, four subarrays S M
A case will be described in which two subarrays, that is, four cell blocks of Ao to SMAa are activated. In this case, two word lines, for example W 1 and Wa, are selected by the X decoder XDEC, and the sub-array 5MAl is selected.

S MAs are activated. At this time, the input/output line selection circuit 10DEC3 selects the switches SW 8 o,
SW82 and SW9 become conductive, and switch S
W 8 I.

S W 8 s becomes non-conductive. Also, subarray S
When M Ao and S M Az are activated, the switches SW 81 , SW 8 g and SW9 are made conductive, and the switches SW 8 o and SW 8 are turned on.
2 into a non-conducting state. Switch SWO, SWI, SW
2 operates in the same way as the embodiment described in FIG. By controlling the switches in this way, only the four activated cell blocks are connected to the input buffer circuit D.
IBo, DIBz and judgment circuit I, OGo, L OG
t, and 4-bit parallel processing is performed. Here, the switch SW9 is connected to the judgment circuit LOG (LOG o
.

By short-circuiting two of the four-manpower circuits of LOG1), it is possible to convert the circuit into a two-manpower judgment circuit. This is because the judgment circuit detects a match between the input 4-bit data.
This is for determining inconsistency, and can be easily converted into a two-man-powered judgment circuit by short-circuiting two human-powered circuits. Next, let's look at the operation when the second test control signal device selects word lines that are multiples (generally multiples) of normal operation using the X decoder and simultaneously activates four subarrays, or eight cell blocks. explain.

In this case, the X decoder
DEC selects four word lines. In addition, the input/output line selection circuit 10DEC3 selects the switch 5W8o.

SW 81, SW 8 x, SW 8
s is made conductive, and switch SW9 is made non-conductive. By setting the switches in such a state, all eight activated cell blocks are connected to input/output circuits such as a manual buffer circuit and a determination circuit, and 8-bit parallel processing can be performed. Therefore, compared to the above-mentioned 4-bit parallel processing operation, the test time can be further reduced. However, in this 8-bit parallel processing operation, the power consumption for the same cycle time increases and the operating speed becomes slower than in normal operation or in the test mode of 4-bit parallel processing. Therefore, it is effective to use two operations depending on the test content, such as using 4-bit parallel processing for tests with short cycle times and 8-bit parallel processing for tests with long cycle times. In this embodiment, memory array MA is divided into four subarrays and eight cell blocks, and four of these cell blocks are activated during normal operation. The number of cell blocks can be appropriately selected for the semiconductor memory device. Furthermore, in the embodiment shown in FIG. 8, an example was shown in which the second test control signal device is applied from outside the chip as a signal for controlling the number of cell blocks activated during the test mode. It is also possible that the problem occurs inside the chip. For example, in the test mode, two of the address signals Ai, Aj, and Ak are essentially unnecessary, so this address signal and the test control signal TE are used to generate a signal that controls the number of activated cell blocks. It's okay.

Several embodiments have been described above, and in these embodiments, the present invention is applied to an example of a memory array configuration described in Japanese Patent Laid-Open No. 57-198592. Moreover, in contrast to a memory array configuration in which each subarray divided in the layout that constitutes memory array MA is composed of different cell blocks, one cell block is a memory array included in only one subarray. The configuration was shown. In other words, using FIG. 4 as an example, the cell block belonging to input/output line ■00 is included in subarray S M A o;
Not included in A1. However, the present invention is not limited to application to such a memory array configuration, and one cell block may be included in a plurality of subarrays. Further, the present invention is also applicable to memory array configurations other than the memory array configuration described in Japanese Patent Application Laid-Open No. 57-198592. In short, the cell blocks may be logically divided and may differ from layout divisions as long as they are mutually independent. - An example is shown in FIG. The memory array shown in FIG. 9 consists of four subarrays SMAoo
It is composed of ySMAoz, SMAzo, and SMAtt, and each subarray has a memory MC and an N-channel MOS.
Amplifier circuit NS consisting of transistors, P channel MOS
Amplifier circuit PS consisting of transistors and data pair line DL
, DLti - is comprised of a precharge circuit PC that precharges to a certain voltage (in the figure, half the value of the power supply voltage Vcc). Memory cell MC is folded d
ata ], ine cells are used, and this is described in I.E., Proceedings, Vol. 130,
Part I, No. 3 (June 1983), pp. 127-135 (IEE).

PROC, voQ, 130. ptl, N(1
3 (June 1983) pp 127-135). Each memory cell is connected to a word line W and a data line DL or DL, and each data line pair DL, D
The aforementioned PC, NS, and PS are connected to L. Now, the operation of the memory array configuration shown in FIG. 9 is as follows.

First, all data lines and drive lines CLoo and CLI of amplifier circuits NS and PS are connected by precharge signal φP.
O, etc. are precharged to Vcc/2. Note that a precharge circuit such as the drive line CLon is not shown in FIG. 9 to simplify the drawing. Next, the X decoder XDEC is
selects one word line for each subarray. As a result, a read signal voltage is outputted from the memory cell MC connected to the word line to the corresponding data line, for example, DL. - No memory cell is connected to the data line DL, which is the power pair, and the precharge voltage is Vcc/
It remains at 2. Next, amplifier circuit drive signals φNO and φPD
is applied, and the drivers ND and PD operate. Correspondingly, NS and PS operate to amplify the minute signal voltage on the data pair line.

After that, a pulse is applied to one output signal aYS by the Y decoder YDEC selected by a plurality of address signals, and the amplified signal on the data pair line is transferred to the input/output pair line IO.
o, completion) ■, etc., and is then further amplified by an amplifier circuit PAo, etc.

A write operation is performed in the reverse path of a read, as is well known.

Now, the difference between the memory array configuration shown in FIG. 9 and the memory array configuration shown in FIG. 4 is that in FIG. into two subarrays S M A o
o v SM A so and an X decoder XDEC is placed between the subarrays. This shortens the length of each word line, reduces the delay time due to word line resistance, and increases the operating speed. In the memory array configuration shown in FIG. 9, cell blocks belonging to each input/output line are included in two subarrays. For example, cell blocks belonging to input/output pair lines IOo and IO□ are included in both subarrays SMAoo and SMA1o. The present invention can also be applied to such a memory array configuration in the same way as the embodiments shown in FIGS. 4 to 8.

FIG. 10 shows yet another memory array configuration. The difference from the memory array configuration shown in FIG. 9 is that the common drive line of the amplifier circuit NS group belonging to sub-array SMAoo (or SMAol) and the sub-array SM AI
Connect the common drive line of the amplifier circuit ps group belonging to SM A oo (or SMAtt), and connect the common drive line of the amplifier circuit 28 group belonging to SM A oo and the common drive line of the amplifier circuit NS group belonging to SM A 10. This is where the wires are connected. Accordingly, each common drive line CLoo.

Drivers ND and PD are provided for CLIO, etc.

The operational characteristics of this memory array configuration are the X decoder
Subarrays SMAoo and SMAzo sandwich EC.

The purpose is to select only a word line belonging to one of the subarrays of SMAOI and SMAtz, and activate only the amplifier circuit group belonging to the selected word line without increasing the number of common drive lines. Therefore, there is an advantage that the transient current flowing through the common drive line during read signal amplification can be reduced, and the wiring width of the common drive line can be reduced.

The operation of this memory array configuration begins with the X decoder XDEC.
, one subarray, e.g. S MAoo, S
A word line belonging to MAoz is selected, and a read signal voltage is output from the memory cell to the data pair lines in sub-arrays S_MAoo and S_MAO1. Next, when a pulse is applied to φNDI, the common drive lines C, Lzo, and CLz are driven by ND, thereby activating the amplifier circuit NS and amplifying the data line in the direction of discharging. Further, when a pulse is applied to φPD1, the common drive lines CLoo and CLOI are driven by PD, thereby activating the amplifier circuit PS and further amplifying the data line in the direction of charging. Here, the pulse applied to the common drive line is applied to the unselected subarray SMA
It is also applied to the amplifier circuits NS and PS belonging to IO and SMAtz, but these are never activated because the applied polarity is always in the direction in which NS and PS are cutoff. This is the unselected subarray SMA1o.

5MAl! This is because all the data lines within are held at the precharge voltage. On the contrary, subarray SM
When selecting Azo, S MAII, φNDOφ
A pulse may be applied to poo. Now, in the memory array configuration shown in FIG. 10, the number of subarrays that are simultaneously activated is half that of the configuration explained in FIG. The memory array configuration shown in FIG. 10 is also the same as the embodiment shown in FIGS. 4 to 8.
The present invention can be applied.

Although several embodiments of the present invention have been described above, it has not been mentioned in these embodiments that the number of input/output signals to and from the outside of the chip during the test mode increases compared to that during normal operation. For example, in the embodiment shown in FIG. 1, the input signal Dlnl+the output signal Dout1 and the test control signal TE. If the package housing the chip has enough pins to handle these increasing signals, dedicated pins can be provided. For example, in the case of a 1M bit dynamic MOS memory using the address multiplex method, the number of pins required for normal operation is 17, and this chip is connected to a 26-pin SOJ.
(small, l outline J-1eaded)
When stored in a package, it is easy to provide a dedicated pin. On the other hand, if the number of pins is insufficient, it is conceivable to share the pins with signals needed during normal operation for these increased signals. An example is shown below.

The embodiment shown in FIG. 11 is different from the embodiment shown in FIG. 1 or FIG.
It also takes the output signal DouL. This is an example where each pin is shared by utl, and it is a manual buffer circuit DIR.

This is an example in which there is one output buffer circuit DOB and one judgment circuit LOG, and a part of the memory array is omitted for the sake of simplicity. In order to share the input/output signal pins, in the embodiment shown in FIG. 11, in addition to the test control signal TE, another type of test control signal TE is provided.
2 and a switch S W 4 o which is collectively controlled by this signal.

SW 4.1, SW 42 and inverter circuit I
NV is set up. In this configuration, the input/output line IOo
, IOz, the input signal Dln is written as is, but when the switch SW 4 o is connected to the terminal 30, the inverted signal of Dln is written to the input/output line ■○z, IO3 by the test control signal TE2. , when connected to terminal 4°, Din itself is written, and the input/output lines IOo and I○2 forming one cell block group and the input/output lines forming another cell block group are written by the test control signal TE2. Independent data can be written to the output lines IO+ and IOa. Next, during the read operation in the test mode, the test control signal TE2 causes the switches SW 4 L and SW
4 z to the same side as the switch S W 4 o when writing data to the currently selected memory cell, for example, if S W 4 o was connected to the terminal 30, Sυ/b.

SW 42 are connected to terminals 31 and 32, respectively.

As a result, the four data input to the judgment circuit LOG become the same data during normal operation, that is, the same as DIn at the time of writing. .

Can be tested to determine inconsistency.

According to this embodiment, the same effect as described in FIG. 1 can be obtained, and by adding one test control signal TE2, the number of input/output signals can be reduced by two, resulting in a total of one signal. The number of pins required can be reduced. Furthermore, since the address signals Ai and Aj are originally unnecessary in the test mode, one of these address signals and the test control signal TE
It is also possible to generate the test control signal TE2 inside the chip by the logical output of , and in this case the number of signals can be reduced by two in total.

Note that the pin sharing of input/output signals explained in Fig. 11 is as follows.
The present invention can be applied not only to the embodiments shown in FIGS. 1 and 4, but also to the embodiments shown in FIGS. 5 to 10 by appropriately modifying them.

FIG. 12 shows another embodiment of the present invention, in which pins used for inputting address signals during normal operation are used for inputting and outputting input signals Dint and output signals ooutt during test mode. For this reason, in the same figure, the switch SW controlled by the test control signal TE is
5 o, SW 51 are provided. During normal operation, the pin terminal 100 is used for inputting the address signal Ai, and the pin terminal 101 is used for inputting Aj.
Switch S W 5 o , S controlled by E
It is connected to the address buffer circuit AB by W51. On the other hand, in the test mode, the pin terminal 100 is connected to the switch SW5 for inputting the input signal Dtnt.
o, the pin terminal 101 is connected to the input buffer circuit DIBz, and the pin terminal 101 is connected to the output buffer circuit DOB1 by the switch SW51 for outputting the output signal Douti.
are connected to each other. Here, the address signals Ai and Aj are used to select one of the four input/output lines do=da, but in the test mode, since 4-bit data is processed in parallel, these It is no longer necessary to input address signals, and these input pins can be used for input/output of input/output signals I)+nz+Doutl. Therefore, in this embodiment as well, the number of required pins can be reduced.

Note that the pin sharing of input/output signals and address signals explained in this embodiment is applicable not only to the embodiments shown in FIGS. 1 and 4 as in FIG. 11, but also to the embodiments shown in FIGS. The present invention can also be applied to the above embodiments by making appropriate modifications.

FIG. 13 shows another embodiment of the present invention, in which a dynamic MOS
This figure shows an example in which pins are shared by address signals and input/output signals in an address multiplex system used in memory.

In the figure, a pin terminal 100 is a terminal for an address signal Al during normal operation, and is connected to an address buffer circuit AB' to generate a row address signal ARI and a column address signal ACt in one time series. Similarly, pin terminal 10
1 is a terminal for normal address signal Aj, and switch SW
connected to the address buffer circuit AB' by 61;
Generates a row address signal ARJ and a column address signal AC-. Of these address signals generated, A
CJ, AC: t.

A Ra is input to the input/output line selection circuit l0DECI. On the other hand, in the test mode, the test control signal TH selects the output for the column address signal ACI inputted to l0DECI among the outputs of the address buffer circuit AB' connected to the pin winding terminal 100 as the input signal D+nt. Switch SW 6 to use
Control o. In addition, the switch SW 61 is set by TE.
and output buffer circuit DOBI to pin terminal 101.
Connect pin terminal 101 to output signal. Used for utl output. According to this embodiment, even in an address multiplex type semiconductor memory device, pins can be shared for input/output signals and address signals, and the number of required pins can be reduced. Note that the pin sharing described in this embodiment can be applied by appropriately modifying the embodiments shown in FIGS. 1 and 4 to 10 in the same manner as described in FIG. 12.

Although several embodiments of the present invention have been described above, the scope of application of the present invention is not limited to the embodiments described here, and it goes without saying that various changes can be made without departing from the spirit of the invention. For example, the memory array configuration shown in FIGS. 9 and 10 is a CMO5 (Complementary M
Although this is an example of a one-transistor MOS memory configured with OS), the present invention is also applicable to a memory configured with NMO5. Furthermore, it is not limited to dynamic MOS memory.

The present invention is applicable to large-capacity semiconductor memory devices, and is also applicable to so-called static memories and EEFROMs configured with flip-flop type memory cells. .

〔Effect of the invention〕

As described above, in the present invention, parallel processing for simultaneously writing and reading a plurality of cell blocks is performed inside the chip, so that the time required for testing can be shortened. Moreover, since independent data can be written and read between cell blocks where there is physical interference, interference between cell blocks can also be detected and highly reliable tests can be performed.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the main parts of an embodiment of the present invention, FIG. 2 is a circuit block diagram showing the main parts of a conventional semiconductor memory device, and FIG. 3 shows a part of the memory array of the semiconductor memory device. 4 to 8 are circuit block diagrams showing essential parts of another embodiment of the present invention; FIGS. 9 and 10 are circuit diagrams showing a part of a memory array of a semiconductor memory device; FIG.
13 are circuit block diagrams showing essential parts of still another embodiment of the present invention. MA...Memory array, work○, d...I/O line, P
A...Amplification circuit, LOG...Judgment circuit, DOB...
・Output buffer circuit, DIB...input buffer circuit,
l0DEC. l0DHCI, l0DEC2, l0DEC3...Input/output line selection circuit, TE...test control signal,
W E ...Write control signal, D t n
p D 1 n 1... Input signal, No. M 2 No. 3 No. 4 Fig. % 5 Cause 156] Section 7 Section No. 8 Fig. 9I21 Z lO Fig. cPseo 41f91ePseo ``go+spear 1
20

Claims (1)

[Claims] 1. A memory array consisting of a plurality of cell blocks each having an input/output line, and an input/output line selection circuit that connects input/output data to the input/output lines using a test control signal, a write signal, and an address signal. 1. A semiconductor memory device comprising means for dividing the plurality of cell blocks into two or more cell block groups and allowing data to be input and output independently from each other. 2. The semiconductor memory device according to claim 1, wherein the means is an input/output circuit provided for each cell block group. 3. The above means provides an input/output circuit in common to the cell block groups, connects the input/output circuit to one cell block group, and connects it to at least one other cell block group through each of the cell block groups. 2. The semiconductor memory device according to claim 1, wherein the means controls whether or not to pass through an inverter circuit provided individually for each group using a second test control signal provided individually.