JP5954498B2 - Semiconductor memory device and method for testing semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device and a method for testing a semiconductor memory device.

  Conventionally, a memory cell array having memory cells of the product of the number of rows and the number of columns in a memory core of a semiconductor chip, and a predetermined number of columns of the memory cell array formed in the memory core for normal operation of the memory cell array There is a semiconductor memory circuit device including an input / output circuit corresponding to a 1-bit input line, output line or input / output line.

  The semiconductor memory circuit device further includes a 1-bit input line, output line, or input / output line for each number of columns of the memory cell array formed in the memory core for inspection at the time of manufacture of the memory cell array, which is smaller than a predetermined number (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 2002-237198

  However, when a conventional semiconductor memory circuit device performs an operation test at the time of manufacturing a memory cell corresponding to half of the column addresses of a plurality of memory cells included in a memory block of the same bit, it corresponds to the remaining half of the column addresses. Even if a defective memory cell occurs, it may not be detected.

  Accordingly, it is an object of the present invention to provide a semiconductor memory device capable of detecting a defect with high accuracy and a test method for the semiconductor memory device.

  A semiconductor memory device according to an embodiment of the present invention includes a memory block having a plurality of memory cells that hold data, and a first column that is a half of column addresses of a plurality of memory cells of the same bit included in the memory block A selection circuit for outputting a first selection signal for selecting an address or a second selection signal for selecting the second column address of the remaining half of the column addresses of the plurality of memory cells of the same bit; When writing test data to the plurality of memory cells, both the first selection signal and the second selection signal are output, and when writing normal data to the plurality of memory cells, the first selection signal or A selection circuit that outputs one of the second selection signals; and a plurality of memory cells having the same bit when the first selection signal is at a first level. A first driver that outputs write data to a first memory cell corresponding to the first column address; and when the second selection signal is at a first level, among the plurality of memory cells of the same bit, And a second driver for outputting write data to the second memory cell corresponding to the second column address.

  It is possible to provide a semiconductor memory device capable of detecting a defect with high accuracy and a test method of a test method for a semiconductor memory device.

It is a figure which shows allocation of the bit and column in SRAM of premise technology. It is a figure which shows the state in which data was written in the operation | movement test of SRAM of a base technology. FIG. 2 is a diagram showing a state in which test data is written in a sub-block on the lower side in an operation test at the time of manufacturing the SRAM of the base technology shown in FIG. FIG. 2 is a diagram illustrating a state in which leakage between subblocks adjacent to each other cannot be detected in the SRAM illustrated in FIG. It is a figure which shows SRAM of embodiment. It is a figure which shows the relationship between a 3-bit column address and the column selected. FIG. 3 is a diagram illustrating details of a circuit used for a write operation of the SRAM according to the embodiment. 4 is a timing chart showing a write operation during normal operation of the SRAM of the embodiment; It is a figure which shows the detail of the circuit used for SRAM of embodiment. 4 is a timing chart illustrating a write operation during an operation test of the SRAM according to the embodiment. It is a figure which shows the state which wrote the write data with the checkerboard pattern in the memory cell of SRAM of embodiment. It is a figure which shows the test data written in each memory cell, when the leak has generate | occur | produced between the memory cells located in the boundary of the adjacent sub block of the upper side and lower sub block. It is a figure which shows the procedure of the operation | movement test of SRAM of embodiment. It is a figure which shows the state which connected the LSI tester to SRAM of embodiment.

  Before describing an embodiment to which a semiconductor memory device and a test method for a semiconductor memory device of the present invention are applied, a semiconductor memory device and a test method for a semiconductor memory device according to a prerequisite technique will be described.

  FIG. 1 is a diagram showing bit and column assignments in a prerequisite technology SRAM (Static Random Access Memory). FIG. 2 is a diagram showing a state in which data is written in the operation test of the SRAM of the base technology.

  FIG. 1A shows the configuration of an SRAM of 4K words × 72 bits-4 columns / bit. The SRAM shown in FIG. 1A has 72 I / Os (Input / Output) (RD / WD [0] to RD / WD [71]) and 72 memory blocks (column [3: 0]). ) And two redundant blocks (red [3: 0]). The total number of memory cells of the SRAM shown in FIG. 1A is 296 per word including the memory cells included in the redundant block (red [3: 0]).

  FIG. 1B shows the configuration of an SRAM of 4K words × 72 bits-8 columns / bit. The SRAM shown in FIG. 1B includes 72 I / Os (RD / WD [0] to RD / WD [71]), 72 memory blocks (column [7: 0]), and 2 Contains redundant blocks (red [7: 0]). The total number of SRAM memory cells shown in FIG. 1B is 592 per word including the memory cells included in the redundant block (red [7: 0]).

  FIG. 1C shows the configuration of an SRAM of 8K words × 36 bits-8 columns / bit. The SRAM shown in FIG. 1C has 36 I / O (Input / Output) (RD / WD [0] to RD / WD [35]) and 36 memory blocks (column [7: 4]). , column [3: 0]) and two redundant blocks (red [3: 0]). The total number of memory cells of the SRAM shown in FIG. 1C is 296 per word including the memory cells included in the redundant block (red [3: 0]). This is shown in FIG. It is the same as the SRAM shown.

  The 36 memory blocks (column [7: 4], column [3: 0]) of SRAM shown in FIG. 1 (C) are the upper side sub-block (column [7: 4]) and the lower side respectively. And sub-blocks (column [3: 0]).

  The upper side sub-block (column [7: 4]) and lower side sub-block (column [3: 0]) can be selected by the most significant bit value of the column address, and data is written separately. And reading can be performed.

  In SRAM (SRAM macro), as a countermeasure against soft errors caused by alpha rays or neutron rays, a method of preventing a multi-bit error by doubling the number of columns per bit is adopted.

  For example, the SRAM of 4K words × 72 bits−4 columns / bit shown in FIG. 1A is similar to the SRAM of 4K words × 72 bits−8 columns / bit shown in FIG. This is realized by doubling the number of columns. That is, the SRAM shown in FIG. 1B is a SRAM in which a soft error countermeasure is taken with respect to the SRAM shown in FIG.

  However, if the number of columns per bit is simply doubled, the size of the SRAM (SRAM macro) increases in the direction in which the columns are aligned (the vertical direction in FIGS. 1A and 1B). The wiring length of the word line is approximately doubled. For this reason, performance increases such as an increase in delay due to an increase in load such as an increase in parasitic capacitance due to an increase in the wiring length of the word line.

  Therefore, as shown in FIG. 1C, the number of bits in the entire SRAM (SRAM macro) is halved, and the number of columns of the redundant block (red [3: 0]) is the same as before the soft error countermeasure. By doing so, it is possible to take measures against soft errors while avoiding an increase in the size of the SRAM (SRAM macro) in the direction in which the columns are arranged.

  The column number (4) of the SRAM redundant block (red [3: 0]) shown in FIG. 1C is the column of the SRAM memory block (column [3: 0]) shown in FIG. It is the same as the number (4).

  In the SRAM shown in FIG. 1C, an upper side sub-block (column [7: 4]), a lower side sub-block (column [3: 0]), and a redundant block (red [3: 0]) We have the same size. This is because any sub-block (column [7: 4]) or (column [3: 0]) of 36 memory blocks (column [7: 4], column [3: 0]) is defective. This is because a redundant block (red [3: 0]) can be used in place of a defective sub-block.

  Hereinafter, the size of such a sub-block (column [7: 4]) or (column [3: 0]) and a redundant block (red [3: 0]) is referred to as a half bit. The half bit is a 1-bit memory block (column [7: 4], column [3: 0]) that combines the sub-block (column [7: 4]) and the sub-block (column [3: 0]). The size corresponds to half.

  However, in the SRAM having the configuration shown in FIG. 1C, the memory block is divided into sub-blocks (column [7: 4]) and (column [3: 0]). Although it is possible to specify whether or not a block is defective, it is not possible to specify which of the sub-blocks (column [7: 4]) and (column [3: 0]) is defective.

  Therefore, in the operation test at the time of manufacturing, as shown in FIG. 2A, data writing and reading to the lower side sub-block (column [3: 0]) and as shown in FIG. As described above, data is written to and read from the upper sub-block (column [7: 4]) separately. The arrows in FIGS. 2A and 2B indicate reading.

  If data is written to and read from the lower side sub-block (column [3: 0]) and the upper side sub-block (column [7: 4]) separately, the lower side sub-block (column [3 :: This is because it is possible to determine which of the sub blocks (column [7: 4]) on the upper side is defective.

  If a defect is found, replace the defective sub-block (column [7: 4]) or (column [3: 0]) with the redundant block (red [3: 0]). To determine whether the SRAM can be shipped.

  As shown in FIG. 1C, one SRAM (SRAM macro) has two redundant blocks (red) for 72 sub-blocks (column [7: 4], column [3: 0]). [3: 0]), the SRAM can be shipped if the number of defective sub-blocks is up to two.

  FIG. 3 is a diagram showing a state in which test data is written in the sub-block (column [3: 0]) on the lower side in the operation test at the time of manufacturing the SRAM of the base technology shown in FIG.

  In FIG. 3, test data is written in the upper side sub-block (column [7: 4]) so that the test data is written in the lower side sub-block (column [3: 0]). Absent.

  As shown in FIG. 3, in an operation test at the time of manufacturing, test data having a checkerboard (checkered pattern) pattern is written in a sub-block (column [3: 0]). The checkerboard pattern is obtained by writing “1” and “0” data in a checkered pattern in memory cells arranged in an array.

  By writing the test data of the checkerboard pattern into the memory cells, the data of one memory cell and the data of the four memory cells above, below, left, and right of this memory cell differ from each other in plan view. It is possible to detect defects such as the occurrence of leaks in between.

  Note that such writing of the checkerboard pattern is similarly performed for the upper side sub-block (column [7: 4]).

  However, in the manufacturing operation test as described above, by writing the test data to the upper sub-block (column [7: 4]) by fixing the most significant bit value of the column address to “1”. Read. In addition, by fixing the most significant bit value of the column address to “0”, the test data is written to and read from the lower side sub-block (column [3: 0]).

  For this reason, when writing and reading test data to the lower sub-block (column [3: 0]), the test data is not stored in the upper sub-block (column [7: 4]). The data is not written, and the memory cell of the upper side sub-block (column [7: 4]) is in an indefinite state where it is not known which data “0” / “1” is held. In FIG. 3, data in an indefinite state is indicated by “x”.

  In the SRAM shown in FIGS. 1A and 1B, writing and reading of test data to and from all 72 memory blocks (column [3: 0]) and memory blocks (column [7: 0]). Therefore, it is possible to detect a leak between adjacent memory blocks (column [3: 0], column [7: 0]).

  On the other hand, in the SRAM shown in FIG. 1C, as described above, the lower side sub-block (column [3: 0]) and the upper side sub-block (column [7: 4]) are processed. Since writing and reading of test data are performed separately, there is a case where leakage between adjacent sub-blocks cannot be detected.

  Here, with reference to FIG. 4, a case where a leak between adjacent sub-blocks cannot be detected in the SRAM shown in FIG.

  FIG. 4 is a diagram illustrating a state in which leakage between subblocks adjacent to each other cannot be detected in the SRAM illustrated in FIG.

  Here, as an example, in FIG. 4, it is assumed that there is a leak between the memory cell in column [3] of the lower side sub-block and the memory cell in column [4] of the upper side sub-block.

  Here, a case will be described in which test data is written to and read from the sub-block (column [3: 0]) on the lower side. For this reason, test data is not written in the upper side sub-block (column [7: 4]).

  In FIG. 4, columns [0] to [7] of sub-blocks (column [7: 4], column [3: 0]) are shown in the horizontal direction, and the time axis is shown in the vertical direction. “1” and “0” shown in FIG. 4 represent data values held by the memory cells in the columns [0] to [7] after the time t1, and “x” indicates that the data value is indefinite. .

  The test data is written in the order of the columns [3], [2], [1], [0] to the lower side sub-block (column [3: 0]).

  At time t1, since test data is not written in the memory cells in the columns [3] to [0], the data values of the memory cells in the columns [3] to [0] are “x” indicating indefinite. is there.

  At time t2, “1” is written to the memory cell in column [3]. At this time, since there is a leak between the memory cell in column [3] and the memory cell in column [4], the memory cell in column [4] to which no test data has been written is set to “1”. Hold.

  Thereafter, from time t3 to time t5, the state in which the memory cell in the column [3] and the memory cell in the column [4] hold “1” continues.

  At time t3, “0” is written to the memory cell in column [2]. At time t4, “1” is written to the memory cell in column [1]. At time t5, “0” is written to the memory cell in column [0].

  As described above, the test data “1”, “0”, “1”, “0” is written in the memory cells in the columns [3] to [0] from the time t2 to the time t5.

  After writing “0” to the memory cell in column [0] at time t5, the data value read from the memory cell in column [3] is “1”, which is the memory in column [3] at time t2. The data value (expected value) written in the cell is the same as “1”, and is consistent.

  Therefore, it is determined that no defect has occurred in the memory cell in column [3].

  In this way, when there is a leak between the memory cell in column [3] of the lower side sub-block and the memory cell in column [4] of the upper side sub-block, the sub-block (column [ When test data is written to 3: 0]), data is not read from the upper side sub-block, and data cannot be read.

  Therefore, the SRAM shown in FIG. 1C may not detect a defect even if an operation test at the time of manufacture is performed.

  Therefore, an object of the embodiment described below is to provide a semiconductor memory device capable of detecting a defect with high accuracy and a test method for the semiconductor memory device.

  Embodiments to which a semiconductor memory device and a test method for a semiconductor memory device of the present invention are applied will be described below.

<Embodiment 1>
FIG. 5 is a diagram illustrating the SRAM 100 according to the embodiment.

  The SRAM 100 includes a memory block 110, a selection circuit 120, drivers 130U and 130L, write amplifiers 140U and 140L, write column selection circuits 150U and 150L, and an FF (Flip Flop) 160.

  The SRAM 100 further includes an FF 210, a read multiplexer 220, read amplifiers 230U and 230L, read column selection circuits 240U and 240L, a chopper circuit 310, FFs 320 and 330, and a write clock generator 340. The SRAM 100 is an example of a semiconductor memory device.

  In the following, the subscript U of each component sign means Upper, and the subscript L means Lower.

  The memory block 110 is a portion corresponding to 1 bit in the memory cell array included in the SRAM 100. The memory cell array of the SRAM 100 is a memory cell array of 8K words × 36 bits-8 columns / bit.

  All the memory cells included in one memory block 110 hold the same bit of data.

  The memory block 110 includes sub blocks 110U and 110L. The sub block 110U is an upper side sub block (column [7: 4]), and the sub block 110L is a lower side sub block (column [3: 0]). The sizes of the sub-blocks 110U and 110L are half bits.

  Each of the sub-blocks 110U and 110L has memory cells for four columns, but FIG. 5 shows one memory cell 111U and 111L in each of the sub-blocks 110U and 110L for convenience of explanation.

  The memory cells 111U and 111L are so-called six-transistor type bit cells, and their addresses are specified by the bit lines BL and BLB and the word line WL.

  The memory cell 111U includes a pair of negative circuits, inverters 111A and 111B, and a pair of NMOS (N-type metal oxide semiconductor) transistors 111C and 111D.

  The inverters 111A and 111B are connected so as to form a loop. The gates of the NMOS transistors 111C and 111D are both connected to a word line WL (Word Line), the drain of the NMOS transistor 111C is connected to the positive bit line BL, and the drain of the NMOS transistor 111D is the negative bit line. It is connected to BLB (BL bar).

  The sources of the NMOS transistors 111C and 111D are connected to the connection portions N1 and N2 of the inverters 111A and 111B connected in a loop.

  The inverters 111A and 111B are CMOS (Complementary Metal Oxide Semiconductor) type inverters each having a PMOS (P-type metal oxide semiconductor) transistor and an NMOS transistor 11B. is there. Therefore, memory cell 111U includes six MOS transistors.

  As described above, the memory cell 111U is realized as a latch circuit including the inverters 111A and 111B.

  By holding the complementary data of “1”, “0” or “0”, “1” in the storage nodes N1, N2, and selecting the memory cell 111U with the word line WL and the pair of bit lines BL, BLB, Data is read from and written to the storage nodes N1 and N2.

  Note that the configuration of the memory cell 111L is the same as the configuration of the memory cell 111U.

  The bit lines BL and BLB of the memory cell 111U are connected to the write column selection circuit 150U and the read column selection circuit 240U via local bit lines LBL_U and LBLB_U, respectively.

  Similarly, the bit lines BL and BLB of the memory cell 111L are connected to the write column selection circuit 150L and the read column selection circuit 240L via local bit lines LBL_L and LBLB_L, respectively.

  Actually, the sub-blocks 110U and 110L have four pairs of bit lines BL and BLB.

  Therefore, in reality, the four pairs of bit lines BL and BLB of the sub-block 110U are connected to the write column selection circuit 150U and the read column selection circuit 240U via the four pairs of local bit lines LBL_U and LBLB_U, respectively. ing.

  Similarly, the four pairs of bit lines BL and BLB of the sub-block 110L are connected to the write column selection circuit 150L and the read column selection circuit 240L via the four pairs of local bit lines LBL_L and LBLB_L, respectively.

  The column address selection when writing data to the memory cells 111U and 111L is performed by the write column selection circuits 150U and 150L via the bit lines BL and BLB and the local bit lines LBL_L and LBLB_L or LBL_U and LBLB_U.

  The column address selection when reading data from the memory cells 111U and 111L is performed by the read column selection circuits 240U and 240L via the bit lines BL and BLB and the local bit lines LBL_L and LBLB_L or LBL_U and LBLB_U.

  The system clock CLK is input to the input terminal of the chopper circuit 310. The output terminal of the chopper circuit 310 is connected to the clock input terminal of the FFs 160, 210, 320, and 330 and one terminal (upper side in the drawing) of the write clock generator 340.

  The chopper circuit 310 generates a clock CLK1 to be input to the FFs 160, 210, 320, and 330 based on the system clock CLK. The chopper circuit 310 inputs the clock CLK1 in which the width of the system clock CLK is adjusted to the FFs 160, 210, 320, and 330. The FFs 160, 210, 320, and 330 operate in synchronization with the clock CLK1.

  The FF 320 receives the write enable signal WE, and the FF 320 operates according to the clock CLK1 input from the chopper circuit 310 to the clock input terminal. The output terminal of the FF 320 is connected to the other terminal (lower side in the figure) of the write clock generator 340.

  The SRAM 100 performs a read operation when the write enable signal WE is “0”, and performs a write operation when the write enable signal WE is “1”.

  The FF 330 receives the most significant bit value AD [2] of the column address and operates according to the clock CLK1 input from the chopper circuit 310 to the clock input terminal. The output terminal of the FF 330 is connected to the selection circuit 120.

  The write clock generator 340 includes a NAND circuit 341 and an inverter 342. A system clock CLK and a write enable signal WE are input to a pair of input terminals of the NAND circuit 341. The write enable signal WE is input from the FF 320. The output terminal of the NAND circuit 341 is connected to the input terminal of the inverter 342. The output of the inverter 342 is output as the output of the write clock generator 340 (write clock WCK).

  The write clock generator 340 outputs a write clock WCK obtained by inverting the negative logical product of the system clock CLK and the write enable signal WE by the inverter 342.

  Here, when the write enable signal WE is “0” and the write clock WCK is “0”, the SRAM 100 performs a read operation. Further, when the write enable signal WE is “1” and the write clock WCK is “1”, the SRAM 100 performs a write operation.

The selection circuit 120 has three input terminals. The selection circuit 120 receives the most significant bit value AD [2] of the column address, the write clock WCK, and the test control signal CT. The most significant bit value AD [2] and the write clock WCK are input from the FF 330 and the write clock generator 340, respectively.
The selection circuit 120 has two output terminals connected to the signal lines net_A and net_B. The column address is 3-bit address data.

  The selection circuit 120 generates selection signals net_A and net_B based on the most significant bit value AD [2] of the column address, the write clock WCK, and the test control signal CT, and outputs them to the signal lines net_A and net_B, respectively.

  Two output terminals of the selection circuit 120 are connected to drivers 130U and 130L via signal lines net_A and net_B, respectively. Selection signals net_A and net_B output from the selection circuit 120 are input to the drivers 130U and 130L, respectively.

  The selection signals net_A and net_B are used to set the write data write destination to either the upper side sub-block 110U or the lower side sub-block 110L. The selection signal net_A is an example of a first selection signal. The selection signal net_B is an example of a second selection signal.

  Each of the drivers 130U and 130L has two input terminals. Signal lines net_A and net_C are connected to the two input terminals of the driver 130U, respectively. Signal lines net_B and net_C are connected to the two input terminals of the driver 130L, respectively.

  Each of the drivers 130U and 130L has two output terminals. Write bit lines WBL_U and WBLB_U are connected to two output terminals of the driver 130U. The write bit lines WBL_U and WBLB_U are connected to the write amplifier 140U.

  Write bit lines WBL_L and WBLB_L are connected to the two output terminals of the driver 130L. The write bit lines WBL_L and WBLB_L are connected to the write amplifier 140L.

  The driver 130U receives the selection signal net_A from the selection circuit 120 and the write data from the FF 160. The driver 130L receives the selection signal net_B from the selection circuit 120 and the write data from the FF 160.

  The driver 130U outputs write data to the write bit lines WBL_U and WBLB_U when the selection signal net_A is at H (High) level, and does not output write data when the selection signal net_A is at L (Low) level.

  The driver 130L outputs write data to the write bit lines WBL_L and WBLB_L when the selection signal net_B is at the H (High) level, and does not output write data when the selection signal net_B is at the L (Low) level.

  Each of the write amplifiers 140U and 140L has two input terminals. Write bit lines WBL_U and WBLB_U are connected to the two input terminals of the write amplifier 140U, respectively. Write bit lines WBL_L and WBLB_L are connected to the two input terminals of the write amplifier 140L, respectively.

  Light column selection circuits 150U and 150L are connected to the output sides of the write amplifiers 140U and 140L, respectively.

  The write amplifier 140U amplifies complementary write data input from the write bit lines WBL_U and WBLB_U and inputs the amplified write data to the write column selection circuit 150U. The write amplifier 140L amplifies complementary write data input from the write bit lines WBL_L and WBLB_L and inputs the amplified write data to the write column selection circuit 150L.

  The light column selection circuits 150U and 150L are connected to the output sides of the write amplifiers 140U and 140L, respectively. The write column selection circuits 150U and 150L are supplied with the complementary write data amplified by the write amplifiers 140U and 140L and the lower two bits of the column address AD [1: 0]. The The lower 2 bits of bit value AD [1: 0] are used for selecting columns [7] to [4] of sub-block 110U and for selecting columns [3] to [0] of sub-block 110L.

  In practice, four pairs of local bit lines LBL_U and LBLB_U are connected to the output side of the write column selection circuit 150U, respectively. Similarly, four pairs of local bit lines LBL_L and LBLB_L are actually connected to the output side of the write column selection circuit 150L, respectively.

  The write column selection circuit 150U outputs the write data input from the write amplifier 140U to the local bit lines LBL_U and LBLB_U specified by the bit value AD [1: 0].

  The write column selection circuit 150L outputs the write data input from the write amplifier 140L to the local bit lines LBL_L and LBLB_L specified by the bit value AD [1: 0].

  In the FF 160, the write data WD is input to the data input terminal. The data output terminal of the FF 160 is connected to one input terminal of the drivers 130U and 130L via the signal line net_C. The FF 160 may be a D-FF, for example.

  The FF 160 outputs the write data WD input to the data input terminal to the signal line net_C in accordance with the clock CLK1 input to the clock input terminal. The clock CLK1 is a pulse-like clock with a short rise time that rises instantaneously at a timing when a system clock CLK described later rises.

  The FF 210 is an FF that holds read data. The FF 210 may be a D-FF, for example. The data input terminal of the FF 210 is connected to the output terminal of the read multiplexer 220.

  In the read multiplexer 220, the read amplifiers 230U and 230L are connected to the input side, and the FF 210 is connected to the output side. The read multiplexer 220 selects the read data input from the read amplifier 230U or 230L and outputs it to the FF 210.

  The read amplifiers 230U and 230L are connected to the read column selection circuits 240U and 240L on the input side and the read multiplexer 220 on the output side, respectively. The read amplifiers 230U and 230L amplify the read data input from the read column selection circuits 240U and 240L, respectively, and output the amplified data to the multiplexer 220.

  Each of the read column selection circuits 240U and 240L has two input terminals. The sub-block 110U is connected to the two input terminals of the read column selection circuit 240U via local bit lines LBL_U and LBLB_U. The sub-block 110L is connected to the two input terminals of the read column selection circuit 240L via local bit lines LBL_L and LBLB_L.

  The read column selection circuits 240U and 240L input the read data read from the sub blocks 110U and 110L to the read amplifiers 230U and 230L, respectively.

  Next, the 3-bit column address AD [2: 0] will be described with reference to FIG.

  FIG. 6 is a diagram illustrating a relationship between a 3-bit column address AD [2: 0] and a selected column.

  The memory block 110 of the SRAM 100 of this embodiment has eight columns and is divided into sub-blocks 110U and 110L.

  The sub blocks 110U and 110L have memory cells 111U and 111L for four columns, respectively. The eight columns of the memory block 110 are specified by a 3-bit column address AD [2: 0].

  In FIG. 6, the column selected by the column address AD [2: 0] is indicated by ◯, and the column not selected is indicated by ×.

  As shown in FIG. 6, when the column address AD [2: 0] is “000”, the column [0] is selected. When the column address AD [2: 0] is “001”, the column [1] is selected, and when the column address AD [2: 0] is “010”, the column [2] is selected.

  When the column address AD [2: 0] is “011”, the column [3] is selected, and when the column address AD [2: 0] is “100”, the column [4] is selected. When the column address AD [2: 0] is “101”, the column [5] is selected, and when the column address AD [2: 0] is “110”, the column [6] is selected. When the column address AD [2: 0] is “111”, the column [7] is selected.

  The selection circuit 120 (see FIG. 5) of the SRAM 100 sets the signal levels of the selection signals net_A and net_B based on the most significant bit value AD [2] of the column address AD [2: 0]. When the most significant bit value AD [2] of the column address AD [2: 0] is “1”, the selection circuit 120 sets the selection signal net_A to the H level in order to select the upper side sub-block 110U. To set the selection signal net_B to L level.

  Further, when the most significant bit value AD [2] of the column address AD [2: 0] is “0”, the selection circuit 120 sets the selection signal net_B to H in order to select the lower side sub-block 110L. Set to level and select signal net_A to L level.

  Next, details of a circuit used when write data is written in the memory cells 111U and 111L of the sub-blocks 110U and 110L in the SRAM 100 of the embodiment will be described with reference to FIG.

  FIG. 7 is a diagram illustrating details of a circuit used for the write operation of the SRAM 100 according to the embodiment.

  FIG. 7 shows portions corresponding to the sub-blocks 110U and 110L, the selection circuit 120, the drivers 130U and 130L, the write amplifiers 140U and 140L, the write column selection circuits 150U and 150L, and the FF 160 in FIG.

  The circuit used for the write operation of the SRAM 100 shown in FIG. 7 includes a selection circuit 120, drivers 130U and 130L, write amplifiers 140U and 140L, write column selection circuits 150U and 150L, FF160, and inverters 161 and 162.

  7 shows details of the selection circuit 120 and the drivers 130U and 130L, and details of the write amplifiers 140U and 140L and the write column selection circuits 150U and 150L are omitted.

  The selection circuit 120 includes input terminals 120A, 120B, 120C, an inverter 121, NAND circuits 122U, 122L, 123U, 123L, and inverters 124U, 124L, 125.

  The input terminal 120A is an input terminal to which the most significant bit value AD [2] of the column address is input. The column address is extracted from the input address by a column decoder (not shown), and the most significant bit value AD [2] is input to the input terminal 120A.

  The input terminal 120A is connected to the input terminal of the inverter 121 and one input terminal of the NAND circuit 122L.

  The input terminal 120B is an input terminal to which the write clock WCK is input. The input terminal 120B is connected to one input terminal of the NAND circuits 123U and 123L.

  The input terminal 120C is an input terminal to which the test control signal CT is input. The test control signal CT is input from an LSI (Large Scale Integrated circuit) tester connected to a test terminal of the SRAM 100 in an operation test during manufacturing. The input terminal 120C is connected to the input terminal of the inverter 125. The input terminal 120C is an example of a test input terminal.

  Here, the LSI tester connected to the test terminal of the SRAM 100 inputs an H level test control signal CT to the input terminal 120C when performing an operation test during manufacturing. Since the LSI tester is not connected to the test terminal of the SRAM 100 except when an operation test at the time of manufacturing is performed, the signal level of the input terminal 120C becomes L level.

  The input terminal of the inverter 121 is connected to the input terminal 120A, and the output terminal is connected to one input terminal of the NAND circuit 122U. The inverter 121 inverts the most significant bit value AD [2] of the column address input from the input terminal 120A, and inputs the inverted value to one input terminal of the NAND circuit 122U.

  NAND circuit 122U has one input terminal connected to the output terminal of inverter 121 and the other input terminal connected to the output terminal of inverter 125. The output terminal of the NAND circuit 122U is connected to one input terminal of the NAND circuit 123U.

  The NAND circuit 122U calculates a negative logical product of the output signals of the inverters 121 and 125, and inputs a signal representing the calculation result to one input terminal of the NAND circuit 123U. The NAND circuit 122U is an example of a first NAND circuit.

  The NAND circuit 122L has one input terminal connected to the output terminal of the inverter 125 and the other input terminal connected to the input terminal 120A. The output terminal of the NAND circuit 122L is connected to one input terminal of the NAND circuit 123L.

  The NAND circuit 122L calculates a negative logical product of the output of the inverter 125 and the most significant bit value AD [2] of the column address, and inputs a signal representing the calculation result to one input terminal of the NAND circuit 123L. The NAND circuit 122L is an example of a second NAND circuit.

  NAND circuit 123U has one input terminal connected to the output terminal of NAND circuit 122U and the other input terminal connected to input terminal 120B. The output terminal of the NAND circuit 123U is connected to the input terminal of the inverter 124U.

  The NAND circuit 123U calculates a negative logical product of the output of the NAND circuit 122U and the write clock WCK, and inputs a signal representing the calculation result to the inverter 124U.

  One input terminal of the NAND circuit 123L is connected to the input terminal 120B, and the other input terminal is connected to the output terminal of the NAND circuit 122L. The output terminal of the NAND circuit 123L is connected to the input terminal of the inverter 124L.

  The NAND circuit 123L calculates a negative logical product of the write clock WCK and the output of the NAND circuit 122L, and inputs a signal representing the calculation result to the inverter 124L.

  The inverter 124U has an input terminal connected to the output terminal of the NAND circuit 123U, and an output terminal connected to one input terminal of the NAND circuits 132U and 132UB of the driver 130U.

  The inverter 124U inverts the output of the NAND circuit 123U to generate the selection signal net_A. The inverter 124U inputs the selection signal net_A to one input terminal of the NAND circuits 132U and 132UB.

  The inverter 124L has an input terminal connected to the output terminal of the NAND circuit 123L, and an output terminal connected to one input terminal of the NAND circuits 132L and 132LB of the driver 130L.

  The inverter 124L inverts the output of the NAND circuit 123L to generate the selection signal net_B. The inverter 124L inputs the selection signal net_B to one input terminal of the NAND circuits 132L and 132LB.

  The inverter 125 has an input terminal connected to the input terminal 120C, and an output terminal connected to one input terminal of the NAND circuits 122U and 122L.

  The inverter 125 inverts the test control signal CT input from the input terminal 120C and inputs the inverted value to one input terminal of the NAND circuits 122U and 122L.

  The selection circuit 120 having the above configuration generates and outputs selection signals net_A and net_B based on the most significant bit value AD [2] of the column address, the write clock WCK, and the test control signal CT. The selection signals net_A and net_B are examples of a first selection signal and a second selection signal, respectively.

  The driver 130U includes an inverter 131U, NAND circuits 132U and 132UB, inverters 133U and 133UB, and inverters 134U and 134UB.

  The inverter 131U has an input terminal connected to the output terminal of the inverter 162, and an output terminal connected to one input terminal of the NAND circuit 132U. The inverter 131U inverts write data transmitted from the FF 160 via the inverters 161 and 162, and inputs an inverted value of the write data to one input terminal of the NAND circuit 132U.

  NAND circuit 132U has one input terminal connected to the output terminal of inverter 124U of selection circuit 120, and the other input terminal connected to the output terminal of inverter 131U. The output terminal of the NAND circuit 132U is connected to the input terminal of the inverter 133U.

  The NAND circuit 132U calculates a negative logical product of the output of the inverter 124U and the output of the inverter 131U, and inputs a signal representing the calculation result to the inverter 133U.

  NAND circuit 132UB has one input terminal connected to the output terminal of inverter 124U and the other input terminal connected to the output terminal of inverter 162. The output terminal of NAND circuit 132UB is connected to the input terminal of inverter 133UB.

  The NAND circuit 132UB calculates a negative logical product of the output of the inverter 124U and the write data transmitted from the FF 160 via the inverters 161 and 162, and inputs a signal representing the calculation result to the inverter 133UB.

  Inverter 133U has an input terminal connected to the output terminal of NAND circuit 132U, and an output terminal connected to the input terminal of inverter 134U. The inverter 133U inverts the output of the NAND circuit 132U and inputs the inverted value to the input terminal of the inverter 134U.

  Inverter 133UB has an input terminal connected to the output terminal of NAND circuit 132UB, and an output terminal connected to the input terminal of inverter 134UB. Inverter 133UB inverts the output of NAND circuit 132UB and inputs the inverted value to the input terminal of inverter 134UB.

  The inverter 134U has an input terminal connected to the output terminal of the inverter 133U, and an output terminal connected to the write amplifier 140U via the write bit line WBL_U. Inverter 134U inverts and outputs the output of inverter 133U.

  Here, the output of the inverter 134U is write data to be written to the memory cell 111 in any column of the upper subblock 110U when the upper subblock 110U is selected.

  That is, the inverter 134U outputs the write data to the write bit line WBL_U when the upper side sub-block 110U is selected.

  The inverter 134UB has an input terminal connected to the output terminal of the inverter 133UB, and an output terminal connected to the write amplifier 140U via the write bit line WBLB_U. Inverter 134UB inverts and outputs the output of inverter 133UB.

  Here, the output of the inverter 134UB is write data to be written to the memory cell 111 in any column of the upper side sub-block 110U when the upper side sub-block 110U is selected.

  That is, the inverter 134UB outputs the write data to the write bit line WBLB_U when the upper side sub-block 110U is selected.

  Note that the write data output from the inverter 134UB to the write bit line WBLB_U is an inverted value of the write data output from the inverter 134U to the write bit line WBL_U, and the write data output from the inverter 134U and the write data output from the inverter 134UB. Is to construct complementary format write data.

  The driver 130L includes an inverter 131L, NAND circuits 132L and 132LB, inverters 133L and 133LB, and inverters 134L and 134LB.

  The inverter 131L has an input terminal connected to the output terminal of the inverter 162, and an output terminal connected to one input terminal of the NAND circuit 132L. The inverter 131L inverts write data transmitted from the FF 160 via the inverters 161 and 162, and inputs the inverted value of the write data to one input terminal of the NAND circuit 132L.

  The NAND circuit 132L has one input terminal connected to the output terminal of the inverter 124L of the selection circuit 120, and the other input terminal connected to the output terminal of the inverter 131L. The output terminal of the NAND circuit 132L is connected to the input terminal of the inverter 133L.

  The NAND circuit 132L calculates a negative logical product of the output of the inverter 124L and the output of the inverter 131L, and inputs a signal representing the calculation result to the inverter 133L.

  NAND circuit 132LB has one input terminal connected to the output terminal of inverter 124L and the other input terminal connected to the output terminal of inverter 162. The output terminal of NAND circuit 132LB is connected to the input terminal of inverter 133LB.

  The NAND circuit 132LB calculates a negative logical product of the output of the inverter 124L and the write data transmitted from the FF 160 via the inverters 161 and 162, and inputs a signal representing the calculation result to the inverter 133LB.

  The inverter 133L has an input terminal connected to the output terminal of the NAND circuit 132L, and an output terminal connected to the input terminal of the inverter 134L. The inverter 133L inverts the output of the NAND circuit 132L and inputs the inverted value to the input terminal of the inverter 134L.

  Inverter 133LB has an input terminal connected to the output terminal of NAND circuit 132LB, and an output terminal connected to the input terminal of inverter 134LB. Inverter 133LB inverts the output of NAND circuit 132LB and inputs the inverted value to the input terminal of inverter 134LB.

  The inverter 134L has an input terminal connected to the output terminal of the inverter 133L, and an output terminal connected to the write amplifier 140L via the write bit line WBL_L. The inverter 134L inverts and outputs the output of the inverter 133L.

  Here, the output of the inverter 134L is write data to be written to the memory cell 111 in any column of the lower sub-block 110L when the lower sub-block 110L is selected.

  That is, the inverter 134L outputs the write data to the write bit line WBL_L when the lower side sub-block 110L is selected.

  The inverter 134LB has an input terminal connected to the output terminal of the inverter 133LB, and an output terminal connected to the write amplifier 140L via the write bit line WBLB_L. Inverter 134LB inverts and outputs the output of inverter 133LB.

  Here, the output of the inverter 134LB is write data to be written to the memory cell 111 in any column of the lower sub-block 110L when the lower sub-block 110L is selected.

  That is, the inverter 134LB outputs write data to the write bit line WBLB_L when the lower-side sub-block 110L is selected.

  Note that the write data output from the inverter 134LB to the write bit line WBLB_L is an inverted value of the write data output from the inverter 134L to the write bit line WBL_L. The write data output from the inverter 134L and the write data output from the inverter 134LB Is to construct complementary format write data.

  The inverter 161 has an input terminal connected to the data output terminal of the FF 160 and an output terminal connected to the input terminal of the inverter 162. The inverter 161 inverts the write data output from the data output terminal of the FF 160 and inputs it to the inverter 162.

  The inverter 162 has an input terminal connected to the input terminal of the inverter 161, and an output terminal connected to the input terminals of the inverters 131U and 131L and one input terminal of the NAND circuits 132UB and 132LB.

  The inverter 162 inverts the inverted value of the write data input from the inverter 161 and inputs the inverted value to the input terminals of the inverters 131U and 131L and one input terminal of the NAND circuits 132UB and 132LB.

  The output of the inverter 162 is write data obtained by delaying the write data output from the FF 160 by the delay time of the inverters 161 and 162. The delay times of the inverters 161 and 162 are set so that the timing matches the selection signals net_A and net_B output from the selection circuit 120.

  The inverters 161 and 162 are provided for amplifying the write data output from the FF 160 through the transmission path.

  In the SRAM 100 including the circuit as described above, the normal operation means a time when data is written or read except when an operation test at the time of manufacturing is performed. The test time refers to a time when an operation test at the time of manufacturing is performed.

  In the SRAM 100 during normal operation, the signal level of the input terminal 120C is L level. Therefore, in the circuit of FIG. 7, an L level signal is input to the inverter 125 and the output of the inverter 125 is H level.

  At this time, when the most significant bit value AD [2] of the column address of H level (“1”) is input to the input terminal 120A in order to select the upper side sub-block 110U, the output of the NAND circuit 122U Becomes H level, and the output of the NAND circuit 122L becomes L level.

  In this state, when the write clock WCK input to the input terminal 120B rises to H level, the output of the NAND circuit 123U goes to L level, and the selection signal net_A output from the inverter 124U rises to H level. Further, the output of the NAND circuit 123L becomes H level, and the selection signal net_B output from the inverter 124L is held at L level.

  That is, the selection signal net_A rises to the H level, and the selection signal net_B is held at the L level. The signal levels of the selection signals net_A and net_B at this time reflect the value of the most significant bit value AD [2] of the column address held at the H level in order to select the upper side sub-block 110U. .

  The H level selection signal net_A and the L level selection signal net_B are input to the drivers 130U and 130L, respectively.

  When the H level write data WD is output from the FF 160, the NAND circuit 132U receives the L level signal inverted by the inverter 131U and the H level selection signal net_A. The output of 132U becomes H level. As a result, the output of inverter 133U becomes L level.

  In addition, since the H level signal output from the inverter 162 and the H level selection signal net_A are input to the NAND circuit 132UB, the output of the NAND circuit 132UB is at the L level. As a result, the output of inverter 133UB rises to the H level.

  As a result, the output of inverter 134U is held at the H level, and the output of inverter 134UB falls to the L level.

  Accordingly, the write data is transferred to the memory cell 111 in the column specified by the bit value AD [1: 0] of the lower 2 bits of the column address of the upper sub-block 110U via the write amplifier 140U and the write column selection circuit 150U. “1” is written.

  On the other hand, since the L level signal inverted by the inverter 131L and the L level selection signal net_B are input to the NAND circuit 132L, the output of the NAND circuit 132L becomes the H level. As a result, the output of the inverter 133L becomes L level.

  In addition, since the H level signal output from the inverter 162 and the L level selection signal net_B are input to the NAND circuit 132LB, the output of the NAND circuit 132LB is at the H level. As a result, the output of inverter 133LB becomes L level.

  As a result, the output of inverter 134L is held at H level, and the output of inverter 134LB is also held at H level.

  Therefore, write data is not written to the lower side sub-block 110L.

  Here, the case where write data is written to the upper side sub-block 110U has been described, but the same applies to the case where write data is written to the lower side sub-block 110L.

  As described above, during normal operation, write data is written to either the upper side sub-block 110U or the lower side sub-block 110L selected by the most significant bit value AD [2] of the column address. It is.

  FIG. 8 is a timing chart showing a write operation during normal operation of the SRAM 100 of the embodiment.

  FIG. 8 shows the system clock CLK, the write data WD, the write clock WCK, the test control signal CT, the selection signals net_A, net_B, the signal level of the signal line net_C, and the signal levels of the write bit lines WBL_U, WBLB_U, WBL_L, WBLB_L. Show.

  The timing chart shown in FIG. 8 corresponds to the operation described with reference to FIG. That is, FIG. 8 shows an operation of writing H level write data to the upper side sub-block 110U during normal operation.

  First, the write data WD becomes H level at time t11, and the system clock CLK rises at time t12 thereafter. In this manner, the write data WD is set to a level at which writing is desired before the system clock CLK rises.

  Further, a short pulse of H level reflecting only the rising edge of the system clock CLK is input to the clock input terminal of the FF 160. As a result, the FF 160 reflects the write data input to the data input terminal on the data output terminal.

  At time t13, the signal level of the signal line net_C becomes H level. This indicates that the write data reflected on the data output terminal of the FF 160 at time t12 is delayed by the inverters 161 and 162 and output to the signal line net_C.

  Next, at time t14, the write clock WCK rises. The write clock WCK is delayed by a sufficient time (period from time t11 to t14) with respect to the system clock CLK so as to rise in a state where the write data is reliably reflected on the data output terminal of the FF 160.

  Next, at time t15, the selection signal net_A rises and the selection signal net_B is held at the L level. The rising edge of the selection signal net_A is the result of receiving the rising edge of the write clock WCK.

  At time t16, the write bit line WBLB_U falls. At this time, the write bit lines WBL_U, WBL_L, and WBLB_L are held at the H level.

  As described above, when the write bit line WBLB_U falls at time t16, the memory cell specified by the column specified by the lower 2 bits of the column address in the upper side sub-block 110U and the word line H-level write data WD is written in 111.

  Next, the write operation in the operation test will be described.

  FIG. 9 is a diagram illustrating details of a circuit used in the SRAM 100 of the embodiment. FIG. 9 shows the signal level of each signal during a write operation in an operation test during manufacturing.

  In the SRAM 100, since the signal level of the input terminal 120C is H level during the operation test, an H level signal is input to the inverter 125 and the output of the inverter 125 is L level in the circuit of FIG.

  At this time, when the most significant bit value AD [2] of the column address of H level (“1”) is input to the input terminal 120A in order to select the upper side sub-block 110U, the output of the NAND circuit 122U Becomes H level and the output of the NAND circuit 122L also becomes H level.

  In this state, when the write clock WCK input to the input terminal 120B rises to H level, the output of the NAND circuit 123U goes to L level, and the selection signal net_A output from the inverter 124U rises to H level.

  Further, the output of the NAND circuit 123L becomes L level, and the selection signal net_B output from the inverter 124L also rises to H level.

  That is, during the operation test, the selection signals net_A and net_B both rise to the H level. The signal levels of the selection signals net_A and net_B at this time are forcibly set to the H level regardless of the value of the most significant bit value AD [2] of the column address. This is because the H level outputs of the NAND circuits 122U and 122L to which the L level signal is input from the inverter 125 are input to the NAND circuits 123U and 123L, respectively.

  The H level selection signals net_A and net_B are input to the drivers 130U and 130L, respectively.

  When the H level write data WD is output from the FF 160, the NAND circuit 132U receives the L level signal inverted by the inverter 131U and the H level selection signal net_A. The output of 132U becomes H level. As a result, the output of inverter 133U is held at the L level.

  In addition, since the H level signal output from the inverter 162 and the H level selection signal net_A are input to the NAND circuit 132UB, the output of the NAND circuit 132UB is at the L level. As a result, the output of inverter 133UB rises to the H level.

  As a result, the output of inverter 134U is held at the H level, and the output of inverter 134UB falls to the L level.

  Accordingly, the write data is transferred to the memory cell 111 in the column specified by the bit value AD [1: 0] of the lower 2 bits of the column address of the upper sub-block 110U via the write amplifier 140U and the write column selection circuit 150U. “1” is written.

  The NAND circuit 132L receives the L level signal inverted by the inverter 131L and the H level selection signal net_B, so that the output of the NAND circuit 132L becomes the H level. As a result, the output of inverter 133L is held at the L level.

  Further, since the H level signal output from the inverter 162 and the H level selection signal net_B are input to the NAND circuit 132LB, the output of the NAND circuit 132LB is at the L level. As a result, the output of inverter 133LB rises to the H level.

  As a result, the output of inverter 134L is held at the H level, and the output of inverter 134LB falls to the L level.

  Therefore, the write data is transferred to the memory cell 111 of the column specified by the bit value AD [1: 0] of the lower 2 bits of the column address of the sub-block 110L on the lower side via the write amplifier 140L and the write column selection circuit 150L. “1” is written.

  As described above, in the operation test, write data is written to both the upper side sub-block 110U and the lower side sub-block 110L regardless of the most significant bit value AD [2] of the column address.

  As described above, during the operation test, the write data is written to both the upper side and lower side sub-blocks 100U and 110L regardless of the value of the most significant bit value AD [2] of the column address. The sub block (100U or 100L) to be subjected to the operation test is a sub block specified by the most significant bit value AD [2].

  Therefore, the operation test may be performed in two ways: when the most significant bit value AD [2] of the column address is “1” and when it is “0”.

  FIG. 10 is a timing chart showing a write operation during an operation test of the SRAM 100 of the embodiment.

  In FIG. 10, the system clock CLK, the write data WD, the write clock WCK, the test control signal CT, the selection signals net_A, net_B, the signal level of the signal line net_C, and the signal levels of the write bit lines WBL_U, WBLB_U, WBL_L, WBLB_L are shown. Show.

  The timing chart shown in FIG. 10 corresponds to the operation described with reference to FIG. That is, FIG. 10 shows an operation of writing H level write data during a normal test.

  Since the operation from time t11 to time t14 is the same as the operation in the normal operation shown in FIG. 8, the description thereof is omitted here.

  At time t15, both the selection signal net_A and the selection signal net_B rise. The rising edge of the selection signal net_A and the selection signal net_B is the result of receiving the rising edge of the write clock WCK.

  At time t16, both write bit lines WBLB_U and WBLB_L fall. At this time, the write bit lines WBL_U and WBL_L are held at the H level.

  As described above, when both the write bit lines WBLB_U and WBLB_L fall at time t16, the bit values of the lower 2 bits of the column address in the upper side sub-block 110U and the lower side sub-block 110L are specified. H level write data WD is written into the memory cell 111 specified by the column and the word line.

  That is, at the time of the operation test, it is specified by the column specified by the lower 2 bits of the column address in the adjacent upper side sub-block 110U and the lower side sub-block 110L, and the word line. H level write data WD is written into the memory cell 111.

  Therefore, by continuously changing the lower two bits of the column address, all the memory cells in the upper side sub-block 110U and the lower side sub-block 110L which are adjacent to each other during the operation test are used. In 111, write data can be written in a checkerboard pattern.

  FIG. 11 is a diagram illustrating a state in which write data is written to the memory cell of the SRAM 100 according to the embodiment in a checkerboard pattern. FIG. 11 corresponds to FIG. 3 and includes a lower side sub-block (column [3: 0]), an upper side sub-block (column [7: 4]), and a redundant block (red [3: 0] ]) Data value.

  As described with reference to FIGS. 9 and 10, in the SRAM 100 according to the embodiment, at the time of the operation test, all the memory cells 111 in the adjacent upper side sub-block 110U and lower side sub-block 110L. You can write data to it.

  Therefore, if test data “1” and “0” are alternately written during the operation test, as shown in FIG. 11, the adjacent upper side sub-block (column [7: 4]) and the lower side Test data can be written to both the sub-block (column [3: 0]) using a checkerboard pattern.

  For this reason, the test data written in the checkerboard pattern on both the upper sub-block (column [7: 4]) and the lower sub-block (column [3: 0]) adjacent to each other is read by the LSI tester. If this occurs, it is possible to detect a defect such as the occurrence of a leak between adjacent memory cells.

  Here, using FIG. 12, between memory cells located at the boundary between adjacent upper side sub-blocks (column [7: 4]) and lower side sub-blocks (column [3: 0]). The test data written in each memory cell when a leak occurs will be described.

  FIG. 12 shows that leakage occurs between memory cells located at the boundary between adjacent upper side sub-blocks (column [7: 4]) and lower side sub-blocks (column [3: 0]). FIG. 5 is a diagram showing test data written in each memory cell in a case where the memory cell is read.

  In FIG. 12, as an example, it is assumed that there is a leak between a memory cell in column [3] of the lower side sub-block and a memory cell in column [4] of the upper side sub-block. This is the same case as the case where the leakage in the SRAM of the base technology is described with reference to FIG.

  In FIG. 12, as in FIG. 4, columns [0] to [7] of sub-blocks (column [7: 4], column [3: 0]) are shown in the horizontal direction, and the time axis is shown in the vertical direction. “1” and “0” shown in FIG. 12 represent data values held by the memory cells in the columns [0] to [7] after the time t1, and “x” indicates that the data value is indefinite. .

  Test data is written to columns [7] and [3], [6] for the upper side sub-block (column [7: 4]) and the lower side sub-block (column [3: 0]). ] And [2], [5] and [1], [4] and [0].

  At time t1, since test data is not written in the memory cells in the columns [7] to [0], the data values of the memory cells in the columns [7] to [0] are “x” indicating indefinite. is there.

  At time t2, “1” is written in the memory cells in columns [7] and [3]. At this time, since there is a leak between the memory cell in column [3] and the memory cell in column [4], the memory cell in column [4] to which no test data has been written is set to “1”. Hold.

  Thereafter, from time t3 to time t5, the state in which the memory cell in the column [3] and the memory cell in the column [4] hold “1” continues.

  At time t3, “0” is written in the memory cells in the columns [6] and [2]. At time t4, “1” is written in the memory cells in the columns [5] and [1]. At time t5, “0” is written to the memory cells in the columns [4] and [0].

  As described above, from time t2 to time t5, the memory cells in the columns [7] to [0] and the columns [3] to [0] have “1”, “0”, “1”, “ 0 "test data is written.

  By the way, when “0” is written in the memory cells in the columns [4] and [0] at time t5, there is a leak between the memory cell in the column [3] and the memory cell in the column [4]. The value of the memory cell in the column [3] changes from “1” to “0” (overwritten) due to the influence of the data written in the memory cell in the column [4].

  In such a case, the data value read from the memory cell in column [3] is “0”, which is the data value (expected value) “1” written in the memory cell in column [3] at time t2. Is different and inconsistent.

  Therefore, it is possible to detect that a defect has occurred in the memory cell in column [3].

  Therefore, according to the SRAM 100 of the embodiment, at the time of the operation test, the SRAM 100 is positioned at the boundary between the adjacent upper side sub-block (column [7: 4]) and lower side sub-block (column [3: 0]). It is possible to detect a defect such as a leak generated between memory cells with high accuracy.

  As described above, when there is a leak between the memory cell in column [3] and the memory cell in column [4], the value of the memory cell in column [3] is On the contrary, the value written to the memory cell in column [4] overwrites the value in the memory cell in column [3]. It may be done.

  For this reason, the operation test is performed by performing two kinds of operation tests, when the most significant bit value AD [2] of the column address is “1” and when it is “0”. A defect can be detected regardless of which column [4] is overwritten.

  Next, an operation test procedure of the SRAM 100 according to the embodiment will be described with reference to FIG.

  FIG. 13 is a diagram illustrating an operation test procedure of the SRAM 100 according to the embodiment. This operation test is performed by an LSI tester connected to the test terminal of the SRAM 100.

  First, when the LSI tester starts processing (start), the most significant bit AD [2] of the column address included in the input address is set to “0” (step S1).

  Next, the LSI tester writes checkerboard pattern test data in the memory cells in the columns [3] to [0] (step S2). At this time, the test data of the checkerboard pattern is simultaneously written in the memory cells in the columns [7] to [4].

  Next, the LSI tester reads the test data written in the memory cells in the columns [3] to [0], and stores the test data in the internal memory as a test result (step S3).

  Next, the LSI tester sets the most significant bit AD [2] of the column address included in the input address to “1” (step S4).

  Next, the LSI tester writes checkerboard pattern test data in the memory cells in the columns [7] to [4] (step S5). At this time, the test data of the checkerboard pattern is simultaneously written in the memory cells in the columns [3] to [0].

  Next, the LSI tester reads the test data written in the memory cells in the columns [7] to [4], and stores them in the internal memory as a test result (step S6).

  Next, the LSI tester merges both test results (file information) obtained in step S3 and step S4 into one file information (step S7).

  Next, the LSI tester determines whether there is a defect based on the file information merged in step S7 (step S8).

  If it is determined in step S8 that there is no defect, the LSI tester determines that it is not necessary to replace the defective sub-block with the redundant block (step S9). In this case, the LSI tester ends the process (end).

  If the LSI tester determines that there is a defect in step S8, the LSI tester determines whether the number of defective portions is three or more (step S10).

  If the LSI tester determines in step S10 that the number of defective portions is not 3 or more (S10: NO), it determines that the SRAM 100 that has performed the operation test can be relieved (step S11).

  In this case, since there are one or two defective portions, if a redundant block is used in place of the defective sub-block 110U or 110L, the SRAM 100 can operate without any problem.

  If the LSI tester determines in step S10 that there are three or more defective portions (S10: YES), it determines that the SRAM 100 that has performed the operation test cannot be repaired (step S12).

  In this case, since there are three or more defective portions and only two redundant blocks, the SRAM 100 is a defective product.

  As described above, according to the SRAM 100 of the embodiment, during the operation test, the adjacent upper side sub-block 110U and lower side sub-block are independent of the most significant bit value AD [2] of the column address. Write data is written to both of 110L.

  Accordingly, it is possible to detect a defect such as a leak between the memory cells located at the boundary between the adjacent upper-side sub-block 110U and the lower-side sub-block 110L with high accuracy.

  As described above, according to the embodiment, in the SRAM 100 that operates by dividing the 1-bit memory block 110 in half into the sub-blocks 110U and 110L, the most significant bit AD [2] of the column address is determined during the operation test. Regardless, test data can be written to both sub-blocks 110U and 110L.

  Accordingly, it is possible to detect a defect such as a leak between the memory cells located at the boundary between the adjacent upper-side sub-block 110U and the lower-side sub-block 110L with high accuracy, and to improve reliability. A high SRAM 100 can be provided.

  In addition, although the form which performs an operation | movement test using the test data of a checker board pattern was demonstrated above, test data is not restricted to a checker board pattern. Test data other than the checkerboard pattern may be used as long as the test data can detect a defect between the memory cells 111 at the boundary between adjacent sub-blocks 110U and 110L.

  Finally, a state where the LSI tester 500 is connected to the SRAM 100 of the embodiment will be described with reference to FIG.

  FIG. 14 is a diagram illustrating a state in which the LSI tester 500 is connected to the SRAM 100 according to the embodiment.

  SRAM 100 includes input terminals 100A, 100B, 100C, 100D and an output terminal 100E. The input terminals 100A, 100B, 100C, 100D and the output terminal 100E are connected to the LSI tester 500.

  The most significant bit AD [2] of the column address, the write clock WCK, the test control signal CT, and the write data WD (write test data) are input to the input terminals 100A, 100B, 100C, and 100D, respectively. The output terminal 100E is a terminal from which the LSI tester 500 reads read data from the SRAM 100 in an operation test.

  The LSI tester 500 includes a CPU (Central Processing Unit) chip 501 and an internal memory 502. The internal memory 502 may be a non-volatile memory, for example.

  As described above, the operation test may be performed by connecting the LSI tester 500 to the SRAM 100 and causing the LSI tester 500 to execute the processing of steps S1 to S12 shown in FIG.

  The semiconductor memory device and the test method for the semiconductor memory device according to the exemplary embodiments of the present invention have been described above. However, the present invention is not limited to the specifically disclosed embodiments. Various modifications and changes can be made without departing from the scope of the claims.

100 SRAM
110 memory block 110U, 110L sub-block 120 selection circuit 130U, 130L driver 140U, 140L write amplifier 150U, 150L light column selection circuit 160 FF
210 FF
220 Read multiplexer 230U, 230L Read amplifier 240U, 240L Read column selection circuit 500 LSI tester

Claims (5)

A memory block having a plurality of memory cells for holding data;
A first selection signal for selecting a first column address which is half of column addresses of a plurality of memory cells of the same bit included in the memory block, or of the column addresses of the plurality of memory cells of the same bit; A selection circuit for outputting a second selection signal for selecting the second half of the second column address, when writing test data to the plurality of memory cells, both the first selection signal and the second selection signal; When writing normal data to the plurality of memory cells, a selection circuit that outputs either the first selection signal or the second selection signal;
A first driver that outputs write data to a first memory cell corresponding to the first column address among the plurality of memory cells of the same bit when the first selection signal is at a first level;
A second driver that outputs write data to a second memory cell corresponding to the second column address among the plurality of memory cells of the same bit when the second selection signal is at a first level. Storage device.   2. The semiconductor memory device according to claim 1, wherein the first column address and the second column address of the column addresses are different in the most significant bit value of the column address. The selection circuit includes:
An address input terminal to which the most significant bit value of the column address is input;
A test input terminal to which a test control signal indicating whether to write the test data or the normal data is written to the plurality of memory cells;
A first NAND circuit that outputs a first NAND of the inverted value of the most significant bit value and the inverted value of the test control signal;
A second NAND circuit that outputs a second NAND of the most significant bit value and the inverted value of the test control signal;
3. The semiconductor memory device according to claim 2, wherein the first selection signal is a signal corresponding to the first negative logical product, and the second selection signal is a signal corresponding to the second negative logical product.   The selection circuit has a test input terminal to which a test control signal indicating whether to write the test data or the normal data is written to the plurality of memory cells, and is input to the test input terminal. The semiconductor memory device according to claim 1, wherein both the first selection signal and the second selection signal are output when a test control signal indicates writing the test data to the plurality of memory cells. A memory block having a plurality of memory cells for holding data;
A first selection signal for selecting a first column address which is half of column addresses of a plurality of memory cells of the same bit included in the memory block, or of the column addresses of the plurality of memory cells of the same bit; A selection circuit for outputting a second selection signal for selecting the second half of the second column address, when writing test data to the plurality of memory cells, both the first selection signal and the second selection signal; When writing normal data to the plurality of memory cells, a selection circuit that outputs either the first selection signal or the second selection signal;
A first driver that outputs write data to a first memory cell corresponding to the first column address among the plurality of memory cells of the same bit when the first selection signal is at a first level;
A second driver that outputs write data to a second memory cell corresponding to the second column address among the plurality of memory cells of the same bit when the second selection signal is at a first level. An operation test method in which an operation test of a storage device is performed by a computer,
The computer
A first writing step of writing first test data to a memory cell corresponding to the first column address among a plurality of memory cells of the same bit included in the memory block;
A first read step of reading first test data written in the memory cell corresponding to the first column address in the first write step;
A second writing step of writing second test data to a memory cell corresponding to the second column address among a plurality of memory cells of the same bit included in the memory block;
And a second reading step of reading second test data written in the memory cell corresponding to the second column address in the second writing step.

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