JPH05159561A - Fifo memory circuit - Google Patents

Abstract

PURPOSE:To properly detect a defective-mode occurrence accident when a FIFO memory circuit is tested and to enhance a testing function by in stalling a test circuit wherein a pointer signal selecting a memory cell is output directly to the outside. CONSTITUTION:A test circuit 6 corresponding to a write pointer signal group 107 which is output from a write pointer 4 is added. Thereby, write pointer signals from outside painter lines 201-1 to 201-32 can be output directly via a data output buffer 3. In addition, a test circuit 7 corresponding to a read pointer signal group 108 is added. Thereby, read pointer signals from read pointer lines 202-1 to 202-32 can be output directly via the data output buffer 3. When the test circuits 6, 7 are installed, the defective-mode occurrence accident of a FIFO circuit can be detected properly. Consequently, the testing function of an erroneous selection, a double selection and a nonselection in a memory cell is enhanced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a FIFO memory circuit.

[0002]

2. Description of the Related Art A conventional FIFO memory circuit is provided with a cell array 1, a data input buffer 2, a data output buffer 3, a write pointer 4, and a read pointer 5, as shown in FIG. Consists of Figure 4
, The clock signal 102 is input to the write pointer 4, and the write pointer line 201-
1, 201-2, 201-3, ..., 201-32, the memory cell 1 is serially selected corresponding to this, and the write data 101 to be input.
Is a data input group 104 via the data input buffer 2.
Is input to the memory cell 1 and written in the selected memory cell 1. Similarly, in the read system as well, the clock signal 103 is input to the read pointer 5 and the read pointer lines 202-1 and 202-2 are input every clock.
02-2, 202-3, ..., 202-32, the memory cell 1 is serially selected corresponding to this, and the data in the memory cell is output as the data output group 105. Then, the read data 106 is output via the data output buffer 3.

As described above, in the conventional FIFO memory circuit, the operation of the FIFO memory is restricted by serially inputting and writing data and reading the data serially in the order of input. Therefore, when detecting defective modes such as erroneous selection, double selection and non-selection in a memory cell, normal RA is detected.
In contrast to the fact that the test pattern with high detection power is created by the combination of the address and the data in M, this FI
In the case of the FO memory, the detection performance is improved by variously devising only the input data in the test pattern such that the data of the cell of interest is reversed to the surrounding cells. It is common to have

[0004]

DISCLOSURE OF THE INVENTION The conventional FIF described above
In the O memory circuit, a FIFO that serially selects memory cells at the time of testing the FIFO memory circuit
In the event of a failure such that the pointer signal, which is a main signal inside the O memory circuit, disappears in the middle of the operation, the failure data can be eliminated by devising various input data of the test pattern. Depending on the input data condition of the test pattern, there is a possibility that the defective accident may be missed, and there is a defect that there is a defect in the test function.

[0005]

A FIFO memory circuit of the present invention includes a memory cell, a data input buffer, a data output buffer, a write pointer and a read pointer, and the data input buffer is provided for the memory cell group. In a FIFO memory circuit in which data is serially input via the data write-in via the data output buffer and the data is read out via the data output buffer in the order of input, the data is input to the write pointer during a data write test. Input clock signal and the write point signal group output from the write pointer,
A first test circuit that outputs the write point signal group as a serial signal to the outside through a predetermined test signal, a clock signal that is input to the read pointer during a data read test, and a read signal from the read pointer. And a second test circuit which inputs the output lead point signal group and outputs the lead point signal group as a serial signal to the outside through a predetermined test signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment includes a cell array 1, a data input buffer 2, a data output buffer 3, a write pointer 4, a read pointer 5, and test circuits 6 and 7. It

In FIG. 1, the clock signal 102 is input to the write pointer 4, and the write pointer lines 201-1, 201-2, 201-3, ...
01-32, the memory cell 1 is serially selected corresponding to this, and the write data 101 to be input is input to the memory cell 1 as the data input group 104 via the data input buffer 2. The data is input and written in each of the selected memory cells 1. Similarly, in the read system as well, the clock signal 103 is input to the read pointer 5 and the read pointer lines 202-1, 202-2, 202-3, ...
32, the memory cell 1 is serially selected corresponding to this, and the data in the memory cell 1 is output as the data output group 105, and the read data is output via the data output buffer 3. It is output as 106.

In the present embodiment, the test circuit 6 corresponding to the write pointer signal group 203 output from the write pointer 4 is included in the configuration of these FIFO memory circuits.
By adding the write pointer line 201-1,
The write pointer signals in 201-2, 201-3, ..., 201-32 can be directly output through the data output buffer 3 without passing through the memory cell 1. This also applies to the read system. By adding the test circuit 7 corresponding to the read pointer signal group 108 output from the read pointer 5, the read pointer lines 202-1, 202-2, and 2-2 are added.
The read pointer signal in 02-3, ..., 202-32 can be directly output through the data output buffer 3 without passing through the memory cell 1.

Next, an embodiment of the test circuit 6 is shown in FIG. 2, and operation timing charts in the test circuit 6 are shown in FIGS. 3 (a), (b), (c), (d) and (f). And (g). As shown in FIG. 2, the test circuit 6
Is a shift register 8 and an NMOS transistor 9-1.
.About.9-32, 10 and 11, and inverters 12 and 13.

In FIG. 2, the test signal 109 is set to the high level and the test signal 110 is set to the low level to enter the test mode, and the clock signal 102 is input to the shift register 8, whereby the write pointer 4 is input.
In response to the input of the write pointer signal group 107 from
NMOS transistors 9-1, 9-2, 9-3, ...
…, 9-32 are turned on sequentially every clock,
Write pointer signals 107-1, 107-2, 107-
, ..., 107-32 are converted into serial signals and output as signals 111 (see FIG. 3G) via the NMOS transistor 10 and the inverters 12 and 13. This makes it possible to externally check the operation of the write pointer 4. This is exactly the same for the read system, and the operation of the read pointer 5 can be externally checked via the test circuit 7 corresponding to the read pointer signal group 108.

When the test signal 109 is at low level and the test signal 110 is at high level, the normal operation state of the FIFO memory circuit is set and the memory cell 1
The data read from the read data line 203 via the read data line 203 is output to the outside as read data via the NMOS transistor 11 and the inverters 12 and 13.

[0013]

As described above, according to the present invention, the FIF
By providing a test circuit which is applied to an O memory circuit and directly outputs a pointer signal for selecting a memory cell to the outside, during the test of the FIFO memory circuit,
Even when a defective situation occurs such that the pointer signal disappears in the test process, the defective accident can be accurately detected, and the defect in the test function can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of a test circuit in this embodiment.

FIG. 3 is a timing diagram of operation signals in the test circuit.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

1 memory cell 2 data input buffer 3 data output buffer 4 write pointer 5 read pointer 6, 7 test circuit 8 shift register 9-1, 9-2, 9-3, ..., 9-32, 10, 11
NMOS transistor 12, 13 Inverter

Claims (1)

[Claims] 1. A memory cell, a data input buffer, a data output buffer, a write pointer, a read pointer and the like are included, and data is serially input to the memory cell group through the data input buffer to perform writing. In the FIFO memory circuit in which the data is read out through the data output buffer according to the input order, the clock signal input to the write pointer and the output from the write pointer in the data writing test. A write point signal group for inputting the write point signal group, and outputting the write point signal group as a serial signal to the outside through a predetermined test signal; Input clock signal and output from the read pointer Enter the over de point signal group, through a predetermined test signal, FIFO memory circuit, characterized in that and a second test circuit for outputting the read point signal group to the outside as a serial signal.