JPH03268293A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To read out delayed data through simple configuration by storing beforehand a desired write-in address at the time of starting the read-out of a memory cell, and starting the read-out sequentially when the write-in address and a present write-in address coincide with each other. CONSTITUTION:The write-in address at the time of starting the read-out is stored beforehand in a delay register 27. A write-in pointer 23 is increased successively at the rise-up of a write-in clock W, and data is written in the corresponding address of the memory cell 22. When the pointer 23 outputs the address WP stored in the register 27, a read-out pointer 25 is reset through an exclusive OR signal EOR, and the read-out is started sequentially from 0-address of the memory cell 22. Thus, an external counter becomes unnecessary, and the data can be read out by delaying it later than the write-in through the simple configuration.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a FIFO (First4n) that sequentially accesses memory cells.
The present invention relates to semiconductor storage devices such as first-out (first-out) memories.

FIFO memory is generally used as a line memory in devices that scan image information, such as TVs, fax machines, and copiers. , it is possible to perform image processing to remove noise.

In order to perform these image processes, it is necessary to write the image information for one scanning line into the FIFO memory and then output it in synchronization with the scanning of the next scanning line.
It is necessary to generate a predetermined delay between the input and output to the O-mechanism.

[Conventional technology]

FIG. 4 shows a schematic configuration of a conventional FIFO memory 1, in which 2 is a memory cell that inputs and outputs data, 3 is a write pointer that outputs a data write address WP to the memory cell 2, and 4 is a write pointer that outputs input data DIN. A write circuit for writing to memory cell 1; 5 is a read pointer for outputting read address RP to memory cell 2 for reading data written to memory cell 1; 6 is a read pointer for outputting the read address RP for reading data written to memory cell 1 to data D; . This is a readout circuit that outputs as IIT.

In the above configuration, the write pointer 3 is set to a sequential write address WP by the write clock W.
The write circuit 4 sequentially outputs the input data DIN to the memory cells 2 using the write clock W. Therefore, the input data DIN is sequentially written to the addresses specified by the write pointer 3.

Similarly, the read pointer 5 generates a sequential read address RP based on the read clock R,
Therefore, the read circuit 6 reads data using the read clock π, and obtains data D. Output as U.

Note that the addresses of the write pointer 3 and read pointer 5 are reset to address 0 by the write reset signal R3T%4 and the read cent signal R3T, respectively.

In such a FIFO memory 1, data writing and reading are performed independently and asynchronously, so
The memory cell 2 is usually a dual port type memory cell, and as shown in FIG. 5, this memory cell is a flip-flop consisting of a storage transistor 13. 10 is used.

The flip-flop 10 includes write transfer transistors 15 and 16, write side bit lines BLW, Wτ
The gates of write transfer transistors 15 and 16 are both connected to the write pointer 3 via a write word line W L u . Therefore, write word line WLw
The data on the write side bit lines BL, 1, BLw when selected by the write pointer 3 is written to the flip-flop 10.

The flip-flop 10 also includes readout transfer transistors 17 and 18, a readout side bit line BL,
, B10 to the readout circuit 6, and the gates of the readout transfer transistors 17 and 18 are both connected to the readout pointer 5 via the readout side word line WLR. Therefore, when the read side word line WLR is selected by the read pointer 5, the data stored in the flip-flop 10 is transferred to the read side bit line BLR.

It is read out onto BLw.

FIG. 6 is a timing chart showing the operation of the FIFO memory according to the above configuration.

After power is applied, when the write reset signal R3TW is input, the write pointer 3 is reset and the write address WP at address 0 is generated, and then the write clock W is input.
When becomes low level, the input data DO at that time is written to address 0 of the flip-flop 10. The write pointer 3 is sequentially incremented at the rising edge of the write clock W and specifies addresses 1, 2, and so on, so that data D1, D2, and so on are sequentially transferred to the flip-flop 1.
It is written to addresses 1 and 2 of 0.

Similarly, in the case of reading, the read reset signal R3
When TR is input, the read pointer 5 is reset to generate a read address RP at address O, and then when the read clock 100 becomes low level, the data DO stored at address 0 of the flip-flop 10 is read out. Next, when the read clock R rises, the read pointer 5 is incremented to designate the first read address RP and prepare for the next read.

Therefore, according to the above configuration, writing and reading of data are performed independently and sequentially using the write clock W and the read clock 100.

FIG. 7 shows a timing chart when data output is delayed by 3 bits from data input in the above configuration.

In this example, after the write reset signal R3T is input, three pulses of the write clock W are counted by an external counter (not shown), and then the read reset signal R3TR is input. Therefore, in this case, when the fourth data D3 is input, 1
The th data Do is output.

That is, when using the above conventional FIFO as a line memory or delay line in a device that scans image information such as a TVSFAX or a copy machine, desired delay data can be read out by using an external counter. .

(Problems to be Solved by the Invention) However, the conventional semiconductor memory device described above has a problem in that the circuit configuration becomes complicated because data is read out with a delay from writing using an external counter.

SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a semiconductor memory device that can read delayed data with a simple configuration.

[Means to solve the problem]

In order to achieve the above object, the present invention, as shown in FIG. a storage means for storing in advance a write address of the first address generation means; and a first address generating means for starting generation of sequential read addresses and outputting them to the memory cells when the write address of the first address generation means and the write address of the storage means match. 2 address generating means.

[Effect]

With the above configuration, the present invention stores in advance a desired write address at the time of starting reading of the memory cell, and starts reading when this write address matches the current write address. Therefore, there is no need for an external counter as in the conventional example, and the delayed data can be read out with a simple configuration.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. FIGS. 2 and 3 are diagrams showing an embodiment of a semiconductor memory device according to the present invention.

In FIG. 2, 21 is a FIFO memory;
The O memory 21 has memory cells 22 arranged in a matrix with respect to a plurality of bit lines and word lines, as shown in FIG.

23 is a write pointer that outputs the write address WP to the memory cell 22 according to the write reset signal R3Tw and the write clock W, and 24 is the write clock W.
25 is an internal read reset signal R3Ti.
z and the read clock “, the read address RP
A read pointer 26 outputs data to the memory cell 22, and 26 is a read circuit that reads data from the memory cell 22 using a read clock R.

27 is a delay register in which a write address at the start of reading of the memory cell 22 is set in advance; 28 is an exclusive OR signal EOR of the write address WP from the write pointer 23 and the write address from the delay register 27;
28 is an AND circuit that outputs an AND signal of the external read reset signal R3TRI, the exclusive 0 OR signal F, and OR as the internal read reset signal R8TR2.

Next, the operation of the above embodiment will be explained with reference to FIG.

FIG. 3 shows a timing chart when the data output is delayed by 3 bits from the data input, as in the conventional example, and the delay register 27 has the write address "3".
is stored in advance.

When the write reset signal R3Tt+ is input after power is applied, the write pointer 23 is reset and the write address WP of address 0 is generated, and when the write clock W becomes low level after that, the input data DO at that time is
is written to address O of the memory cell 22. The write pointer 23 is sequentially incremented at the rising edge of the write clock W and specifies addresses 1, 2, etc., so that data DI, D2, etc. are sequentially written into the memory cells 2201, 2, and so on.

Write pointer 23 is write address wp at address 3
When the write address WP matches the write address "3" of the delay register 27, the exclusive OR signal FOR becomes low level, and therefore the internal read cent signal πS T RZ becomes low level.

The read pointer 25 is reset by this internal read reset signal R3TR2 to generate the read address RP at address O, and then when the read clock R becomes low level, the data DO stored at address 0 of the memory cell 22 is read out. . Next, when the read clock 100 rises, the read pointer 25 is incremented and specifies the read address RP at address 1,
Prepare for next readout.

Therefore, according to the above embodiment, the write address at the start of reading is stored in advance in the delay register 27, and when this write address matches the current write address, the read pointer 25 is reset and reading is started. There is no need for an external counter as in the conventional example, and data can be read with a delay from writing with a simple configuration 1 2 .

In the above embodiment, the write address at the start of reading is stored in advance in the delay register 27.
M may also be used.

〔Effect of the invention〕

As described above, according to the present invention, delay data can be read out with a simple configuration, eliminating the need for an external counter and simplifying the circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2.3 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram thereof, and FIG. 4 to 7 are diagrams showing a conventional semiconductor memory device, FIG. 4 is a block diagram thereof, FIG. 5 is a detailed block diagram of FIG. 4, and FIG. 6 is a diagram showing a conventional semiconductor memory device. FIG. 7 is a timing chart showing the operation of the apparatus shown in FIGS. 4 and 5 at the time of a 3-bit delay. 22...Memory cell, 23...Write pointer (first address generation means), 25...Read pointer (second address generation means), 27... ...Delay register (storage means), 28...
...Exclusive OR circuit, 29...AND circuit. 3 4 Timing chart for 3-bit delay showing the operation of the device shown in Figs. 4 and 5.

Claims (1)

[Claims] Generates sequential write addresses and writes FIFO
a first address generation means for outputting to a memory cell of a memory; a storage means for storing an arbitrary write address of the memory cell in advance; a write address of the first address generation means and a write address of the storage means; A semiconductor memory device comprising second address generation means that starts generating sequential read addresses and outputs them to memory cells when they match.