JPH05242668A - Tap address loading circuit for memory and method thereof - Google Patents

Abstract

PURPOSE: To perform splitting transfer in a system without restriction by loading the tap address of a transferred serial access memory. CONSTITUTION: A tap address TA is latched 12 through a buffer 11. When splitting transfer of VRAM is started, clock signals A-D are generated 14. The signal A has the reverse phase of an inverted RAS signal, and the signal B has the same phase as an SC signal. The signal C becomes a high state, when the output of a serial address counter AD is the last address of a split SAM during transfer, the signal D becomes a low state from a high state, according to the low state of an inverted CAS signal in a splitting transfer cycle and becomes high state after new TA is inputted to AD. From among the last address of SAM inputted to a control part 15 of the respective signals A-D during transfer and the falling edge of the inverted CAS signal in read transfer, a next tap address is impressed on AD 13 with a later timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tap address loading circuit for splitting transfer of a video random access memory (hereinafter referred to as "VRAM") and a method thereof, and more particularly, in a section where split transfer of VRAM is prohibited. Also relates to a tap address loading circuit and method for enabling tap loading.

[0002]

2. Description of the Related Art An image memory is a reproduction storage device for storing image information, and the image information read from the image memory is converted into a video signal and displayed on a display device. Such an image memory is a random access memory (hereinafter,
“RAM” and serial access memory (hereinafter “SA”)
In the data transfer mode between the RAM and the SAM, there are read transfer, write transfer, pseudo write transfer, split read transfer, split write transfer and the like.

In the above-mentioned data transfer mode, split read transfer is performed on an upper split RAM and an upper SAM divided into a lower split RAM and an upper split SAM and a lower split SAM. Alternatively, data is loaded into the lower split SAM, and in split write transfer, data is loaded from the upper or lower split SAM into the upper or lower split RAM. Also,
In a split transfer mode such as split read transfer or split write transfer, either one of the upper and lower split SAMs can be used as the split SA.
While split read transfer or split write transfer is being performed in M, the other split SA
In M, data at tap positions (addresses corresponding to upper and lower division positions) designated from the outside can be serially shifted and input or output.

FIG. 1 is a block diagram of a conventional tap address loading circuit. As shown in FIG. 1, the column address used as the tap address position in the split SAM is a column address strobe (hereinafter referred to as "inverted CAS") for designating the next tap address position of the split SAM to be transferred next during split transfer. At the falling edge (that is, the strobe start point) of the signal "", the data is stored in the latch unit 2 from the buffer 1. The column address stored in the latch unit 2 is transferred to the serial address counter 3 by a flag signal generated when the address of the serial address counter 3 is counted and reaches the end of the split SAM currently transferred. The address transferred to the serial address counter 3 becomes the tap address position of the split SAM to be transferred next, and the serial SAM counter 3 counts from the tap address position and specifies the address of the split SAM. Data will be transferred from the specified tap position.

[0005]

However, in the prior art, when a split transfer operation occurs in a certain portion of the section where the address of the split SAM to be transferred next starts and in the section where split transfer is prohibited, an erroneous tap address is generated. There is a problem that the serial address counter is loaded.

Therefore, an object of the present invention is to solve the above-mentioned conventional disadvantages and to provide a split SA.
The system handles the split transfer that occurs in a section where the split transfer of the fixed part of the part where the address of M starts and the fixed part of the end is prohibited, V
To provide a tap address loading circuit and a loading method thereof in split transfer of RAM.

[0007]

According to the present invention, a tap address of a serial access memory to be transferred next in a split transfer mode of a video random access memory including a serial access memory composed of first and second split serial access memories is provided. A circuit for loading, a column address buffer for storing a column address used as a tap position in split transfer of the second split serial access memory, and a latch unit for latching the column address according to a column address strobe signal , A serial address counter for receiving the latched column address and sequentially generating an address to be transferred next, a clock A having a phase opposite to that of the row address strobe signal, and a same phase as the serial clock signal. Have a clock B, a clock C which goes high when the address of the serial address counter designates the end of the first split access memory being transferred, and a high to low level when the column address strobe signal goes low in the split transfer cycle. A clock generator that generates a clock D that goes to a high state after a new tap address is input to the serial address counter after transition to the state, and a first split that is transferred with the clock signal of the clock generator as an input signal. A tap loading control means is provided for controlling the tap address loading to the serial address counter in synchronism with the last address of the serial access memory and the falling edge of the column address strobe signal of the split transfer cycle at a late timing.

Preferably, the tap loading control means detects the last address of the first split serial access memory transferred from the clocks A, B and C, and the column address strobe for split transfer. Inversion means for inverting the clock D signal containing the signal information of the falling edge of the signal, and second detection means for outputting a signal synchronized with a later timing among the outputs of the detection means and the inversion means. May be included.

Further, preferably, the first detecting means is a first inverter having an input terminal connected to the clock A signal line of the clock generator, and a second inverter having an input terminal connected to the output terminal of the first inverter. A third inverter having an input terminal connected to an output terminal of the second inverter, and a third inverter
A first NAND gate whose input terminals are connected to the output terminal of the inverter and the clock A signal line, and a second NAND gate whose respective input terminals are connected to the clock B signal line and the clock C signal line of the clock generator When,
A fourth inverter having an input terminal connected to the output terminal of the second NAND gate, a fifth inverter having an input terminal connected to the output terminal of the fourth inverter, and a fifth inverter having an input terminal connected to the output terminal of the fifth inverter. 6 inverters and 6th
A seventh inverter having an input terminal connected to the output terminal of the inverter, and a first Nth having input terminals connected to the output terminal of the seventh inverter and the output terminal of the fourth inverter, respectively.
The OR gate and the drain terminal are connected to the power supply voltage Vcc, the drain terminal is connected to the source terminal of the P-type FET whose gate terminal is connected to the output terminal of the first NAND gate, and the gate terminal is connected to the output terminal of the first NOR gate. N-type FE that is connected and has its source terminal connected to the power supply voltage Vcc
T, a ninth inverter whose input terminal is connected to the drain terminal of the N-type FET, and a tenth inverter whose input terminal is connected to the output terminal of the ninth inverter and whose output terminal is connected to the drain terminal of the N-type FET May be included.

As another preferable example, the tap address of the split serial access memory to be transferred next in the split transfer mode of the video random access memory including the serial access memory including the first and second split serial access memories is designated. To detect the last address of the first split serial access memory, detecting the falling edge of the column address strobe signal, and the first split serial access. The last address of the memory is compared with the timing of the falling edge of the detected column address strobe signal, and a new tap address for the second split serial access memory is synchronized with the later timing. The scan may include the steps of loading the address counter.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 2 is a configuration diagram of the tap address loading circuit 9 according to the embodiment of the present invention. As shown in FIG. 2, the configuration of the tap address loading circuit according to the embodiment of the present invention is transferred next. Column address buffer 1 for storing tap address of split SAM
1, a latch unit 12 that latches a column address that is the tap address according to an inverted CAS signal, and a serial address counter 13 that receives the latched column address and sequentially generates an address to be transferred next.
A clock generator 14 and a tap address loading controller 15 connected to the clock generator 14.

The operation of the tap address loading circuit having the above structure is as follows. The operation in which the tap address is latched by the latch unit 12 through the column address buffer 11 is the same as the conventional one. When the split transfer of the VRAM is started, the clock generator 14 generates and outputs a clock signal defined as follows.

Clock A: RAS inverted every transfer cycle
Clock signal having the opposite phase of the signal Clock B: Clock signal having the same phase as the SC signal Clock C: When the output of the serial address counter designates the last address of the split SAM currently being transferred, it goes to the high state Clock signal Clock D: Inverted CA in split transfer cycle
When the S signal is in the low state, the clock signal is changed from the high state to the low state and then becomes the high state after a new tap address is input to the serial address counter. 15 is input, the tap loading control unit 15 determines that the split SA currently being transferred is present.
The next tap address is applied to the serial address counter 13 at a later timing among the last address of M and the falling edge of the inverted CAS signal of the split (read) transfer.

FIG. 3 is a detailed view of the tap loading controller 15 according to the embodiment of the present invention. As shown in FIG. 3, the tap loading controller 1 according to the embodiment of the present invention.
In the configuration of No. 5, the first detection unit 25 for detecting the last address of the first split SAM transferred from the clocks (A, B and C) described above, and the rising of the inverted CAS signal during the split transfer. Of the outputs of the inverting unit 35 for inverting the clock D signal including the signal information of the falling edge, and the outputs of the first detecting unit 25 and the inverting unit 35,
Second for outputting signals synchronized with late timing
It is composed of a detector 45.

The first detecting section 25 includes a clock generating section 1
A first inverter 51 whose input terminal is connected to the clock A signal line (CLK A) of No. 4, and a second inverter 52 whose input terminal is connected to the output terminal of the first inverter 51;
A third inverter 53 having an input terminal connected to an output terminal of the second inverter 52, and two inputs having respective input terminals connected to an output terminal of the third inverter 53 and a clock A signal line (CLK A) First NAND gate 5
4 and the clock B signal line (CLK
B) and a clock C signal line (CLK C) having two input second NAND gates 55 having respective input terminals connected to each other
A fourth inverter 56 having an input terminal connected to the output terminal of the second NAND gate 55, a fifth inverter 57 having an input terminal connected to the output terminal of the fourth inverter 56, and a fifth inverter 57. A sixth inverter 58 having an input terminal connected to the output terminal, a seventh inverter 59 having an input terminal connected to the output terminal of the sixth inverter 58, an output terminal of the seventh inverter 59 and a fourth inverter 59.
A two-input first NOR gate 60 whose input terminals are connected to the output terminal of the inverter 56, and a power supply voltage Vc
P-type F in which the drain terminal 62a is connected to c and the gate terminal 62b is connected to the output terminal of the first NAND gate 54
ET (Field Effect Transisto)
r) 62, an N-type FET 63 in which the drain terminal 63a is connected to the source terminal of the P-type FET 62, the gate terminal 63b is connected to the output terminal of the first NOR gate 60, and the source terminal 63c is connected to the power supply voltage Vss; Type FE
A ninth inverter 64 having an input terminal connected to the drain terminal 63a of T63, and a tenth inverter 65 having an input terminal connected to the output terminal of the ninth inverter 64 and an output terminal connected to the drain terminal 63a of the N-type FET 63. Composed of and.

On the other hand, the inverting section 35 is composed of an eighth inverter 61, and the second detecting section 45 is an N-type FET 63.
From a two-input second NOR gate 66 whose input terminals are connected to the drain terminal and the output terminal of the eighth inverter 61, and an eleventh inverter 67 whose input terminal is connected to the output terminal of the second NOR gate 66. Become.

The operation of the tap loading controller having the above structure will be described with reference to the waveform chart of the tap loading controller of FIG. When the clock A signal (CLK A) having the inverted phase of the inverted RAS signal is input to the tap loading controller 15, the first inverter 51, the second inverter 52, the third inverter 53, and the first NAND gate 54 cause the clock of FIG. A pulse having a negative value is output from the first NAND gate 54 at the rising edge of the A signal (CLK A). In addition, the clock B signal (CLK B) and the clock C signal (CLK B
C) is input to the tap loading controller 15, the second NAND gate 55 and the fourth inverter 56 are input.
Therefore, the potential at point A is like the waveform A in FIG. Therefore, the fifth inverter 57, the sixth inverter 58, the seventh inverter 59 and the first NOR gate 60 output a pulse having a positive value at the falling edge of the waveform at point A of FIG. It Further, when the clock D signal (CLK D) is input to the tap loading controller 15, the eighth inverter 6
The inverted phase of the clock D signal (CLK D) is output to 1.

The potential at the point B is the P-type FET 62 which is turned on when the output of the first NAND gate 54 is in the low state,
The N-type FET 63 that is turned on when the output of the first NOR gate 60 is in the high state, the ninth inverter 64, and the tenth
This appears as the waveform B of FIG. 4 by the latch formed of the inverter 65. Therefore, the output OUT of the tap loading controller 15 is output to B as shown in FIG. 4 by the second NOR gate 66 and the eleventh inverter 67.
A waveform is obtained by ORing the potential of the point and the output signal of the eighth inverter 61. Such an output OUT waveform means that the serial address counter 3 is loaded with the tap address at a later timing of the last address of the split SAM currently being transferred and the falling edge of the inverted CAS signal in the read transfer. .. That is, the tap address loading is limited to the portion shown by the dotted line of the output OUT waveform in FIG.

[0020]

As described above, according to the present invention, in the section where the split transfer is prohibited in the fixed portion of the section where the address of the split SAM starts and the fixed portion of the end section,
Split transfers can be handled without restrictions in the system.

The above-described effects of the present invention can be used in all information processing equipment using a VRAM for transmitting image information using split transfer.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a conventional tap address loading circuit.

FIG. 2 is a configuration diagram of a tap address loading circuit according to an embodiment of the present invention.

FIG. 3 is a detailed circuit diagram of a tap loading controller according to an exemplary embodiment of the present invention.

FIG. 4 is a waveform diagram of a tap loading controller according to an embodiment of the present invention.

[Explanation of symbols]

 11 Column Address Buffer 12 Latch Unit 13 Serial Address Counter 14 Clock Generation Unit 15 Tap Address Loading Control Unit 51 First Inverter 52 Second Inverter 53 Third Inverter 54 First NAND Gate 55 Second NAND Gate 56 Fourth Inverter 57 Fifth Inverter 58 6th inverter 59 7th inverter 60 1st NOR gate 61 8th inverter 62 P-type FET 63 N-type FET 64 9th inverter 65 10th inverter 66 2nd NOR gate 67 11th inverter

Claims (4)

[Claims] 1. A circuit for loading a tap address of a serial transfer memory to be transferred next in a split transfer mode of a video random access memory including a serial access memory composed of first and second split serial access memories. A column address buffer that stores a column address used as a tap position during split transfer of the second split serial access memory; a latch unit that latches the column address according to a column address strobe signal; and the latched column A serial address counter for receiving an address and sequentially generating an address to be transferred next, a clock A having a phase opposite to that of the row address strobe signal, and a clock B having the same phase as the serial clock signal. A A clock C that goes high when the address of the address counter designates the end of the first split access memory that is being transferred, and a transition from high to low when the column address strobe signal goes low in the split transfer cycle. A clock generator for generating a clock D that goes high after a new tap address is input to the serial address counter, and a first split serial access memory transferred with the clock signal of the clock generator as an input signal. And a tap loading control means for controlling tap address loading for the serial address counter in synchronism with a late timing of the last address of the column address strobe signal of the split transfer cycle and the falling edge of the column address strobe signal of the split transfer cycle. Circuitry for loading the tap address of the split serial access memory to be transferred next access memory. 2. The tap loading control means includes first detection means for detecting the last address of the first split serial access memory being transferred from the clocks A, B, C, and the split transfer. Inverting means for inverting the clock D signal containing the signal information of the falling edge of the column address strobe signal, and a first means for outputting a signal synchronized with a later timing among the outputs of the detecting means and the inverting means. Circuit for loading the tap address of the split serial access memory transferred next to the video random access memory according to claim 1, comprising two detection means. 3. The first detecting means comprises a first inverter having an input terminal connected to a clock A signal line of a clock generator, and a second inverter having an input terminal connected to an output terminal of the first inverter.
An inverter and a third inverter in which an input terminal is connected to an output terminal of the second inverter
An inverter, a first NAND gate whose input terminal is connected to the output terminal of the third inverter and the clock A signal line, and each input terminal is connected to the clock B signal line and the clock C signal line of the clock generator. And a fourth inverter having an input terminal connected to the output terminal of the second NAND gate, and a fifth inverter having an input terminal connected to the output terminal of the fourth inverter.
An inverter and a sixth inverter in which an input terminal is connected to an output terminal of the fifth inverter
An inverter and a seventh inverter in which an input terminal is connected to an output terminal of the sixth inverter
An inverter, a first NOR gate having input terminals connected to the output terminal of the seventh inverter and an output terminal of the fourth inverter, and a drain terminal connected to the power supply voltage Vcc, and a first NAN
P-type FE in which the gate terminal is connected to the output terminal of the D gate
The drain terminal is connected to the source terminal of T, and the first NOR
The gate terminal is connected to the output terminal of the gate, and the power supply voltage V
N-type FET whose source terminal is connected to cc, and N-type FET whose input terminal is connected to the drain terminal of N-type FET
The input terminal is connected to the output terminal of the inverter and the ninth inverter, and the N-type F
A circuit for loading a tap address of a split serial access memory transferred next to the video random access memory according to claim 2, including a tenth inverter having an output terminal connected to a drain terminal of ET. 4. An address counter for designating a tap address of a split serial access memory to be transferred next in a split transfer mode of a video random access memory including a serial access memory composed of the first and second split serial access memories. A method of loading a tap address, the method comprising: detecting a last address of the first split serial access memory; detecting a falling edge of a column address strobe signal; Address of the detected column address strobe signal is compared with the timing of the falling edge of the detected column address strobe signal, and a new tap address for the second split serial access memory is added in synchronization with the later timing. And a tap address loading method for a split serial access memory to be transferred next in a split transfer mode of the video random access memory.