JPS61162893A - Mos type memory device - Google Patents

Abstract

PURPOSE:To speed up bit line discharge at the time of reading operation and enable high speed reading by making discharge operation continuously after precharge operation. CONSTITUTION:When an address changes and reading operation is started, change point of the address is detected in a pulse generating circuit 2, and precharge is made to bit lines 5, 6 by a precharge circuit 3. After a precharge signal becomes 'H' and precharge is completed, a discharge signal becomes 'H' and discharge of bit lines 5, 6 is made by a discharge circuit 4. After completion of discharge, a word line becomes 'H'. When a memory cell 7 is selected, potential of bit lines 5, 6 changes at once reflecting the content of the memory cell 7, and data are outputted to a data outputting line 10. Thus, potential of the bit line and threshold value VTH are made nearly equal by precharge and discharge of the bit line. Thereby, discharge of the bit line by the memory cell becomes unnecessary, and high speed reading becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bit line precharge circuit for a MOS type memory device.

BACKGROUND OF THE INVENTION In conventional memory circuits, a method of reducing current consumption without slowing down readout time is to generate a pulse corresponding to an address change, delay and shape this pulse, and use it as a precharge signal for a bit line and a word. Methods of generating line selection/mask signals, etc. are known. (For example, IEEE
Iaurnal of 5acVol 5G-17,5
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r 8KX8bit Full 0MOSRAM wH
h6TrCell) A conventional memory circuit will be explained below with reference to FIG. When a change in the address signal as shown in FIG. 4a is input to the address input terminal 21, the pulse generation circuit 22
A precharge signal as shown in FIG. 4bK and a word line selection/mask signal substantially synchronized with the same signal as shown in FIG. 4C are generated and applied to the precharge signal line 31 and word 2B, respectively. . The width T3 of the precharge signal generated by the pulse generation circuit 22 is equal to the bit line 26°26
A time is set for the potential to rise sufficiently to near the power supply potential vDD. After precharging is completed, a selection signal is output to the word line 28, and the contents of the selected memory cell 27 are read onto the bit line 26°26, amplified by the sense amplifier 29, and sent to the output terminal 30. The read results are output.

Problems to be Solved by the Invention In such conventional circuits, precharging causes the pinto line potential to rise to nearly vDD, so the read time is shortened by the bit line potential falling due to the memory cell and reaching the threshold value of the sense amplifier. This is the sum of the time to reach the potential vTH and the time before the sense amplifier is activated. However, the above-described discharge time for lowering the potential on the bit line to vTH is essentially unnecessary regardless of the read operation.

The present invention has been made with these points in mind, and aims to speed up the readout time.In order to solve the above problems, the present invention has been developed by:
A pulse that serves as a precharge signal for the bit line and a pulse that serves as a discharge signal that lowers the bit line potential precharged to vDD to near the threshold of the sense amplifier are generated. This optimizes the bit line potential.

According to the above-described configuration, the present invention discharges the bit line precharged to vDD by the precharge circuit to near the threshold value of the sense amplifier by the discharge circuit. Line vDD to vT
The time required for discharging to H can be eliminated.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the memory circuit of the present invention. In FIG. 1, 1 is an address input terminal, and 2 is a pulse generation circuit, which outputs a precharge signal line 11, a discharge signal line 12, and a word line 8. 3 is a precharge circuit, 4 is a discharge circuit, 7 is a memory cell, and 9 is a sense amplifier, each of which is connected to a pair of bit lines 6.6. 10 is a data output terminal. The operation of the circuit shown in FIG. 1 will be explained with reference to the operation waveform diagram shown in FIG. 2. In FIG. 2, a is the address signal applied to the address input terminal 1, b, a, and d are the waveforms (precharge signal) on the precharge signal line 11 output from the pulse generation circuit 2, and the discharge signal line. Waveform on 12 (discharge signal), word line 8
The upper word line selection signal is the word line selection signal, e is the waveform on the bit line 5.6, and f is the waveform (output signal) on the data output terminal 10.

When the address changes and a read operation is started, the pulse generation circuit 2 detects the change point of the address, and uses this change point as a reference as shown in FIG. 2, a.

A waveform as shown in d is output to the precharge signal line 11, the discharge signal line 12, and the word line 8. First, the word line 8 is at a low logic level (hereinafter abbreviated as "L").

Similarly, the high logic level (also abbreviated as "L") makes the memory cell 7 unselected, the precharge signal becomes "L", and the precharge circuit 3 precharges the bit lines 5 and 6. ◇Width of precharge paris T1 is set to a time sufficient to raise the potentials of both bit lines 6, 6 to near vDD. After the precharge signal becomes 'H#' and the precharge is completed, the discharge signal becomes @
It becomes H# and the bit line 6,
Perform 6 discharges.

The width T2 of the discharge pulse is set to a time sufficient to reduce the potentials of both bit lines 6, 6 to near the threshold value vTH of the sense amplifier 9. Discharge signal is “L”
After the discharge is completed and the word line 8 becomes '
When it becomes H'' and selects memory self, bit line 6.6
The potential changes instantly to reflect the contents of the memory self. This potential change on the bit lines 6, 6 is sensed by the sense amplifier 10, and data is output to the data output line 1o. In this way, by precharging and discharging the bit line, the bit line potential before reading and the threshold voltage vTH of the sense amplifier are made almost the same.
There is no need to discharge from vTH to vTH, allowing high-speed reading.

Effects of the Invention As described above, according to the present invention, the discharge operation that is performed following the precharge operation speeds up the bit line discharge during the read operation, making it possible to perform high-speed read, which is extremely useful.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a memory circuit according to an embodiment of the present invention, Fig. 2 is an operation waveform diagram of its main parts, Fig. 3 is a diagram showing a conventional memory circuit, and Fig. 4 is an operation of its main parts. FIG. 2.22...Pulse generation circuit, 3,23...
...Precharge circuit, 4...Discharge circuit, 7゜27...Memory cell, 9,29.
...Sense amplifier. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1s 2 Figure 3

Claims (1)

[Claims] a pulse generation circuit that generates a first pulse and a second pulse prior to a read operation; a circuit that precharges a bit line with the first pulse; and a circuit that precharges a bit line with the first pulse;
a circuit for discharging a bit line by a pulse, the second pulse is output following the first pulse, and the second pulse discharges the bit line.
A MOS type memory device characterized in that a part of the charge charged by the pulse is discharged.