JPH0312398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a complementary integrated circuit memory (hereinafter referred to as
It is called CMOS RAM. This invention relates to a semiconductor memory device in which the amplitude voltage is reduced, the charging current is reduced, and the access time is made faster by synchronizing internal signals in ).

The conventional edge-sensing CMOS RAM is shown in Figure 1. In the figure, 1
2 is an address input terminal, 2 is an edge detection circuit that detects a change in the edge of the waveform of the address input signal, and 3
4 is a NOR circuit that combines the outputs of a plurality of edge detection circuits, 4 is a plurality of pairs of bit lines that transmit data of memory cells, 5 is a precharge signal φ _P for charging the bit lines, and 6 is a precharge signal φ of 5. _P
7 is a transistor for charging the bit line with the precharge signal, 8 is a word line for selecting a memory cell, 9 is a word line control circuit for controlling the 8 word lines, 10 is a memory cell , 11 is an input/output line commonly connected to a plurality of bit lines via a transistor 12, 12 is a switching transistor that connects the bit line and the input/output line, and 13 is an input/output line that controls the switching transistor 12 to perform a predetermined operation. Y decoder for selecting a pair of bit lines 4; 14 is a memory cell 10;
a sense amplifier for amplifying read data from 15;
1 is an output buffer for taking out data to the outside of the chip, 16 is a wiring for sending the output signal of the sense amplifier to the output buffer, and 17 is an output terminal.

Next, while referring to the timing diagram in Figure 2,
The operation of the circuit shown in the figure will be explained. When an address signal different from the previous cycle is input from address input terminal 1, a single pulse is generated from edge detection circuit 2. Here, the NOR circuit 3 has the function of transmitting a pulse to the next stage when even one of the plurality of edge detection circuits generates a pulse. Due to the pulse generation, the word line 8 is brought to the "L" level by the word line control circuit 9 at time _t0 in FIG. 2, and the memory cell 10 becomes non-selected. Similarly, the precharge signal generation circuit 6 is operated by pulse generation, and the precharge signal φ _P is the second
At time _t1 in the figure, it becomes "L" level and generates a negative polarity signal. The precharge signal φ _P enters the gate of the transistor 7 and is connected to the bit line 4 and the input/output line 11.
is charged to "H" level. Also, at this time, the output of the sense amplifier is set to the "L" level. Thereafter, after charging is completed, _φP returns to the "H" level at time _t2 . Next, after φ _P goes to "H" level, word line control circuit 9 operates, word line 8 goes to "H" level, and memory cell 10 is selected. One of the pair of bit lines 4 is discharged to the "L" level depending on the content stored in the memory cell. At this time, the input/output line 11 is connected to any pair of bit lines via the switching transistor 12, and similarly, one of the pair of input/output lines changes to the "L" level.

Next, when one of the input/output lines goes low to a certain level, 14 sense amplifiers are activated and one of the 16 goes up to high level. then 15
Data is output to the output terminal 17 via the output buffer. After time _t3 in FIG. 2, the bit line and the input/output line continue to discharge and fall to the GND level.

The current that flows during this operation is from t ₀ to t ₃ , and after t ₃ there is no current path between V _CC and GND, and no current flows at all.

In the conventional example, when the address changes, the bit line is charged, the memory cell is selected, and the data is output to the output terminal after passing through the sense amplifier. In other words, a time t ₁ -t ₂ (as shown in FIG. 2) is required for charging the bit line to the "H" level after the address changes and before starting access. This greatly affects access time and has the disadvantage of slowing down access. Furthermore, as the number of bit lines increases with the increase in capacity per chip, charging the bit lines from the GND level to the V _CC level has the disadvantage that the charging current becomes large.

This invention was made in order to eliminate the drawbacks of the conventional devices as described above, and by reducing the voltage amplitude of the bit line and moving the charging period of the bit line after the completion of memory access, it is possible to achieve low power consumption. The purpose of the present invention is to provide a memory device that can be accessed at high speed.

FIG. 3 shows an embodiment of the present invention. What is different from the conventional example shown in FIG. 1 is a sense amplifier output detection circuit 18 that detects the completion of the amplification operation of read data from the memory cell 10 based on changes in the output level of the 14 sense amplifiers, and an output of the output detection circuit 18. An AND circuit 19 as a selection control means performs an AND process between the word line control circuit 6 and the word line control circuit 6, and controls the word line 8 to a non-selected state based on the output of the output detection circuit 18 upon detection. A transistor 21 is provided between the bit line 4 and the transistor 21 as a charge control means which is turned on by a precharge signal b input to the gate via a signal line 20 when the output detection circuit 18 detects the bit line 4 and controls the bit line 4 to a charged state. That's true.

The operation of one embodiment of the present invention will be described with reference to the timing diagram of FIG.

When an address signal different from the previous cycle is input to the address input terminal 1, the edge detection circuit 2 operates, and a negative pulse is generated by the precharge generation circuit 6 via the NOR circuit 3. The process up to this point is the same as the conventional one. In the present invention, since the bit line has already been charged in the previous cycle as described later, the precharge signal a of 5 can be set to "H" in a faster time than the conventional pulse by simply resetting the output of the sense amplifier to "L" level. “It’s going to be on the level. Then, from the word line control circuit 9, the signal passes through the AND circuit 19, and the word line becomes "H" level, and the memory cell is selected. Thereafter, memory cell data is sent from a pair of bit lines to a pair of input/output lines and input to 14 sense amplifiers, as in the conventional example. When one of the wirings 16 through which the output of the sense amplifier is output and goes to a pair of output buffers rises to the "H" level, 18 sense amplifier output detection circuits are activated. As a result, the AND circuit 19 operates and the word line goes to the "L" level, and the memory cell 10 is separated from the bit line 4. When the bit line 4 and the memory cell 10 are disconnected, the precharge signal b on the signal line 20 goes to "L" level, and the transistor 21 charges the bit line to "H" level.

That is, in the present invention, after data is read from a memory cell, the memory cell is disconnected to stop unnecessary discharging of the bit line, and conversely, charging is performed. This does not charge the bit line at the beginning of the next cycle, making access faster than the conventional method by the time required to charge the bit line. Also,
The bit line level at time t1 in Figure ₄ , when the word line becomes "L" level after data reading, is close to the "H" level, which is only slightly lower than the bit line level to which the sense amplifier responded. Therefore, the charging current for charging the bit line by the transistor 21 is significantly reduced compared to the conventional charging from the GND level ("L" level) to the V _CC level ("H" level).

Note that after reading, writing may be performed continuously to the same cell, but in that case, it is necessary to set the word line to "H" level again to select that cell. Therefore, a logic circuit is required to bring the word line to the "H" level again when a write command is applied, but this is omitted from the diagram because it is not directly related to the gist of the present invention.

In the above embodiment, CMOS static RAM
Although the above case has been described, any other process or memory may be used as long as the memory precharges the bit line and reads data, and the same effect as in the above embodiment can be achieved.

As described above, the present invention selects a memory cell provided at the intersection of a word line and a pair of bit lines, writes data to and reads data from the selected memory cell, and writes data read by a sense amplifier. a sense amplifier output detection circuit that detects completion of amplification of read data of the sense amplifier from a change in the output level of the sense amplifier; The present invention is characterized by comprising selection control means for controlling the word line to a non-selected state based on a detection output of the circuit, and charging control means for controlling the bit line to a charged state based on the detection output of the output detection circuit.

Therefore, according to the present invention, there is provided a sense amplifier output detection circuit that detects the completion of the amplification operation of read data from a change in the output level of the sense amplifier, and the detection output of this output detection circuit is used to
selection control means for controlling the word line to a non-selected state;
Since a charge control means is provided to control the bit line to a charged state, after data is read from the memory cell, the word line is set to a non-selected state, thereby separating the memory cell and preventing unnecessary discharge. Moreover, the memory cell is not disconnected while reading data from the memory cell, and by charging the bit line, the time required for charging the next cycle can be significantly shortened, reducing access time. It becomes possible to make the time much shorter than before and perform high-speed access.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional edge sense CMOS RAM circuit, FIG. 2 is a timing diagram for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a timing diagram for explaining the operation of this embodiment. In the figure, 4 is a bit line, 8 is a word line, 1
0 is a memory cell, 14 is a sense amplifier, 18 is a sense amplifier output detection circuit, 19 is an AND circuit (selection control means), 20 is a signal line, and 21 is a transistor (charge control means). In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Select a memory cell provided at the intersection of a word line and a pair of bit lines, write data to and read data from the selected memory cell, and amplify the read data using a sense amplifier. A semiconductor memory device comprising an internally synchronous circuit type static RAM, comprising: a sense amplifier output detection circuit for detecting completion of an amplification operation of read data of the sense amplifier from a change in an output level of the sense amplifier; A semiconductor memory device comprising: selection control means for controlling the word line to a non-selected state based on a detection output; and charging control means for controlling the bit line to a charged state based on a detection output of the output detection circuit. .