JP2557337B2 - Semiconductor memory device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to an output buffer control circuit in a complementary (hereinafter referred to as CMOS) static RAM.

[Prior art]

Conventionally, there has been an example of this type of circuit shown in FIG. In the figure, 1 is a word line control circuit for controlling a word line, 2 is a memory cell, 5 is a Y decoder, 4 is a chip select input terminal, 5 is a chip select control circuit, 6 is an output buffer control circuit, and 7 is A sense amplifier for amplifying the signal from the memory cell 2, 8 is an output buffer circuit for taking out an output signal to the outside, and 9 is an output terminal. In addition, CS is a chip select signal that determines chip selection, WL is a memory cell 2 and a word line that is selected, and BL
Is a bit line connected to the memory cell 2 by the word line WL, I / O is an input / output line, E is an output of the sense amplifier 7, and OE is an output enable signal. Furthermore Q1, Q
Reference numeral 2 is a pull-up transistor that charges the bit line BL and the input / output line I / O, and Q3 is a switch transistor that connects the bit line BL and the input / output line I / O.

Next, the operation of the conventional example will be described with reference to FIG. 2A to 2F are chip select signals.
CS, word line WL, bit line BL and input / output line
I / O, output E of sense amplifier 7, output enable signal OE
3 shows a timing chart of output data.

Now, at time t1, when the chip select input signal changes from the L level to the H level, that is, from the selected state to the non-selected state (see FIG. 2 (a)), the word is selected by the chip select signal CS through the chip select control circuit 5. The line control circuit 1 is cut, and the word line WL becomes L level (see FIG. 2 (b)). As a result, the memory cell 2
Is separated from the bit line BL, the transistor Q1
Both the bit line BL and the input / output line I / O are charged to H level by Q2 (see FIG. 2 (c)). At that time,
The sense amplifier 7 is also cut by the chip select signal CS, and the output E of the sense amplifier 7 is set to H level (see FIG. 2 (d)). Further, the output enable signal OE of the output buffer control circuit 6 becomes H level, which causes the output buffer circuit 8 to be in a non-operating state and the output terminal 9 to be in a floating state (FIG. 2 (e)).
(See (f)).

Then, at time t2, the chip select input signal goes high.
When the level changes from the L level to the L level (see FIG. 2 (a)) and the chip is selected, the word line control circuit 1, the sense amplifier 7 and the output buffer circuit 8 are all put into operation by the chip select signal CS.

By the way, the period Δt shown in FIG. 2 is required until the output buffer circuit 8 outputs the information of the memory cell 2. That is, this is because the word line control circuit 1 operates to select the memory cell 2 and the input / output line I / O from the bit line BL via the Y decoder 3 and the transistor Q3.
Is a period until the information of the memory cell 2 is transmitted to the memory cell 2 and the sense amplifier 7 amplifies the signal and inputs it to the output buffer circuit 8.

However, since the operation start time of the word line control circuit 1 and the operation start time of the output buffer circuit 8 are almost at the same time (see FIGS. 2B and 2E), the information of the memory cell 2 corresponding to the address is The false data D1, which is the output E of the sense amplifier 7 that was set before being output,
It is once output by the output buffer circuit 8.

This means that when the decoder 11 selectively uses a plurality of IC memories 12 and 13 as shown in FIG. 3, the chips 12 and 13 are switched by the chip select signal CS (see FIG. a)), contention between the outputs of the two chips 12 and 13 on the data bus 14 (see FIGS. 4 (b) and (c)), causing a chip reliability problem, or a memory of the memory. May induce noise on the board.

Further, when the false data D1 is output from the output terminal 9 (see FIGS. 5A and 5B), the charging / discharging current of the output load flows, so that noise is generated in the power supply line inside the chip (see FIG. (See FIG. 6C), noise is applied to the operating bit line BL, the input / output line I / O, and the sense amplifier 7 (see FIG. 5D), and the original data of the memory cell 2 is output. It will cause problems.

Therefore, conventionally, as shown in FIG. 6, a delay circuit 15 of an inverter stage is provided in the output buffer control circuit 6 to delay the operation of the output buffer circuit 8.

As a result, the period in the floating state until the chip is selected and the data is output from the output terminal 9 onto the data bus is extended.

However, since the operation of the delay circuit 15 is not synchronized with the time Δt from the operation of the word line control circuit 1 shown in FIG. 2 to the output of the data of the memory cell 2 to the circuit, the two are matched. It is very difficult to adjust the delay circuit 15 so that it does. Therefore, depending on the deviation of the delay time DE (see FIGS. 7 (a) and 7 (b)), the false data D1 is still output as shown in FIG. 7 (c), or as shown in FIG. 7 (d). As described above, there is a drawback that the output of the regular data is delayed.

[Outline of Invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional ones. In a semiconductor memory device in which data in a memory cell is output via a sense amplifier and an output buffer circuit, a chip select A signal and an output enable signal are two inputs, an inverted signal is output when the two inputs match, and an input circuit that becomes floating when they do not match, and the output of the input circuit is used as an input, and the input becomes floating. A flip-flop circuit that keeps the previous state when it becomes, an AND circuit that uses the differential output of the sense amplifier and the output of the flip-flop circuit as three inputs, and a chip selector signal and the output of the AND circuit. A sense amplifier that consists of a NOR circuit that receives the input and an inverter circuit that receives the output of the NOR circuit and that outputs the output enable signal. The output buffer control circuit that drives the output buffer circuit in synchronization with the output buffer circuit is driven by the output buffer control circuit in synchronization with the output of the sense amplifier. An object of the present invention is to provide a semiconductor memory device in which normal data directly appears at an output terminal without sacrificing access from the state.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 shows a semiconductor memory device according to an embodiment of the present invention. The feature of this device is that in the output buffer control circuit 16, the delay circuit portion of the inverter stage shown in FIG. This is the point where it was changed to a logic circuit. That is, in the figure, reference numeral 17 is an input circuit having two inputs of the chip select signal CS and the output enable signal OE, and Q1 and Q2 are P
The channel transistors Q3 and Q4 are N-channel transistors. Reference numeral 18 is a flip-flop circuit for maintaining the previous state when the output A of the input circuit 17 is in a floating state. Reference numeral 19 is an AND having three inputs, the output E of the sense amplifier 7 and the output B of the flip-flop circuit 18. Circuit, 20 is a NOR that has two inputs, the chip select signal CS and the output of the AND circuit 19
Circuit.

Next, the operation will be described with reference to the timing chart of FIG. Here, FIGS. 9A to 9F show chip select signal CS, output A of input circuit 17, output B of flip-flop circuit 18, output E of sense amplifier 7, output enable signal OE, and timing of output data. A chart is shown.

The operation until the chip select signal CS changes from the H level to the L level at the time T1 is exactly the same as that of the conventional example, and the description thereof will be omitted. However, in this case, in the input circuit 17 of FIG. 8, the input CS of the transistors Q3 and Q4
Since both OE are at the H level, both transistors Q3 and Q4 are ON, the output A of the input circuit 17 is at the L level, and the output A and the output of the flip-flop circuit 18 are caused by the action of the flip-flop circuit 18 in the next stage. B is fixed at L level and H level, respectively (see FIGS. 9 (b) and 9 (c)).

At time T1, after the chip select signal CS changes to the L level, the word line control circuit 1 and the sense amplifier 7
Start to operate, but the data of the memory cell 2 has not reached the sense amplifier 7, so the output of the sense amplifier 2 remains at H level (see FIG. 9 (d)). At this time, the transistor Q4 in the input circuit 17 of FIG.
Since it is turned off and the transistor Q2 is turned off, the input circuit
Although the output A of 17 becomes floating, the output A and the output B are latched by the floating circuit 18 in the next stage and are maintained at L level and H level respectively, and the output buffer circuit 8 is still inside the chip. It is in a non-selected state (see FIG. 9 (e)).

Next, when the data of the memory cell 2 is input to the sense amplifier 7 and one of the two outputs E of the sense amplifier 7 becomes L level at the time T2 (see FIG. 9 (d)), it remains at H level until then. The output of the AND circuit 19 which was
The output enable signal OE changes to the L level (see FIG. 9 (e)).

As a result, the output buffer circuit 8 starts to operate, but at this time, since the data of the memory cell 2 has already been input to the output buffer circuit 8 through the sense amplifier 7, the false data is not output and the normal data is in the floating state. It will be output more directly.

In the device of the present embodiment as described above, normal data is directly output from the floating state without outputting false data when the chip select signal changes from the non-selected state to the selected state. There is no problem that normal data output is disturbed or output conflict occurs when multiple IC memories are used.

In the above embodiments, the case of the CMOS static RAM has been described, but other memory cells may be used as long as they have a chip select terminal, and the same effect as that of the above embodiments can be obtained.

〔The invention's effect〕

As described above, according to the present invention, in the semiconductor memory device configured to output the data in the memory cell via the sense amplifier and the output buffer circuit, the chip select signal and the output enable signal are two inputs, The 2
An input circuit that outputs an inverted signal when the inputs match and a floating circuit when the inputs do not match, and a flip-flop circuit that receives the output of the input circuit as an input and maintains the previous state when the input becomes floating And an AND circuit having three inputs of the differential output of the sense amplifier and the output of the flip-flop circuit, the chip selector signal and the A
An output buffer for driving the output buffer circuit in synchronization with the sense amplifier, which is composed of a NOR circuit having two inputs of the output of the ND circuit and an inverter circuit having the output of the NOR circuit as an input and the output of which is an output enable signal. Equipped with a control circuit,
Since the output buffer circuit is driven in synchronization with the sense amplifier, when the chip is selected, only the data corresponding to the address is directly output from the floating state, and a stable operation can be obtained. effective.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit example of a conventional CMOS static RAM, FIG. 2 is a timing chart diagram for explaining the operation of the conventional circuit, and FIGS. 3 to 5 are explanations of defects of the conventional circuit operation. FIG. 3 is a memory block diagram, FIGS. 4 and 5 are timing charts, and FIG.
FIG. 6 is a circuit diagram of a conventional output buffer control circuit, FIG. 7 is a diagram showing a timing chart for explaining the problems of the circuit of FIG. 6, and FIG. 8 is a semiconductor memory according to an embodiment of the present invention. Circuit diagram of the output buffer control circuit in the device,
FIG. 9 is a diagram showing a timing chart for explaining the operation of this embodiment. 2 ... Memory cell, 7 ... Sense amplifier, 8 ... Output buffer circuit, 16 ... Output buffer control circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor memory device configured to output data in a memory cell via a sense amplifier and an output buffer circuit, wherein a chip select signal and an output enable signal are two inputs, and the two inputs match. An input circuit that outputs an inverted signal when it does not match, and becomes floating when they do not match, a flip-flop circuit that receives the output of the input circuit as input, and maintains the previous state when the input becomes floating, and a sense amplifier Of the differential output and the output of the flip-flop circuit as 3 inputs, a NOR circuit having 2 inputs of the chip selector signal and the output of the AND circuit, and the output of the NOR circuit as inputs. An output buffer control circuit that drives the output buffer circuit in synchronization with the sense amplifier, which is composed of an inverter circuit whose output is an output enable signal. The semiconductor memory device characterized by comprising a.