JPS60254488A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To output only data corresponding to an address directly in a floating state when a chip is selected, and to perform stable operation by driving an output buffer circuit in synchronism with a sence amplifier. CONSTITUTION:When data from a memory cell 2 is inputted to the sense amplifier 7 and either of two outputs E of the sense amplifier falls to an L level at time, T, the output of an AND circuit 9 which is at an H level so far falls to the L level and an output-enable signal OE also falls to the L level. Consequently, the output buffer circuit 8 begins to operate, but the data of the memory cell 2 is already inputted to the output buffer circuit 8 through the sence samplifier 7, so no false data is outputted and normal data is outputted directly in the floating state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to an output sofa control circuit in a complementary type (hereinafter referred to as CMO3) static RAM.

[Prior art]

A conventional example of this type of circuit is shown in FIG. In the figure, ■ is a word line control circuit for controlling the word line, 2 is a memory cell, 3 is a Y decoder, 4 is a chip select input terminal, 5 is a chip select control circuit, 6 is an output sofa control circuit, and 7 is a memory cell 2
8 is an output buffer circuit for taking out an output signal to the outside, and 9 is an output terminal. Further, C8 is a chip select signal that determines chip selection, WL is a word line that selects memory cell 2,
BL is a bit line connected to the memory cell 2 by a word line WL, Ilo is an input/output line, E is an output of the sense amplifier 7, and OE is an output enable signal.

Furthermore, Ql and C2 are pull amplifier transistors that charge the pinto line BL and the input/output line I10, and C3 is a switch transistor that connects the bit line BL and the input/output line I10.

Next, the operation of the conventional example will be explained based on FIG. 2.

Here, FIG. 2(a) to (f) show the chip select signal C8.
, the word line WL, the bit line BL, the input/output line 1101, the output E1 of the sense amplifier 7, the output enable signal OE, and the timing chart of the output data.

Now, when the chip select input signal changes from the L level to the F level at time t1, that is, from the selected state to the non-selected state (see FIG. 2 (al)), the chip select signal C8 is activated through the chip select control circuit 5. The word line control circuit 1 is turned off, and the word line WL becomes L level (see FIG. 2). As a result, the memory cell 2 is disconnected from the bit line BL, so the bit line BL and the input/output line I10 are both charged to H level by the transistors Q1 and Q2 (TC in FIG. 2).
reference). At that time, the sense amplifier 7 is also cut by the chip select signal C3, and the output E of the sense amplifier 7 is
is set to H level (see Figure 2 (dl)).

In addition, the output enable signal OE of the output sofa control circuit 6
goes to H level, and as a result, the output buffer circuit 8 becomes inactive, and the output terminal 9 becomes a floating state (see FIG. 2(e) (fl)).

Then, at time t2, the chip select input signal goes high.
When the level changes from the L level to the chip selection state as shown in FIG. 2 (see al), the word line control circuit 1. The sense amplifier 7 and the output sofa circuit 8 all enter the operating state.

By the way, a period Δt shown in FIG. 2 is required until the output sofa circuit 8 outputs the information of the memory cell 2. That is, this means that the word line control circuit 1 operates, the memory cell 2 is selected, and the input/output line I is connected from the bit line BL through the Y decoder 3 and the transistor Q3.
This is the period from when the information of the memory cell 2 is transmitted to the memory cell 10 to when the sense amplifier 7 amplifies the signal and inputs it to the output sofa circuit 8.

However, since the operation start time of the word line control circuit 1 and the operation start time of the output buffer circuit 8 are almost the same (see FIG. 2(b) (el)), the information of the memory cell 2 corresponding to the address is output. False data D1, which is the output E of the sense amplifier 7 that was sent before being sent, is outputted by the negative output basso circuit 8.

As shown in FIG. 3, when a plurality of IC memories 12.13 are selectively used by the decoder 11, when the chips 12.13 are switched by the chip select signal C3 (see FIG. )), the outputs of the two chips 12.13 on the data bus 14 (see Fig. 4(b)
(C)), which may cause chip reliability problems or induce noise on the memory board.

In addition, when the false data D1 is output from the output terminal 9 (see Figure 5 (al Tbl)), the charging and discharging current of the output load flows, so noise is generated in the power supply line inside the chip. ), noise will be added to the operating bit line BL, input/output line I10, and sense amplifier 7 (see FIG. 5(e)), which will interfere with the output of the original data of the memory cell 2. .Furthermore, FIG. 5(C) shows fluctuations in the power supply current Ice.

Therefore, conventionally, as shown in FIG. 6, an inverter-stage delay circuit 15 has been provided in the output buffer control circuit 6 to delay the operation of the output buffer circuit 8.

This means that the floating period from when a chip is selected until data is output from the output terminal 9 onto the data bus becomes longer.

However, since the operation of the delay circuit 15 is not synchronized with the time Δt from the operation of the word line control circuit 1 shown in FIG. It is very difficult to adjust the delay circuit 15 in such a way that the Therefore, the delay time DE
(see Fig. 7 (al~)), Fig. 7 (C
This method has the disadvantage that either false data D1 is output as shown in ), or the output of normal data is delayed as shown in FIG. 7+d).

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described in (A). By driving the output sofa circuit in synchronization with the output of the sense amplifier, after the chip is selected, the floating It is an object of the present invention to provide a semiconductor device in which legitimate data appears directly without sacrificing access from the state.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 8 shows a semiconductor memory device according to an embodiment of the present invention, and the feature of this device is that in the output sofa control circuit 16, the delay circuit portion of the inverter stage shown in FIG. 6 is connected to the output E of the sense amplifier. The difference is that it has been changed to a logic circuit. That is, in the figure, reference numeral 17 denotes an input circuit that generates a chip select signal C3 and an output enable signal OE, and Ql,
Q2 is a P-channel transistor, Q3. Q4 is an N-channel transistor. 18 is a flip-flop circuit for maintaining the previous state when the output A of the input circuit 17 becomes frozen; 19 is the output E of the sense amplifier 7;
and the output B of the flip-flop circuit I8 are operated by three people, and 20 is a NOR circuit that requires two people to generate the chip select signal C8 and the output of the AND circuit engineer 9.

Next, the operation will be explained according to the timing chart of FIG. Here, FIG. 9 (al to (f)) shows the chip select signal C8, the output A of the input circuit 17, the output B of the flip-flop circuit 18, the output E of the sense amplifier 7, the output enable signal E, and the output data. The timing chart is shown below.

The operation until the chip select signal C8 changes from the ■ level to the L level at time TI is completely the same as in the conventional example, so a description thereof will be omitted.

However, in this case, in the input circuit 17 of FIG. 8, since the inputs C8 and OE of the transistors Q3 and Q4 are both at H level, both transistors Q3. Q4 is ON, the output A of the input circuit 17 is at the L level, and the output A and the output B of the flip-flop circuit I8 are fixed at the L level and H level, respectively, by the action of the next-stage flip-flop circuit 18. (Figure 9 (bl (see C1)).

At time T1, after the chip select signal cs changes to level 1, the word line control circuit I and the sense amplifier 7 start operating, but since the data in the memory cell 2 has not yet reached the sense amplifier 7, the sense Amplifier 2
The output remains at H level (see Tdl in FIG. 9).

Also, at this time, in the input circuit 17 of FIG. 8, the transistor Q4 is turned off and the transistor Q2 is turned off, so the output A of the input circuit 17 becomes floating, but the output A is output by the next stage flip-flop circuit 1B.

The output B enters a latched state and is maintained at L level and H level, respectively, and the output cover sofa circuit 8 is still in a non-selected state inside the chip (see tel in FIG. 9).

Next, the data in the memory cell 2 is input to the sense amplifier 7, and at time T2, when one of the two outputs E of the sense amplifier 7 goes to L level (see Figure 9 +dl), it becomes H level until then. The output of the AND circuit 19 changes to L level, and the output enable signal OE becomes L level (see tel in FIG. 9).

As a result, the output cover sofa circuit 8 starts operating, but at this time, since the data in the memory cell 2 has already been input to the output cover sofa circuit 8 through the sense amplifier 7, no false data is output and the normal data is output. It will now be output directly from the floating state.

In the device of this embodiment as described above, when the chip select signal changes from a non-selected state to a selected state, genuine data is directly output from a floating state without outputting false data. Thus, problems such as interference with normal data output or conflicts in output when multiple IC memories are used do not occur.

In the above embodiment, a CMOS static RAM has been described, but other memory cells may be used as long as they have a chip select terminal, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor memory device, the output buffer circuit is driven in synchronization with the sense amplifier, so that when a chip is selected, only the data corresponding to the address is stored in the floating state. This has the effect of providing a device that can operate stably.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a circuit of a conventional CMOS static RAM, Fig. 2 is a timing chart diagram for explaining the operation of the conventional circuit, and Figs. 3 to 5 explain the drawbacks of the conventional circuit operation. In the figure for the 311th! I is a memory block diagram, FIGS. 4 and 5 are timing charts, FIG. 6 is a circuit diagram of a conventional output sofa control circuit, and FIG. 7 is for explaining problems with the circuit in FIG. 6. FIG. 8 is a circuit diagram of an output sofa control circuit in a semiconductor memory device according to an embodiment of the present invention, and FIG. 9 is a timing chart for explaining the operation of this embodiment. be. 2...Memory cell, 7...Sense amplifier, 8...
Output buffer circuit, 16...output buffer sofa control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Procedure cuff (self-motivated) 59109 Showa year, month, day, the Office of the Director General's Palace Yavagina 8 1, Indication of the case Patent application Showa 59 -112492 No. 2, Title of the invention: Semiconductor storage device 3, Person making the amendment Representative: Hitoshi Katayama Section 4, Detailed description of the invention in the agent's specification, and drawings (Figure 5) 6. Contents of the amendment ("Fig. 5 (d)" on page 5, line 11 of the specification is corrected to "Fig. 5 (C).") (2) "Fig. 5 (e)" on page 5, line 13 of the same specification. ” to “5th
Figure (d)” is corrected. (3) Delete "Also, Figure 5 (C1 indicates...") in lines 15-16 of page 5. (4) Delete "Data appears" in line 20 of page 6. " is corrected to "data appears on the output terminal." (5) Fig. 5 is corrected as shown in the attached sheet.

Claims (1)

[Claims] (1) A semiconductor memory device configured to output data in a memory cell via a sense amplifier and an output buffer circuit, including an output buffer control circuit that drives an output buffer circuit in synchronization with the sense amplifier. Characteristic semiconductor memory device.