JP3252544B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
The present invention relates to a control circuit effective for speeding up a write operation in a memory IC such as a DRAM.

[0002]

2. Description of the Related Art Conventional measures for speeding up a write operation will be described. FIG. 5 is a conventional data input / output circuit diagram.
Data input / output line pair (DQ, / D
In the write operation after Q), the MOS transistor switches 101 and 102 are turned on, and the data input line pair (WDB,
/ WDB) is transmitted to the data input / output line pair. If the data appearing on the data input / output line pair is different from the data appearing on the data input line pair from now on, the potential of the data input / output line pair is determined after the MOS transistor switches 101 and 102 are turned on. It takes a long time to perform a high-speed write operation. Therefore, conventionally, in order to cope with an increase in the speed of the write operation, the data input / output line pair is connected to the MOS transistor 1.
By performing the equalization by using 05, the time from when the MOS transistor switches 101 and 102 are turned on to when the write potential of the data input / output line pair is determined is reduced.

Further, in order to improve the layout area efficiency, the ability of a sense amplifier to hold a high level is weaker than the ability to hold a low level. Further, to improve the layout area efficiency, the column switches 2 and 2 ′ for controlling the connection between the data input / output line pair and the sense amplifier are constituted by N-channel MOS transistors 108 and 109.
Therefore, at the time of reading, the MOS transistor 1 does not crush the read data appearing on the bit line pair.
06, 107, the data input / output line pair is clamped to a high level, and when the data input / output line pair is equalized, M
The data input / output line pair is precharged to a high level by the OS transistors 103 and 104. Similarly, at the time of writing, the data input / output line pair is precharged to the high level when the data input / output line pair is equalized.

[0004]

The demand for further speeding up demands a further reduction in the time required for the write operation. When the data input / output line pair is clamped to a high level at the time of writing as in the prior art, the MOS transistor switches 101 and 102 are closed, and even if write data is transmitted to the data input / output line pair, the N channel constituting the column switch is not changed. If the potential on the data input / output line row side does not drop above the threshold voltage Vt of the MOS transistors 108 and 109, the write data appearing on the data input / output line pair does not pass through the column switch. In particular, at the time of low-voltage operation, the ratio of the threshold voltage of the MOS transistor to the power supply voltage increases, and the time from when the MOS transistor switches 101 and 102 are closed to when write data passes through the column switch is delayed. .

[0005] The present invention has been made in view of such problems,
It is an object of the present invention to provide a semiconductor integrated circuit in which a writing operation is further speeded up.

[0006]

According to a first aspect of the present invention, there is provided a data input / output line pair connected to a bit line pair via a sense amplifier, and a precharge circuit for equalizing and clamping the data input / output line pair. a, wherein the provided independently for soup and for writing read power of the precharge circuit, but reading
From the precharge level of the data input / output line pair
The precharge level of the data input / output line pair during writing
The semiconductor integrated circuit is characterized in that the potential of the semiconductor integrated circuit is low .

[0007] The second invention includes a data input and output line pair, a data input line pair, and a switching circuit for controlling the data transfer to the data output line pair from the data input line pair, wherein Set the standby level of the data input line pair to the ground potential
The switch circuit connects the data input line pair and the data input / output line pair before write data is transmitted to the data input line pair, and the data input line pair before the write data is transmitted. The semiconductor integrated circuit is characterized in that the potential of the data input / output line pair is transferred to the data input / output line pair to precharge the data input / output line pair to a low level at the time of writing.

[0008]

In the first invention, the power supply of the precharge circuit is provided independently for reading and writing, and in the second invention, the data is set by setting the potential of the data input line input to the switch circuit. The precharge level of the input / output line pair can be set independently for reading and writing. If the precharge level of the data input / output line pair at the time of writing is set to the ground potential or a sufficiently low potential, the write data appearing on the data input / output line pair immediately passes through the column switch composed of N-channel MOS transistors. , The speed of data transfer to the sense amplifier can be increased.

Further, since the data input / output line pair and the bit line pair are connected via the selected column switch via the sense amplifier, the data input / output line pair is precharged to the ground potential or a sufficiently low potential. Then, the bit line pair is also precharged to the low level. Therefore, the potential difference between the bit line pair before the transfer of the write data is small, and the time from when the write data is transferred to the bit line pair until it is determined can be shortened.

[0010]

Embodiments of the present invention will be described below in detail.

FIG. 1A is a circuit diagram of a data input / output system according to an embodiment of the first invention. In the figure, DQ and / DQ are data input / output line pairs, WDB and / WDB are data input line pairs, and B
L and / BL are bit line pairs, 101 and 102 are switches for connecting a data input line pair and a data input / output line pair,
105 is a MOS transistor forming the precharge circuit 1, 108 and 109 are MOS transistors forming the column switches 2 and 2 ', 201 to 203 are MOS transistors forming the precharge power selection switch 3,
Y is a column switch selection signal, SD is a data input / output line pair selection signal, W1 is a write identification signal, W2 is a data input line pair / data input / output line pair connection control signal, EQ is a precharge circuit control signal, and Vr is a read signal. The time precharge power supply, Vw, is a write precharge power supply.

FIG. 1B is a time chart of each signal shown in the data input / output circuit diagram of FIG. 1A. FIG.
The write operation of the data input / output circuit of FIG. 1A will be described with reference to FIG.

First, the data input line pair selection signal SD transitions to low, and the 1/2 VCC power is cut off from the precharge circuit 1 related to the selected data input / output line pair. Subsequently, W1 transitions to low, the precharge power supply for reading Vr is disconnected from the precharge circuit, and the precharge power supply for writing Vw is connected to the precharge circuit. The precharge circuit 1 precharges and equalizes the data input / output line pair while the EQ is at the low level. At this time, assuming that the precharge power supply for writing Vw is at the ground potential, the data input / output line pair DQ and / DQ are precharged to a low level as shown in FIG. Further, when Y transitions to high while EQ is at low level, the potential of the data input / output line pair is transmitted to the bit line pair, and the potential difference between BL and / BL decreases. W2 rises, and data on the data input line pair starts to be transferred to the data input / output line pair via the MOS transistor switches 101 and 102. Column switch is N channel MO
Since it is composed of S transistors 108 and 109,
The low level has a higher passing speed than the high level, and the write data appearing on the data input / output line pair precharged to the low level operates at a higher speed than the column switch when the data input / output line pair is clamped at the high level. Pass through. Further, as described above, the precharge potential of the data input / output line pair is transmitted to the bit line pair, and the potential difference between BL and / BL is reduced. The time until the pair is determined is also faster than when the data input line pair is clamped at a high level.

FIG. 2A is a circuit diagram of a data input / output system according to an embodiment of the second invention. In the figure, DQ and / DQ are data input / output line pairs, WDB and / WDB are data input line pairs, and B
L and / BL are bit line pairs, 108 and 109 are MOS transistors constituting the column switch 2, Y is a column switch selection signal, SD is a data input / output line pair selection signal, W1
Is a write identification signal, W2 is a data input line pair / data input / output line pair connection control signal, and EQ is a precharge circuit control signal. In addition, the switch circuit
A NAND gate having DB and W2 as input signals;
It is constituted by a clocked inverter controlled by W1 and activated only by the switch circuit selected at the time of writing.

FIG. 2B is a time chart of each signal shown in the data input / output system circuit diagram of FIG. 2A. FIG.
The write operation in the data input / output circuit of FIG. 2A will be described with reference to FIG.

First, SD transitions to low, and a data input / output block to which writing is performed is selected. Subsequently, W1 transitions to low, and the clocked inverter forming the switch circuit is activated. The data input / output line pair precharge circuit selected at the time of writing is SD, W
Not activated by 1. At this time, if W2 has not risen, the output of the NAND gate forming the switch circuit is high, and DQ and / DQ are precharged to the low level which is the output of the clocked inverter.
Furthermore, if the potential of the data input line pair at the time of standby is set to the low level even if the rise of W2 is early, the NAND gate of the switch circuit is not used until the write data is transmitted to the data input line pair. Remains high, and DQ and / DQ are precharged to a low level which is the output of the clocked inverter.

As described above, by adopting a configuration in which the potential of the data input line pair is transmitted to precharge the data input / output line pair, the data input / output line pair can be transferred until the write data starts to be transferred to the data input / output line pair. Precharge the pair. Therefore, a timing margin from prohibiting the pre-charging of the data input / output line pair to connecting the data input / output line pair to the data input / output line pair becomes unnecessary, and the data input / output line pair to the data input / output line pair becomes unnecessary. The data transfer rate is
It is faster than starting data transfer from the data input line pair to the data input / output line pair after prohibiting the precharge of the data input / output line pair.

As described in the first embodiment of the present invention, if the precharge level of the data input / output line pair is set to the low level, the write data passes through the column switch composed of N-channel MOS transistors. The speed is faster than when the data input / output line pair is precharged to a high level.

When the degree of integration of a memory or the like increases, the capacity of the data input / output line pair increases. Further, when a plurality of data input / output line pairs are used as in a multi-bit configuration, the data input / output The current consumption increases due to the charge / discharge current of the line pair. If the data input / output line pair is precharged to 1/2 VCC,
The current consumption for charging / discharging the data input / output line pair is only half that required for precharging the data input / output line pair to VCC or ground potential. When reading, set the data input / output line pair to 1
In order to precharge to / 2VCC, it is necessary to reduce the size of the column switch so that the data does not easily pass so that the read data on the bit line is not crushed by the potential of the data input / output line pair. As described above, in the present invention, the writing speed is faster than in the past, so even if the size of the column switch is reduced and the data is set to be difficult to pass, the writing operation itself can be performed sufficiently, and the power consumption can be reduced. Is also effective.

FIG. 3 is a simulation waveform when the data input / output line pair is precharged to the ground potential according to the second invention of the present application, and FIG. 4 is a diagram showing the data input / output line pair according to the first invention of the present invention reduced to 1/2. It is a simulation waveform at the time of precharge.

The waveform of FIG. 3 will be described with reference to the data input / output circuit diagram of FIG. 2A. When W1 rises, DQ is precharged to a low level, and BL also drops to a low side depending on the level of DQ. You can see that it is doing.
When W2 rises, the potential inversion occurs at DQ and / DQ, and about 1.5 after the potential of DQ and / DQ inverts.
After NS, the potentials of BL and / BL are inverted.

The waveform of FIG. 4 will be described with reference to the data input / output circuit diagram of FIG. 1A.
The precharge of Q and / DQ is released and DQ and / D
The potential difference of Q is increasing. D since W2 started
It can be seen that the potentials are inverted at Q and / DQ, and the potentials of BL and / BL are inverted approximately 3.5 NS after the potentials of DQ and / DQ are inverted.

Comparing FIG. 3 with FIG. 4, the data input / output line pair is precharged to the ground potential during the time from the rise of W2 to the inversion of the potential at DQ and / DQ. It can be seen that the output line pair is about 0.5 NS faster than precharging to 1/2 VCC. Also, D
For the time from when the potentials of Q and / DQ are inverted to when the potentials of BL and / BL are inverted, precharging the data input / output line pair to the ground potential can reduce the data input / output line pair by one.
It can be seen that it is about 2.0 NS faster than precharging to / 2VCC.

[0024]

According to the first aspect of the present invention, the power supply of the precharge circuit is provided independently for reading and writing,
According to the second aspect, by setting the potential of the data input line input to the switch circuit, it is possible to precharge the data input / output line pair to different levels during writing and reading. If the data input / output line pair is precharged to a low level at the time of writing, the speed at which the write data appearing on the data input line pair passes through the column switch composed of the N-channel MOS transistor is set to the high level. It is faster than pre-charging.

Further, since the data input / output line pair and the bit line pair are connected through the selected column switch via the sense amplifier, when the data input / output line pair is precharged to a low level, the bit line pair is also connected. Precharged to low level. Therefore, the potential difference between the bit line pair before the transfer of the write data is small, and the time from when the write data is transferred to the bit line pair until it is determined can be shortened.

If the data input line pair is precharged to a low level at the time of writing, the writing capability is increased, so that the capability of the column switch can be suppressed. Therefore, it is not necessary to precharge the data input / output line pair to a high level at the time of reading. If the data input / output line pair at the time of reading is precharged to 1/2 VCC, the charge / discharge current associated with the data input / output line pair is minimized.

[Brief description of the drawings]

FIG. 1A is a configuration diagram centering on a data input / output system of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 1B is a block diagram of each signal shown in the data input / output system circuit diagram of FIG. Time chart

FIG. 2A is a configuration diagram centering on a data input / output system of a semiconductor integrated circuit according to a second embodiment of the present invention; FIG. 2B is a diagram of each signal shown in the data input / output system circuit diagram of FIG. 2A; ,Time chart

FIG. 3 is a diagram showing a simulation result of a data input system at the time of writing in the semiconductor integrated circuit according to the second embodiment of the present invention;

FIG. 4 is a diagram showing a simulation result of a data input system at the time of writing in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 5 is a configuration diagram focusing on a data input / output system of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 Precharge circuit 2 Column switch 3 Precharge power select switch 4 Switch circuit 5 Clocked inverter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-61688 (JP, A) JP-A-5-47187 (JP, A) JP-A-4-349296 (JP, A) JP-A-1- 19588 (JP, A) JP-A-63-222189 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/409

Claims (3)

(57) [Claims] 1. A data input / output line pair connected to a bit line pair via a sense amplifier, and a precharge circuit for equalizing and clamping the data input / output line pair,
The power supply of the precharge circuit is provided independently for reading and writing, and the precharge level of the data input / output line pair at the time of writing is set to a lower potential than the precharge level of the data input / output line pair at the time of reading. A semiconductor integrated circuit characterized in that: 2. A bit line pair selected via a sense amplifier by setting a power supply voltage for writing of the precharge circuit to a ground voltage and precharging to a ground potential of the data input / output line pair at the time of writing. 2. The semiconductor integrated circuit according to claim 1, wherein the circuit is precharged to a low level. 3. A data input / output line pair, a data input line pair,
And a switching circuit for controlling the data transfer to the data output line pair from the data input line pair, the data
The standby level of the input line pair is set to the ground potential, and before the write data is transmitted to the data input line pair, the switch circuit connects the data input line pair to the data input / output line pair to transmit the write data. By transferring the potential of the data input / output line pair before writing to the data input / output line pair , the data input / output line pair at the time of writing is low.
A semiconductor integrated circuit characterized in that a level is precharged.