JP2572607B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for precharging a semiconductor memory device.

[Conventional technology]

The prior art of the static semiconductor memory device is as shown in FIG. The output 3 of the decoder circuit 2 selects a word line (W ₀ , W _1, ...) And a column gate (Y ₀ , Y ₁ ,...) According to the address input Ai.

The read operation is performed when the write signal ▲ ▼ is at the H level.
When a logical change of Ai occurs, an address transition detection circuit (ATD circuit) 4 operates, and equalizing pulses φ ₁ and φ ₂ are generated from a pulse generation circuit 5 to generate bit lines (B ₀ ▲, B ₁・).
▲,...) And the data line (D ·) are equalized. Then, data of the memory cell MC on the selected word line appears on the bit line, and data of the memory cell connected to the selected column gate appears on the data line.

Writing is performed by setting ▲ to the L level and supplying a complementary voltage from the writing circuit 6 to the data line D. Done.

Next, a case where writing is performed at the timing shown in FIG. 6 will be described. Here, Y ₀ is selected as the column gate and T ₁
In reading of the memory cells of word line W _0, write D _in = H level in the memory cell of the W ₁ at T _2, and performs reading of W ₀ at T ₃ again. In the figure ▲ ▼ falling referred to as the address set-up time t _AS the time difference between the change of the required ▲ ▼ and Ai to not write to the memory cell which has been selected by T ₁ against the, ▲ ▼ of to the memory cell selected by T ₃ with respect to the rise required for programming is not performed ▲
The time difference between the change of ▼ and Ai is called the write recovery time t _WR . Generally, OnS is a standard value for both t _AS and t _WR .

Address Setup is determined by falling a and W _g appear data complementary to the rising bit line timing b of the word lines W _0, through an inverter 10 and 11 in the circuit of Figure 5
The t _AS is secured by delaying the rise of Wg.

▲ ▼
Rise in Wg promptly fall of the bit lines has become the writing period to the L level ▲ ▼ and the data line is charged through the load transistor Q ₂ and Q _12. Address input Ai
Q ₅ and Q at equalizing pulse phi ₁ and phi ₂ generated by the change in
₁₃ turns on, and the bit line and the data line are equalized.
At this time, the charges of the bit line B ₀ and the data line D at the H level are temporarily discharged, but are charged again at Q ₁ and Q ₁₁ . To avoid writing to the memory cell selected by T ₃ bit lines B ₀ · ▲ ▼ equalizing and precharging of before word line W ₀ rises there is a need to be sufficiently performed. Normally, writing of a memory cell is performed by discharging the charge of the cell. Therefore, even if the bit line is equalized, the memory cell falls into an unstable state if it is in a discharged state. Accordingly, the write recovery time of this circuit is limited by the timing of the point C where the bit line is sufficiently precharged and the rising edge d of the word line.

[Problems to be solved by the invention]

Since the conventional static semiconductor memory device is configured as described above, it takes time to precharge the bit line, and it is difficult to speed up the rise of the word line in order to secure the write recovery time. Was. If the performance of the load transistors on the bit line and the data line is increased, the time required for precharging is shortened, but the difference in performance between the memory cell and the memory cell is increased, and the signal voltage difference between the read and the memory cell is reduced.

The present invention has been made to solve the above problems, and has as its object to provide a static semiconductor memory device capable of high-speed operation without increasing the write recovery time.

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair, and data to the memory cell via the data line pair. A write circuit for outputting a complementary signal to be written, wherein the write circuit outputs the complementary signal to the data line during a write operation, and after the write operation, the data line pair and the bit. A precharge voltage for precharging a line pair is output to the data line pair, and the output of the complementary signal and the precharge voltage to the data line pair is prohibited during a read operation. .

Further, the bit line pair is connected to bit line current supply means having a smaller current supply capability than the write circuit.

Further, a data line current supply means having a smaller current supply capability than the write circuit is connected to the data line.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a static semiconductor memory device according to one embodiment of the present invention. Since the H level supplied from the write circuit 6 to the data line D • passes through Q ₁₄ and Q ₁₅ , the power supply voltage V
_{It is} lower than _dd by the threshold voltage V _{TH of the} transistor, and is equal to the precharge voltage of the bit line and the data line. Therefore, by simultaneously supplying the H level to the pair of data lines D., it is possible to put the bit lines and the data lines in a precharged state.

Write circuit 6 is an inverter when ▲ ▼ is at L level.
The output of 13 is at the H level, and the NAND circuits 8 and 9 output complementary data. When ▼ is at the H level, the outputs 8 and 9 are at the H level, but since W ₉ is at the L level, Q ₁₄ and Q ₁₅ are off and no voltage is supplied to the data lines. However, ▲
When ▼ rises, the output of 8 and ₉ becomes H level immediately and W ₉
Rises through the delay circuits 10, 11, and 12, and during this period, the H level is supplied to the data line to perform precharge.

Next, the operation of address setup and write recovery will be described with reference to FIG. Since W ₉ is rises delayed from the falling edge of the WE when moving to the write period, which conventional word line W ₀ which has been selected by T ₁ during which it is possible to prevent writing to the memory cell if Kudare standing This is the same principle as the method. T ₂ In the W ₉ is the data line at the H level data is written into the memory cell complementary signal is selected is supplied. At the end of writing, a charge voltage is supplied from the writing circuit to the data line immediately after the rise of ▼, and the bit line ▼ and the data line which have been at the L level are charged. The current supply capability of the write circuit is stronger than the bit line load and the data line load, and rapid charging is possible. Therefore, the bit line is precharged sufficiently at C and the rise of the word line must be accelerated to d. Is possible.

FIG. 3 shows another embodiment of the present invention. In this embodiment, when the address changes, ATD is performed before the word line changes.
Utilizing the pulse occurs, is performed precharge from the write circuit 6 introduces a signal phi ₃ from the pulse generator 5. The phi ₃ is a pulse which becomes H level when the address change, the output of the time the NOR circuit 13 is the output of the NAND circuit 8,9 to become L level precharge become both H levels is performed.

FIG. 4 is a timing chart of this embodiment. φ ₃ is H
Address Setup Since data is kept in the bit line B ₀ · ▲ ▼ precharging performed in the memory cell when the level change of address as the write recovery will be extend by the amount of phi ₃ diagram It is possible to greatly enter the writing period.

〔The invention's effect〕

As described above, in the present invention, precharging is performed from the write circuit, and during the read period, output from the write circuit to the data line pair is prohibited, so that the read operation is not affected by noise. This has the effect that the precharge time after the write operation can be shortened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a static type semiconductor memory device showing one embodiment of the present invention, FIG. 2 is a timing chart of address setup and write recovery thereof, and FIG. 3 is a static type memory showing another embodiment of the present invention. FIG. 4 is a circuit diagram of a semiconductor memory device, FIG. 4 is a timing diagram of the address setup and write recovery, FIG. 5 is a circuit diagram of a conventional static semiconductor memory device, and FIG. 6 is a timing diagram of the address setup and write recovery. is there. In the circuit diagram, a portion 6 surrounded by a broken line indicates a write circuit.

Claims (3)

(57) [Claims] 1. A memory cell; a bit line pair connected to the memory cell; a data line pair connected to the bit line pair; and a complementary element for writing data to the memory cell via the data line pair. A write circuit that outputs a signal, the write circuit outputs the complementary signal to the data line during a write operation, and the data line pair and the bit line pair are output after the write operation. A semiconductor memory device, wherein a precharge voltage to be precharged is output to the data line pair, and the output of the complementary signal and the precharge voltage to the data line pair is prohibited during a read operation. . 2. The semiconductor memory device according to claim 1, wherein bit line current supply means having a smaller current supply capability than said write circuit is connected to said bit line pair. 3. The semiconductor memory device according to claim 1, wherein said data line pair is connected to data line current supply means having a smaller current supply capability than said write circuit.