JP2563893B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
Related to the write circuit.
is there.

[0002]

2. Description of the Related Art The prior art of a static type semiconductor memory device is as shown in FIG. The output 3 of the decoder circuit 2 receives the word line (W ₀ , W ₀ ,
W _1, ...), a column gate _{(Y 0, Y 1, ...} ) selected.

In the read operation, when the write signal WE is at H level and a logical change of Ai occurs, the address shift detection circuit (ATD circuit) 4 operates and the pulse generation circuit 5 equalizes the pulse φ1. , Φ2 , And the bit line (B ₀
・ B ₀ ￣, B ₁・ B ₁ ￣, ...) and data line (D ・ D ￣)
Is equalized. Then, the data of the memory cell MC on the selected word line appears on the bit line, and the data of the memory cell connected to the selected column gate appears on the data line.

For writing, WE is set to L level, a complementary voltage is supplied from the write circuit 6 to the data lines D and D, and the flip-flop of the memory cell is set to the state of write data through the selected column gate and word line. It is done by

Next, a case where writing is performed at the timing shown in FIG. 6 will be described. Here, Y ₀ is selected as the column gate, and at T ₁ , the memory cell of the word line W ₀ is read, T ₀
2 At W1 Write Din = H level to the memory cell of At W0 Shall be read. T1 for the fall of WE in the figure The time difference between the changes in WE and Ai required for not writing to the memory cell selected in step S is called address setup time tAS, which is T3 for the rising edge of WE. The time difference between the changes in WE and Ai necessary for not writing to the memory cell selected by is called the write recovery time tWR. Generally, both tAS and tWR are On
S is the standard value.

Address setup is performed by word line W0 Fall a and Wg Is determined by the timing b at which complementary data appears on the rising rebit line, but in the circuit of FIG.
By delaying the rise of W _g through 0, 11 t
AS is secured.

Further, at the write recovery timing, W _g rapidly falls at the rising edge of WE and the bit line B0 which has been at the L level during the writing period. ￣ and data line D￣
Is charged through the load transistors Q ₂ and Q ₁₂ . Equalize pulse φ ₁ generated by change of address input Ai
And φ ₂ , Q ₅ and Q ₁₃ are turned on to equalize the bit line and the data line. At this time, the charges on the H level bit line B ₀ and the data line D are temporarily discharged, but are again charged on Q ₁ and Q ₁₁ . In order to prevent writing to the memory cell selected by T ₃ , bit line B before word line W ₀ rises.
It is necessary that the equalization and precharge of ₀ · B ₀ are sufficiently performed. Normally, writing to a memory cell is performed by discharging the electric charge of the cell, so even if the bit line is equalized, the memory cell will fall into an unstable state in the discharged state. Therefore, the write recovery time of this circuit is limited by the point C where the bit line precharge is sufficient and the timing d at the rising edge d of the word line.

[0008]

Since the conventional static semiconductor memory device is configured as described above, it takes time to precharge the bit line, and the rise of the word line is accelerated in order to secure the write recovery time. It was difficult to achieve high speed. If the load transistors of the bit line and the data line are used, the time required for precharging will be short, but the difference in the capacity with the memory cell will be large, and the difference in the read signal voltage will be small, making them susceptible to noise.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a static semiconductor memory device capable of high-speed operation without increasing the write recovery time.

[0010]

Means for Solving the Problems] The semiconductor memory device of the present invention includes a memory cell, a bit line pair connected to the memory cell, a data line pair connected to said bit line pair, control
In a semiconductor memory device having a write circuit that outputs a complementary signal for writing data to the memory cell via the data line pair based on a control signal , the write circuit delays the control signal and delays the control signal. Delay times to output
And a control signal input to the write circuit is in the first state, the complementary signal can be output to the data line pair , the control signal is in the second state and the delay signal is present.
When No. is in the first state, is capable of outputting a precharge voltage for precharging said data line pair and the bit line pair to the data line pair, wherein the delay signal is in said second state In this case, output from the write circuit to the data line pair is prohibited. Furthermore ,
Detects a change in the address signal designating the memory cell
And an address transition detection circuit,
Based on the output from the address transition detection circuit,
Precharger for precharging the data line pair and the data line pair
And a charge voltage is output to the data line.

(2) The write circuit of the above (1) supplies complementary signals to the pair of data lines during the write period, supplies a read precharge voltage to the pair of data lines for a certain period after the end of the write, and then outputs the data. It is characterized in that the voltage supply to the line is stopped.

(3) The write circuits of the above (l) and (2) receive the palace signal of the address transition detection circuit and supply the read precharge voltage to the pair of data lines for a certain period when the address signal changes in logic. It is characterized by

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a static type semiconductor memory device according to one embodiment of the present invention. Data line D from the writing circuit 6
Since the H level supplied to D− passes through Q ₁₄ and Q ₁₅ , it is lower than the power supply voltage V _{dd by} the threshold voltage V _{TH of the} retransistor and equal to the precharge voltage of the bit line and the data line. Therefore, by supplying the H level to the pair of data lines D and D at the same time, the bit line and the data line can be precharged.

In the write circuit 6, when WE is at L level, the output of the inverter 13 is at H level, and the NAND circuits 8 and 9 output complementary data. When WE is at H level, the outputs of 8 and 9 are at H level, but since W _g is at L level, Q ₁₄ and Q ₁₅ are off and no voltage is supplied to the data line. However, when WE_ rises, the outputs of 8 and 9 immediately become H level, and W _g rises through the delay circuits l0, l1 and l2, so during this period the H level is supplied to the data line and precharge is performed. Be seen.

Next, according to FIG. 2, address setup,
The operation of write recovery will be described. Since W _g rises with a delay from the fall of WE at the time of shifting to the writing period, during this period, T
_If the word line W ₀ selected by ₁ falls, writing to the memory cell can be prevented. This is the same principle as the conventional method. At T ₂ , W ₉ is at H level and a complementary signal is supplied to the data line to write data to the selected memory cell. At the end of writing, a charge voltage is supplied to the re-data line from the writing circuit immediately after the rise of WE- to charge the bit line B _0- and the data line D-at the L level. The current supply capacity of the write circuit is stronger than that of the bit line load and data line load, and since rapid charging is possible, the bit line is precharged sufficiently with C, and the rise of the reward line is accelerated to d. Is possible.

FIG. 3 shows another embodiment of the present invention.
In this embodiment, when the address is changed, the ATD pulse is generated prior to the change of the word line, and the signal φ ₃ is introduced from the pulse generation circuit 5 to re-charge the write circuit 6. φ ₃ is a pulse that goes to H level when the address changes, and at this time, the output of the NOR circuit 13 goes to L level, so that both outputs of the NAMD circuits 8 and 9 go to H level and precharge is performed. .

FIG. 4 is a timing diagram of this embodiment.
When φ ₃ is at H level, the bit line B ₀ · B ₀ ￣ is precharged and the data in the memory cell is retained, so address setup and write recovery are extended by φ ₃ . It is possible that a change in address significantly enters into the writing period.

[0019]

As described above, according to the present invention, the writing
It becomes possible to perform precharge from the embedded circuit. Ma
Also, by having a delay circuit, the first state and the second
By changing the state of the control signal that has the state, write operation can be performed.
Output to the data line pair from the write, precharge, and write circuits.
It is possible to control the three actions of prohibiting force.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a static semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a timing diagram of the address setup and write recovery.

FIG. 3 is a circuit diagram of a static semiconductor memory device showing another embodiment of the present invention.

FIG. 4 is a timing chart of the address setup and write recovery.

FIG. 5 is a circuit diagram of a conventional static semiconductor memory device.

FIG. 6 is a timing chart of the address setup and write recovery. In the circuit diagram, a portion 6 surrounded by a broken line indicates a write circuit.

[Explanation of symbols]

 1 ... Address input circuit 2 ... Decoder circuit 4 ... ATD circuit 6 ... Write circuit

Claims (2)

(57) [Claims] 1. A memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair, and a memory cell to the memory cell via the data line pair based on a control signal. In a semiconductor memory device having a write circuit that outputs a complementary signal for writing data, the write circuit delays the control signal and outputs a delayed signal.
When the control signal input to the write circuit is in the first state, the complementary signal can be output to the data line pair , and the control signal is in the second state. when the delay signal is in the first state, the precharge voltage to precharge the data line pair and the bit line pairs is capable of outputting to the data line pair, wherein the delay signal is the second In the state, the semiconductor memory device is characterized in that output from the write circuit to the data line pair is prohibited. 2. An address signal for designating the memory cell
The write circuit has an address transition detection circuit for detecting a change, and the write circuit outputs from the address transition detection circuit.
The bit line pair and the data line pair based on the force.
Output the precharge voltage to be charged to the data line.
The semiconductor memory device according to claim 1, wherein: