JPH0541085A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by conducting only one side of a pair of a bit line at the time of writing a signal amplified with a sense amplifier o a memory cell. CONSTITUTION:A word line W0 is made a high level and information in the memory cell is read to the bit line. Since transfer gate control signals TG00, TG01 are the high level, the signal read to the bit line is transmitted to the input nodal points SA0, SA1, as well. At this time, the control signals TG00, TG01 are lowered and the signals read to the nodal points SAO, SA1 are amplified by the sense amplifier SA. Thereafter, when only the control signal TG00 is the high level, the signal amplified by the sense amplifier is sent to only the bit line B0 and written to the memory cell. Thus, since the signal amplified by the sense amplifier is not transmitted to the bit line not connected to the memory cell, no useless charge/discharge current flows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit in a dynamic memory (DRAM).

[0002]

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional sense amplifier circuit, and FIG. 4 shows a timing chart. In FIG.
SA is a sense amplifier, SAE is a sense amplifier operation control signal, SA0 and SA1 are nodes, TG0 is a transfer gate control signal, B0 and B1 are bit lines, W0 is a word line, and HVCD is a power supply voltage (Vcc) / 2 pre. Charge voltage, P is a bit line precharge control signal, T0, T1,
T2, T3, T4 and T5 are nMOSFETs, and C is a memory cell capacitor.

The operation of this circuit will be described with reference to the timing chart of FIG. First, the bit line precharge control signal P is set to a high level to set the bit line to Vcc /
After precharging to 2, the word line W0 is set to high level and the information in the memory cell is read to the bit line. And
After the control signal TG0 of the transfer gate is set to low level, the voltage of SA0 and SA1 is amplified by the sense amplifier by the operation control signal SAE of the sense amplifier.

After that, the transfer gate control signal T
G0 is set to the high level again, the signal amplified by the sense amplifier SA is written back to the bit lines B0 and B1, and the information is written in the memory cell.

[0005]

In this prior art, when writing information to the memory cell, the control signal TG0 of the transfer gate is set to the high level to bring both the bit lines B0 and B1 into conduction, so that the memory cell is The signal amplified by the sense amplifier is transmitted to the bit lines that are not connected, and the charging / discharging current flows through both bit lines. Therefore, there is a problem that wasteful power is consumed.

The present invention is to solve the above-mentioned problems, and an object thereof is to provide a sense amplifier circuit for reducing power consumption when writing a signal amplified by a sense amplifier to a memory cell. It is to be.

[0007]

According to the sense amplifier circuit of the present invention, a drain is connected to one of a pair of bit lines, a first transistor connecting a source to the sense amplifier and a drain to the other bit line, and a source to the sense amplifier. In a sense amplifier circuit having a second transistor for connecting to, a means for writing information in the memory cell by writing only one of the first transistor and the second transistor during writing is provided.

[0008]

According to the present invention, by implementing the above means, when writing the signal amplified by the sense amplifier to the memory cell, only one of the pair of bit lines is made conductive and the power consumption is reduced. Can be made smaller.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sense amplifier circuit of the present invention, and FIG. 2 is a timing chart. 1 is different from the example of the conventional circuit shown in FIG. 3 in that the transfer gate control signal is divided into TG00 and TG01, and the other components are exactly the same, and are therefore denoted by the same symbols. ..

The circuit operation of the present invention will be described with reference to the timing chart of FIG. First, the bit line precharge control signal P is set to a high level to set the bit line to Vcc / 2.
Then, the word line W0 is set to the high level and the information in the memory cell is read to the bit line. Since the transfer gate control signals TG00 and TG01 are at high level, the signal read to the bit line is also transmitted to the input nodes SA0 and SA1 of the sense amplifier section. Here, the control signals TG00 and TG01 of the transfer gate are lowered, and then the signals read to the nodes SA0 and SA1 are amplified by the sense amplifier SA.

After this, the transfer gate control signal T
When only G00 is set to the high level, the signal amplified by the sense amplifier is sent only to the bit line B0 and is written in the memory cell again. Therefore, since the signal amplified by the sense amplifier is not transmitted to the bit line to which the memory cell is not connected, useless charging / discharging current does not flow. for that reason,
Power consumption can be reduced.

[0012]

As described above, according to the present invention, power consumption can be reduced when writing a signal amplified by a sense amplifier into a memory cell.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sense amplifier circuit of the present invention.

FIG. 2 is a waveform diagram in the circuit of the present invention.

FIG. 3 is a circuit diagram of a conventional sense amplifier circuit.

FIG. 4 is a waveform diagram of a conventional circuit.

[Explanation of symbols]

T0, T1, T2, T3, T4, T5 nMOSFE
T SA Sense amplifier SA0, SA1 Node SAE Sense amplifier control signal W0 Word line TG0, TG00, TG01 Transfer gate control signal B0, B1 Bit line HVCD Power supply voltage (Vcc) / 2 Precharge voltage P Bit line precharge control signal C Memory Cell capacitor

Claims (1)

[Claims] 1. A first transistor having a source / drain path connected between one bit line of a bit line pair and a first input / output terminal of a sense amplifier, and the other bit line and a second bit line of the sense amplifier. A sense amplifier circuit comprising: a second transistor having a source / drain path connected between the input and output terminals; and means for controlling conduction of the first transistor and the second transistor with different control signals. ..