JP2002208276A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory device in which current consumption for charging and discharging for a plurality of pairs of first and second bit lines at the time of sensing operation can be reduced. SOLUTION: First and second bit lines of each pair are divided into parts BL-m, BLB-m to which respective memory cells MC (0), MC (1),..., MC(2n+1) are connected and parts BL-SA, BLB-SA to which respective amplifiers SA are connected and gate means Q1, Q2 connecting and separating respectively two parts of bit lines of each pair are provided. The gate means Q1, Q2 are controlled so that the gate means Q1 (or gate means Q2) is turned on and the gate means Q2 (or gate means Q1) is turned off during sensing operation when a bit line to which an accessed memory cell out of a plurality of memory cells is connected is a first bit line BL (or a second bit line BLB).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a memory device.

[0002]

2. Description of the Related Art A conventional D (dynamic) RAM memory device will be described with reference to FIG. This memory device has a plurality of word lines WL (0), WL
(1), WL (2), ‥‥‥, WL (2n), WL (2
n + 1) and a plurality of pairs of first and second bit lines ‥‥‥,
BL- (m-1); BLB- (m-1), BL-m; B
LB-m, BL- (m + 1); BLB- (m + 1), ‥
} And a plurality of word lines WL (0), WL (1), WL
(2), ‥‥‥, WL (2n), WL (2n + 1) and a plurality of pairs of first and second bit lines ‥‥‥, BL− (m−
1); BLB- (m-1), BL-m; BLB-m, B
L- (m + 1); BLB- (m + 1), the memory cells MC respectively connected to the intersections of the alternate bit lines
(0), MC (1), ‥‥‥, MC (2n), MC (2
n + 1).

[0003] Memory cells MC (0), MC (1),
‥, MC (2n), MC (2n + 1) are each formed of a series circuit of a switching transistor (MOS-FET) Q and a capacitor C, and the drain of the MOS-FET Q is a plurality of pairs of first and second bits. line‥‥‥,
BL- (m-1); BLB- (m-1), BL-m; B
LB-m, BL- (m + 1); BLB- (m + 1), ‥
, And the gate of the MOS-FET Q is connected to a plurality of word lines WL (0), WL (1), WL
(2), ‥‥‥, WL (2n), WL (2n + 1). The capacitor C side of the series circuit is connected to a cell plate potential line (not shown).

A plurality of pairs of first and second bit lines {
‥, BL- (m-1); BLB- (m-1), BL-
m; BLB-m, BL- (m + 1); BLB- (m +
1) and ‥‥‥, the sense amplifier SA and each memory cell MC (0), MC (1), ＭＣ, MC (2
n), after completion of reading and writing in MC (2n + 1), a plurality of pairs of first and second bit lines ‥‥‥, BL-
(M-1); BLB- (m-1), BL-m; BLB-
An equalizing circuit EQ for making the potential between m, BL- (m + 1); BLB- (m + 1), ‥‥‥ the same is connected.

The sense amplifier SA is controlled by a sensing operation signal SA-On.
It is controlled by the bit line reset signal Eq-On.

The operation of the memory device shown in FIG. 3 will be described below.
This will be described with reference to a timing chart showing signal waveforms in FIG. When the bit line reset signal Eq-On is L
For example, when the voltage of the word line WL (0) rises from L to H (high) during (low) (released state), the MOS-FET Q of the memory cell MC (0)
Is turned ON, the electric charge of the capacitor C flows to the bit line BL, and a very small voltage is generated between the bit lines BL and BLB. Thereafter, the sensing operation signal SA-On changes from L to H.
, The sense amplifier SA starts to amplify the very small voltage, latches it to the maximum amplitude, and sets the bit lines BL-m, BLB-
The voltage of m reaches Vcc (V) and 0 (V), respectively. At this time, a large current flows through the sense amplifier SA to charge and discharge the bit lines BL and BLB. afterwards,
A read / write operation is performed on a read / write (R / W) circuit. Thereafter, the voltage of the word line WL0 changes from H to L, and thereafter, the sensing operation signal SA-On changes from H to L. After that, the bit line reset signal E
When q-On changes from L to H (bit line reset state), the equalizing circuit EQ operates and the bit line B
So that the voltages of L and BLB are both equal to Vcc / 2,
After the bit lines BL and BLB are precharged, a standby state is set.

[0007]

In such a conventional memory device, a plurality of pairs of first and second bit lines and a plurality of word lines crossing each other and a plurality of pairs of first and second bit lines are alternately arranged. A memory cell respectively connected to each one bit line and each crossing portion of the plurality of word lines;
And a sense amplifier connected between the second bit lines, respectively, wherein only the bit line to which the accessed memory cell of the plurality of pairs of the first and second bit lines is connected during the sensing operation Also, the bit line to which the accessed memory cell is not connected also
In both cases, charging and discharging are performed until the respective voltages reach the latch voltages having the respective maximum amplitudes, so that the current consumption becomes excessively large.

In view of the foregoing, the present invention provides a plurality of pairs of first and second bit lines and a plurality of word lines which cross each other, and a plurality of pairs of first and second bit lines which alternate with each other. In a memory device having a memory cell connected to each intersection of a bit line and a plurality of word lines, and a sense amplifier connected between each pair of first and second bit lines, a memory device having a An object of the present invention is to propose a memory device capable of reducing current consumption for charging and discharging a plurality of pairs of first and second bit lines.

[0009]

According to a first aspect of the present invention, a plurality of pairs of first and second bit lines and a plurality of word lines crossing each other, and a plurality of pairs of first and second bit lines are alternately provided. In a memory device having a memory cell connected to each one bit line and each crossing portion of a plurality of word lines, and a sense amplifier connected between each pair of first and second bit lines, The pair of first and second bit lines are divided into a portion to which each memory cell is connected and a portion to which each sense amplifier is connected, and the two portions of each pair of bit lines are connected to each other. And first and second gate means for separating the memory cells, and the bit line to which the accessed memory cell of the plurality of memory cells is connected is the first
When the sensing operation is performed, the first
The second gate means is turned on, the second gate means is turned off, and if it is the second bit line, the second gate means is turned on and the first gate means is turned off during the sensing operation. A memory device for controlling a plurality of first and second gate means.

According to the first aspect, when the bit line to which the accessed memory cell of the plurality of memory cells is the first bit line, the first bit line is connected during the sensing operation. The second gate means is turned on, the second gate means is turned off, and if it is the second bit line, the second gate means is turned on and the first gate means is turned off during the sensing operation.

According to a second aspect, in the memory device according to the first aspect, during the precharge period for each pair of the first and second bit lines, each of the first and second gate means is set to O.
N is the memory device.

In the memory device according to the first and second aspects, the memory cell is a D-RAM memory cell.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a memory device (D-RAM memory device) according to an embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals. This memory device includes a plurality of word lines WL (0), WL (1), W
L (2), ‥‥‥, WL (2n), WL (2n + 1) and a plurality of pairs of first and second bit lines ‥‥‥, BL- (m
-1); BLB- (m-1), BL-m; BLB-m,
BL- (m + 1); BLB- (m + 1), ‥‥‥, and a plurality of word lines WL (0), WL (1), WL (2), ‥
‥‥, WL (2n), WL (2n + 1) and a plurality of pairs of first and second bit lines ‥‥‥, BL- (m−1); BL
B- (m-1), BL-m; BLB-m, BL- (m +
1); memory cells (D-RAM memory cells) MC (0), MC (1),..., MC () connected to the intersections of the alternate bit lines BLB- (m + 1), 2
n) and MC (2n + 1).

Memory cells MC (0), MC (1),.
‥, MC (2n), MC (2n + 1) are each formed of a series circuit of a switching transistor (MOS-FET) Q and a capacitor C, and the drain of the MOS-FET Q is a plurality of pairs of first and second bits. line‥‥‥,
BL- (m-1); BLB- (m-1), BL-m; B
LB-m, BL- (m + 1); BLB- (m + 1), ‥
, And the gate of the MOS-FET Q is connected to a plurality of word lines WL (0), WL (1), WL
(2), ‥‥‥, WL (2n), WL (2n + 1). The capacitor C side of the series circuit is connected to a cell plate potential line (not shown).

In FIG. 1, a sense amplifier SA and memory cells MC (0), MC (1),..., MC (2n), M
MOS-FETs Q1 and Q2 as first and second gates for connecting and separating between C (2n + 1)
A plurality of pairs of first and second bit lines ‥‥‥, BL- (m-
1); BLB- (m-1), BL-m; BLB-m, B
L- (m + 1); BLB- (m + 1), respectively. In FIG. 1, for convenience, MOS-FET Q
1, the bit line on the left side of Q2 is denoted by BL-SA,
The symbol of BLB-SA is assigned. Therefore, a plurality of pairs of first and second bit lines ‥‥‥, BL- (m-1); BLB-
(M-1), BL-m; BLB-m, BL- (m +
1); BLB- (m + 1), ‥‥‥ are MOS
-Connected to the first and second bit lines BL-SA, BLB-SA via FETs Q1, Q2.

The MOS-FETs Q1 and Q2 are collectively referred to as an isolation gate DG. MOS-FET Q1, Q2
Are turned on and off by respective gate signals Cut-BL and Cut-BLB. In this example, MOS-
N-channel type MOS-F as FETs Q1 and Q2
Since ET is used, the gate signals Cut-BL, C
When ut-BLB is H, the MOS-FETs Q1, Q2
Is ON, and when L, it is OFF. MOS-FE
P-channel type MOS-FET as T Q1 and Q2
May be used, in which case the gate signal Cut-
H and L of BL and Cut-BLB and MOS-FET Q
1, the relationship between Q2 ON and OFF is N channel type M
The reverse is the case when the OS-FET is used.

Incidentally, N- and P-channel type MOS-FETs
Can also be used in combination. In that case, gate signals to be supplied to the gates of the N- and P-channel type MOS-FETs need to be generated separately according to the N-type and P-channel type.

Then, for example, a plurality of pairs of first and second bit lines ‥‥‥, BL- (m-1); BLB- (m-
1), BL-m; BLB-m, BL- (m + 1); BL
B− (m + 1), ‥‥‥, each memory cell MC
(0), MC (1), ‥‥‥, MC (2n), MC (2
After completion of reading and writing at (n + 1), a plurality of pairs of first and second bit lines ‥‥‥, BL- (m−1); B
LB- (m-1), BL-m; BLB-m, BL- (m
+1); an equalizing circuit EQ for making the potential between BLB- (m + 1) and ‥‥‥ the same is connected.

A plurality of pairs of the first and second bit lines ‥‥‥, BL- (m-1); BLB- (m-1), BL
-M; BLB-m, BL- (m + 1); BLB- (m +
1), a sense amplifier BLB-SA is connected between the first and second bit lines BL-SA and BLB-SA of each pair respectively corresponding to ‥‥‥. Note that the equalizing circuit EQ also
Each pair of first and second bit lines BL-SA, BLB-S
A connection may be made between A.

The sense amplifier SA is controlled by a sensing operation signal SA-On.
It is controlled by the bit line reset signal Eq-On.

The operation of the memory device shown in FIG. 1 will be described below.
This will be described with reference to a timing chart showing signal waveforms in FIG. In the standby state, the gate signals Cut-BL, Cut-BL
Since the voltage of BLB is both H, the MOS-FET Q
1 and Q2 are both ON. For example, word line WL
When the voltage of (0) rises from L to H, the memory cell M
When the MOS-FET Q of C (0) is turned on, the electric charge of the capacitor C flows to the first bit line BL, and a very small voltage is generated between the first and second bit lines BL and BLB.

After that, the sensing operation signal SA-On changes from L to H, and the sense amplifier SA starts to amplify the minute voltage and latches the gate signal before latching to the maximum amplitude Vcc (V) -0 (V). By changing the voltage of Cut-BLB from H to L, the second bit line BLB-m and the second bit line B
The second bit line BLB-SA corresponding to LB-m is separated. The voltage of the gate signal Cut-BL remains at H. As a result, the voltages of the first bit lines BL-m and BL-SA are latched on one side and the second bit line BLB
The voltage of -SA is latched on the other side, but the second bit lines BLB-m and BLB-SA are separated, so that the second bit line BLB-m is in a floating state, and the charge / discharge current is Is reduced. Also, the second bit line B
The bit line capacitance of LB-m is the second bit line BLB
Since the bit line capacitance of −SA is about 5 to 10 times, the current consumption reduction effect is large. In the example of FIG. 2, the latch voltage of the first bit line BLB-SA is 0 (V), but the latch voltage of the second bit line BLB-m is Vcc /
The voltage becomes an intermediate voltage between 2 (V) and 0 (V).

Thereafter, a read / write operation is performed on the read / write (R / W) circuit. Thereafter, the voltage of the word line WL0 changes from H to L. Thereafter, the sensing operation signal SA-On changes from H to L. Thereafter, the voltage of the gate signal Cut-BLB changes from L to H (the voltage of the gate signal Cut-BL remains H), and the bit line reset signal Eq-On changes from L to H (to the bit line reset state). ), The equalizing circuit EQ operates, and the first and second bit lines BL, BL
The first and second bit lines BL and BLB are precharged so that the voltage of B becomes equal to Vcc / 2, and then the standby state is set. In other words, during the precharge period of the first and second bit lines BL and BLB, the MOS-FET
Q1 and Q2 are both ON.

In FIG. 2, the sensing operation signal SA-
The shorter the time between the timing at which the voltage of On rises from L to H and the timing at which the voltage of the gate signal Cut-BLB falls from H to L, the higher the effect of reducing current consumption, and the greater the gate. The shorter the time between the timing when the voltage of the signal Cut-BLB rises from L to H and the timing when the voltage of the bit line reset signal Eq-OnNO rises from L to H, the shorter the bit line B becomes.
The precharge period of L and BLB is shortened.

The word lines WL (0), WL (2), W
When the voltage of L (4), ‥‥‥, WL (2n) changes from L to H, as described above, the gate signal Cut-BL
Is always H, and the voltage of the gate signal Cut-BLB changes from H → L → H. Also, word lines WL (1), W
When the voltages of L (3), WL (5), ‥‥‥, WL (2n + 1) change from L to H, the voltage of the gate signal Cut-BLB is always H, Signal C
The voltage of ut-BL changes from H → L → H.

[0026]

According to the first aspect of the present invention, each of a plurality of pairs of first and second bit lines and a plurality of word lines crossing each other and a plurality of pairs of first and second bit lines alternating with each other are provided. In a memory device having a memory cell connected to each intersection of one bit line and a plurality of word lines and a sense amplifier connected between each pair of first and second bit lines, Is divided into a portion to which each memory cell is connected and a portion to which each sense amplifier is connected, and the two portions of each pair of bit lines are connected and connected respectively. First and second gate means for separating are provided, and when the bit line connected to the accessed memory cell among the plurality of memory cells is the first bit line, the sensing operation is performed. Then, the first gate means is turned on, Of the first and second gate lines during the sensing operation so that the second gate means is turned on and the first gate means is turned off during the sensing operation. Since the gate means is controlled, it is possible to obtain a memory device capable of reducing current consumption for charging and discharging a plurality of pairs of first and second bit lines during a sensing operation.

According to a second aspect of the present invention, in the memory device of the first aspect, during the precharge period for each pair of the first and second bit lines, both the first and second gate means are set to O.
N, a plurality of pairs of first
It is possible to obtain a memory device that can reduce current consumption for charging and discharging the first and second bit lines and can surely perform precharging on the first and second bit lines of each pair. it can.

In the memory device according to the first and second aspects, the memory cell is a D-RAM memory cell.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms of the memory device of FIG. 1;

FIG. 3 is a circuit diagram showing a conventional memory device.

FIG. 4 is a timing chart showing signal waveforms of the memory device of FIG. 3;

[Explanation of symbols]

WL (0), WL (1), WL (2), ‥‥‥, WL
(2n), WL (2n + 1) word line, ‥‥‥, BL
-(M-1); BLB- (m-1), BL-m; BLB
−m, BL− (m + 1); BLB− (m + 1), ‥‥‥
Plural pairs of first and second bit lines, MC (0), MC
(1), ‥‥‥, MC (2n), MC (2n + 1) memory cell, SA sense amplifier, EQ equalizing circuit, DG separation gate, M as gate for Q1, Q2
OS-FET.

Claims (4)

[Claims] A plurality of pairs of first and second bit lines and a plurality of word lines intersecting with each other; In a memory device having a memory cell connected to each crossing part of a word line and a sense amplifier connected between the first and second bit lines of each pair, the first and second memory cells of each pair are provided. The second bit line is divided into a portion to which each of the memory cells is connected and a portion to which each of the sense amplifiers is connected, and the two portions of each pair of bit lines are connected and separated, respectively. A first and a second gate means, wherein the bit line to which the accessed memory cell of the plurality of memory cells is connected is the first bit line; The first gate hand The ON, and OFF said second gate means, said second when the bit lines, during the sensing operation, ON said second gate means, said first gate means O
A memory device characterized by controlling the plurality of first and second gate means so as to perform FF. 2. The memory device according to claim 1, wherein said first and second gate means are both connected during a precharge period for said pair of first and second bit lines.
N. A memory device, wherein N is 3. The memory device according to claim 1, wherein said memory cells are D-RAM memory cells. 4. The memory device according to claim 2, wherein said memory cells are D-RAM memory cells.