JP4934897B2 - Memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device.
[0002]
[Prior art]
A conventional D (dynamic) -RAM memory device will be described with reference to FIG. The memory device includes a plurality of word lines WL (0), WL (1), WL (2),..., WL (2n), WL (2n + 1) and a plurality of pairs of first and second Bit lines..., BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),. WL (0), WL (1), WL (2),..., WL (2n), WL (2n + 1) and a plurality of pairs of first and second bit lines. 1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),...,... (0), MC (1),..., MC (2n), MC (2n + 1).
[0003]
The memory cells MC (0), MC (1),..., MC (2n), MC (2n + 1) are each composed of a series circuit of a switching transistor (MOS-FET) Q and a capacitor C, and the MOS-FET Q Of the plurality of pairs of first and second bit lines BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB -(M + 1),... Are alternately connected, and the gate of the MOS-FET Q has a plurality of word lines WL (0), WL (1), WL (2),..., WL (2n), Each is connected to WL (2n + 1). The capacitor C side of the series circuit is connected to a cell plate potential line (not shown).
[0004]
Also, a plurality of pairs of first and second bit lines..., BL− (m−1); BLB− (m−1), BL−m; BLB−m, BL− (m + 1); BLB− ( m + 1),... between the sense amplifier SA and each of the memory cells MC (0), MC (1),..., MC (2n), MC (2n + 1), after completion of reading and writing. , BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),. An equalizing circuit EQ is connected to make the potential between them the same.
[0005]
The sense amplifier SA is controlled by a sensing operation signal SA-On, and the equalizing circuit EQ is controlled by a bit line reset signal Eq-On.
[0006]
The operation of the memory device of FIG. 3 will be described below with reference to the timing chart showing the signal waveforms of FIG. For example, when the voltage of the word line WL (0) rises from L to H (high) when the bit line reset signal Eq-On is L (low) (release state), the memory cell MC (0 ) Is turned on, the charge of the capacitor C flows to the bit line BL, and a minute voltage is generated between the bit lines BL and BLB. Thereafter, the sensing operation signal SA-On changes from L to H, the sense amplifier SA starts to amplify a minute voltage, and latches to the maximum amplitude. The voltages of the bit lines BL-m and BLB-m are Vcc (Vcc ), Reaches 0 (V). At this time, a large current flows through the sense amplifier SA in order to charge and discharge the bit lines BL and BLB. Thereafter, a read / write operation is performed on the read / write (R / W) circuit. Thereafter, the voltage of the word line WL0 changes from H to L, and then the sensing operation signal SA-On changes from H to L. After that, when the bit line reset signal Eq-On changes from L to H (bit line reset state), the equalization circuit EQ operates and the bit lines BL and BLB are set to have the same voltage as Vcc / 2. After the lines BL and BLB are precharged, the standby state is entered.
[0007]
[Problems to be solved by the invention]
In such a conventional memory device, a plurality of pairs of first and second bit lines and a plurality of word lines intersecting each other, and a plurality of pairs of first and second bit lines each having one bit line and a plurality of bit lines are alternately arranged. In a memory device having a memory cell connected to each crossing portion of a word line and a sense amplifier connected between each pair of first and second bit lines, a plurality of pairs of first lines are provided during a sensing operation. In addition, not only the bit line to which the accessed memory cell is connected among the second bit lines but also the bit line to which the accessed memory cell is not connected is set to the latch voltage having the maximum amplitude. Since it is charged / discharged until it becomes, consumption current will become large too much.
[0008]
In view of the above, the present invention provides a plurality of pairs of first and second bit lines and a plurality of word lines that intersect each other, and a plurality of pairs of first and second bit lines that are alternately one bit line and In a memory device having a memory cell connected to each intersection of a plurality of word lines and a sense amplifier connected between each pair of first and second bit lines, a plurality of pairs at the time of sensing operation An object of the present invention is to propose a memory device that can reduce current consumption for charging and discharging the first and second bit lines.
[0009]
[Means for Solving the Problems]
According to a first aspect of the present invention, a plurality of pairs of first and second bit lines and a plurality of word lines intersecting each other, one of the plurality of pairs of the first and second bit lines alternately, and the plurality of the plurality of pairs. Memory cells respectively connected to the crossing portions of the word lines, sense amplifiers connected between the first and second bit lines of the pairs, and the first and second bit lines of the pairs. 1st and 2nd gate means for connecting and separating between the portion to which the memory cells are connected and the portion to which the sense amplifiers are connected, respectively, and the first gate. The bit line to which the memory cell accessed among the plurality of memory cells is connected is the first bit line. In the case of sensing motion During sensing operation after issuing a signal, issue a gate signal as remains in the ON state the first gate means, said second gate means to the OFF state, is the second bit line In this case, during the sensing operation after issuing the sensing operation signal, the gate signal is issued so that the second gate means remains in the ON state, and the first gate means is in the OFF state . The memory device is configured to control the plurality of first and second gate means.
[0010]
According to the first invention, when the bit line to which the accessed memory cell among the plurality of memory cells is connected is the first bit line, the first gate means is used during the sensing operation. Is turned on, the second gate means is turned off, and in the case of the second bit line, the second gate means is turned on and the first gate means is turned off during the sensing operation.
[0011]
The second invention is the memory device according to the first invention, wherein the first and second gate means are both ON during the precharge period for each pair of the first and second bit lines. is there.
[0012]
In the memory devices of the first and second inventions, the memory cell is a D-RAM memory cell.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An example of a memory device (D-RAM memory device) according to an embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. The memory device includes a plurality of word lines WL (0), WL (1), WL (2),..., WL (2n), WL (2n + 1) and a plurality of pairs of first and second Bit lines..., BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),. WL (0), WL (1), WL (2),..., WL (2n), WL (2n + 1) and a plurality of pairs of first and second bit lines. 1); BLB- (m−1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),...,. D-RAM memory cells) MC (0), MC (1),..., MC (2n), MC (2n + 1).
[0014]
The memory cells MC (0), MC (1),..., MC (2n), MC (2n + 1) are each composed of a series circuit of a switching transistor (MOS-FET) Q and a capacitor C, and the MOS-FET Q Of the plurality of pairs of first and second bit lines BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB -(M + 1),... Are alternately connected, and the gate of the MOS-FET Q has a plurality of word lines WL (0), WL (1), WL (2),..., WL (2n), Each is connected to WL (2n + 1). The capacitor C side of the series circuit is connected to a cell plate potential line (not shown).
[0015]
In FIG. 1, sense amplifiers SA and memory cells MC (0), MC (1),..., MC (2n), MC (2n + 1) are connected as first and second gates for connection and separation. MOS-FETs Q1 and Q2 are connected to a plurality of pairs of first and second bit lines, BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (M + 1); Insert into BLB- (m + 1),. In FIG. 1, for the sake of convenience, reference numerals BL-SA and BLB-SA are attached to the bit lines on the left side of the MOS-FETs Q1 and Q2. Therefore, a plurality of pairs of first and second bit lines, BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- ( m + 1),... are connected to the first and second bit lines BL-SA and BLB-SA via the MOS-FETs Q1 and Q2, respectively.
[0016]
The MOS-FETs Q1 and Q2 are collectively referred to as an isolation gate DG. The MOS-FETs Q1 and Q2 are ON / OFF controlled by different gate signals Cut-BL and Cut-BLB. In this example, N-channel MOS-FETs are used as the MOS-FETs Q1 and Q2, so that when the gate signals Cut-BL and Cut-BLB are H, the MOS-FETs Q1 and Q2 are turned on. When L, it is OFF. P-channel MOS-FETs may be used as the MOS-FETs Q1 and Q2, in which case the gate signals Cut-BL and Cut-BLB H and L, and the MOS-FETs Q1 and Q2 ON, The relationship with OFF is reversed when an N-channel MOS-FET is used.
[0017]
N and P channel MOS-FETs can be used in combination. In that case, the gate signals supplied to the gates of the N and P channel type MOS-FETs must be generated separately according to the N and P channel types.
[0018]
For example, a plurality of pairs of first and second bit lines..., BL- (m−1); BLB- (m−1), BL-m; BLB-m, BL- (m + 1); − (M + 1),..., A plurality of pairs of first and second memory cells MC (0), MC (1),..., MC (2n), MC (2n + 1) Second bit line ..., BL- (m-1); BLB- (m-1), BL-m; BLB-m, BL- (m + 1); BLB- (m + 1), ... An equalize circuit EQ is connected to make the potential the same.
[0019]
Then, a plurality of pairs of first and second bit lines..., BL− (m−1); BLB− (m−1), BL−m; BLB−m, BL− (m + 1); BLB− ( Sense amplifier BLB-SA is connected between each pair of first and second bit lines BL-SA, BLB-SA respectively corresponding to m + 1). Note that the equalize circuit EQ may also be connected between each pair of the first and second bit lines BL-SA and BLB-SA.
[0020]
The sense amplifier SA is controlled by a sensing operation signal SA-On, and the equalizing circuit EQ is controlled by a bit line reset signal Eq-On.
[0021]
In the following, the operation of the memory device of FIG. 1 will be described with reference to a timing chart showing signal waveforms of FIG. In the standby state, since the voltages of the gate signals Cut-BL and Cut-BLB are both H, the MOS-FETs Q1 and Q2 are both ON. For example, when the voltage of the word line WL (0) rises from L to H, the MOS-FET Q of the memory cell MC (0) is turned on, and the charge of the capacitor C flows to the first bit line BL. A minute voltage is generated between the first and second bit lines BL and BLB.
[0022]
Thereafter, before the sensing operation signal SA-On changes from L to H and the sense amplifier SA starts to amplify a minute voltage and latches to the maximum amplitude Vcc (V) -0 (V), the gate signal Cut-BLB Is changed from H to L to separate the second bit line BLB-m from the second bit line BLB-SA corresponding to the second bit line BLB-m. The voltage of the gate signal Cut-BL remains H. As a result, the voltage of the first bit lines BL-m and BL-SA is latched on one side, and the voltage of the second bit line BLB-SA is latched on the other side. Since the bit lines BLB-m and BLB-SA are separated, the second bit line BLB-m is in a floating state, and the charge / discharge current is reduced. Further, since the bit line capacity of the second bit line BLB-m is about 5 to 10 times the bit line capacity of the second bit line BLB-SA, the current consumption reduction effect is great. In the example of FIG. 2, the latch voltage of the first bit line BLB-SA is 0 (V), but the latch voltage of the second bit line BLB-m is Vcc / 2 (V) and 0 (V). The voltage is intermediate between.
[0023]
Thereafter, a read / write operation is performed on the read / write (R / W) circuit. Thereafter, the voltage of the word line WL0 changes from H to L. Thereafter, the sensing operation signal SA-On changes from H to L. Thereafter, the voltage of the gate signal Cut-BLB changes from L to H (the voltage of the gate signal Cut-BL remains H), and the bit line reset signal Eq-On changes from L to H (to the bit line reset state). The first and second bit lines BL and BLB are precharged so that the equalizing circuit EQ operates and the voltages of the first and second bit lines BL and BLB are both equal to Vcc / 2. And then enters a standby state. In other words, the MOS-FETs Q1 and Q2 are both ON during the precharge period of the first and second bit lines BL and BLB.
[0024]
In FIG. 2, the shorter the time between the timing when the voltage of the sensing operation signal SA-On rises from L to H and the timing when the voltage of the gate signal Cut-BLB falls from H to L, the shorter the current consumption. The reduction effect increases, and the shorter the time between the timing when the voltage of the gate signal Cut-BLB rises from L to H and the timing when the voltage of the bit line reset signal Eq-OnNO rises from L to H is shorter. The precharge period of the bit lines BL and BLB is shortened.
[0025]
When the voltage of the word lines WL (0), WL (2), WL (4),..., WL (2n) changes from L to H, as described above, the gate signal Cut-BL The voltage is always H, and the voltage of the gate signal Cut-BLB changes from H → L → H. When the voltage of the word lines WL (1), WL (3), WL (5),..., WL (2n + 1) changes from L to H, the gate signal Cut-BLB is contrary to the above. Is always H, and the voltage of the gate signal Cut-BL changes from H → L → H.
[0026]
【Effect of the invention】
According to the first aspect of the present invention, a plurality of pairs of first and second bit lines and a plurality of word lines intersecting each other, and a plurality of pairs of first and second bit lines, each of which is alternately alternated, and In a memory device having a memory cell connected to each intersection of a plurality of word lines and a sense amplifier connected between each pair of first and second bit lines, each pair of first and second The first and second bit lines are divided into a portion to which each memory cell is connected and a portion to which each sense amplifier is connected, and the two portions of each pair of bit lines are connected and separated, respectively. In the case where the second gate means is provided and the bit line to which the accessed memory cell among the plurality of memory cells is connected is the first bit line, the first bit line is provided during the sensing operation. Gate means ON, second gate means When the second bit line is turned off, the plurality of first and second gate means are controlled so that the second gate means is turned on and the first gate means is turned off during the sensing operation. Thus, it is possible to obtain a memory device that can reduce current consumption for charging / discharging the plurality of pairs of the first and second bit lines during the sensing operation.
[0027]
According to a second invention, in the memory device of the first invention, the first and second gate means are both ON during the precharge period for each pair of the first and second bit lines. Current consumption for charging / discharging a plurality of pairs of first and second bit lines during operation can be reduced, and precharging for each pair of first and second bit lines can be performed reliably. Can be obtained.
[0028]
In the memory devices of the first and second inventions, the memory cell is a D-RAM memory cell.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an example of a memory device according to an embodiment of the present invention.
2 is a timing chart showing signal waveforms of the memory device of FIG. 1. FIG.
FIG. 3 is a circuit diagram showing a conventional memory device.
4 is a timing chart showing signal waveforms of the memory device of FIG. 3;
[Explanation of symbols]
WL (0), WL (1), WL (2), ..., WL (2n), WL (2n + 1) Word line, ..., BL- (m-1); BLB- (m-1) BL-m; BLB-m, BL- (m + 1); BLB- (m + 1),... Multiple pairs of first and second bit lines, MC (0), MC (1),. MC (2n), MC (2n + 1) Memory cell, SA sense amplifier, EQ equalize circuit, DG isolation gate, Q-, MOS-FET as Q2 gate.

Claims (4)

A plurality of pairs of first and second bit lines and a plurality of word lines crossing each other;
A memory cell connected to each of the alternating bit lines of the plurality of pairs of first and second bit lines and the crossing portions of the plurality of word lines;
A sense amplifier connected between each pair of first and second bit lines;
Of the first and second bit lines of each pair, a first and a second for connecting and separating a portion connected to each memory cell and a portion connected to each sense amplifier, respectively. And gate means,
The first gate means and the second gate means are both turned on to issue a sensing operation signal, and a bit line connected to the accessed memory cell among the plurality of memory cells is connected to the first gate means . In the case of the bit line, the gate signal is issued to leave the first gate means in the ON state and the second gate means in the OFF state during the sensing operation after issuing the sensing operation signal. In the case of the second bit line, during the sensing operation after issuing the sensing operation signal, the gate signal is issued to leave the second gate means in the ON state, the gate means to an OFF state, the memory device which is adapted to control the plurality of first and second gate means. 2. The memory device according to claim 1, wherein both the first and second gate means are ON during the precharge period for the first and second bit lines of each pair. The memory device according to claim 1, wherein the memory cell is a D-RAM memory cell. 3. The memory device according to claim 2, wherein the memory cell is a D-RAM memory cell.

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