KR0184088B1 - Semiconductor memory device having a flash write function - Google Patents

Abstract

[purpose]

In a VRAM having a flash write function, a bit line can be precharged sufficiently and reliably in a short time even in a region of low power supply potential by simply adding a strong potential switching circuit to noise, without increasing the circuit in the cell array.

[Configuration]

The bit line pair of the memory cell array is connected to the first bit line pair and column selection transfer gate pair CS and CS of the memory cell and the precharge / equalization circuit 10 by the bit line transfer gate pair Q1 and Q2. The second MOS transistor Q7 and the second end of the second MOS transistor Q8 for flash writing are connected in correspondence with each bit line of the second bit line pair. The potential is set by the potential switching circuit 16 to the bit line precharge potential VBL or the predetermined reference potential VSS.

Description

Semiconductor memory device

1 is a circuit diagram showing a part of a memory cell array constituting a core portion of a VRAM according to a first embodiment of the present invention.

2 is a circuit diagram showing an example of the potential switching circuit in FIG.

3 is a view showing an example of the time change of the main signal to explain the operation example of the circuit of FIG. 1 and FIG.

4 is a circuit diagram showing an example of a memory cell array constituting a core portion of a conventional VRAM.

FIG. 5 is a diagram showing an example of time change of main signals to explain the operation of the circuit of FIG.

* Explanation of symbols for main parts of the drawings

10: precharge equalization circuit 11: P-channel sense amplifier

12 N-channel sense amplifier 13: first flash write circuit

15 flash recording control circuit 16 potential switching circuit

17: control signal generating circuit Q1 to Q10: MOS transistor

CS: transfer gate for column selection FWG1: first flash write signal

FWG2: Second flash write signal VBL: Bit line precharge potential

XGL: first control signal XGD: second control signal

FW: Flash recording mode recognition signal

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory having a flash write (collective write) function such as VRAM (Video Random Access Memory) for pixel data storage.

[Prior art]

FIG. 4 shows a part of the memory cell array corresponding to the core portion of the conventional VRAM (only two rows for simplicity of explanation).

In FIG. 4, MC is a dynamic memory cell, WL is a word line, and two and one are typically represented, respectively. Complementary bit line pairs BLi and / BLi are respectively formed inside the plurality of data line pairs DQRi and / DQRi via the bit line transfer gay pairs Q1 and Q2 and the column select transfer gate pairs CS and CS. It is connected to a pair.

The bit line precharge / equalization circuit 10 and bit line potential re-stored P are stored in the bit line pair (first bit line pair) between the memory cell MC and the bit line transfer gate pairs Q1 and Q2. The channel sense amplifier 11 is connected.

In addition, an N-channel sense amplifier for potential sense between bit line pairs is used in the bit line pair (second bit line pair) between the bit line transfer gate pair Q1 and Q2 and the row select transfer gate pair CS and CS. (12) and one end of the first NMOS transistor Q7 and the second NMOS transistor Q8 for flash writing are connected. The other ends of the first NMOS transistor Q7 and the second NMOS transistor Q8 are collectively connected to the ground potential VSS node.

In addition, VPL is capacitor plate potential, VBL is bit line precharge potential, EQL is equalization signal, SAP is sense enable signal for P-channel sense amplifier, / SAN is enable signal for N-channel sense amplifier, øT Is a bit line transfer gate control signal, FWG0 is a first flash write signal, FWG1 is a second flash write signal, and CSL is a column select signal.

FIG. 5 shows an example of the time change of the main signal to explain the operation example of the circuit of FIG.

Next, an operation example of the circuit of FIG. 4 will be briefly described with reference to FIG.

First, when the / RAS (hang address strobe) signal is at the H level (inactive state), the equalizing signal EQL is at the H level (active state), and the equalizing circuit 10 is turned on. Thus, the first bit line pair on the P-channel sense amplifier side is precharged and equalized to the bit line potential VBL via the equalization circuit 10, and the second bit line pair on the N-channel sense amplifier side is transferred to the bit line. The bit line potential VBL is precharged via the gate pairs Q1 and Q2.

Next, when the / RAS signal becomes L level (active state) and the row address is taken in, the EQL signal first becomes L level (inactive state), and the equalizing circuit 10 is turned off. As a result, the bit lines are switched from the power supply potential VCC, the ground potential VSS, and the bit line potential VBL. When the word line corresponding to the inserted row address is selected, the data of the memory cells of the selected row is read out to the bit line, the sense amplifier 12 is operated to amplify the potential difference between the pair of bit lines, and the sense amplifier 11 ) Is operated to determine the potential of the bit line pair.

Next, when the / RAS signal becomes H level again, the EQL returns to the signal H level, and the equalizing circuit 10 is turned on. Thus, the first bit line pair is again precharged and equalized to the bit line potential VBL through the equalization circuit 10, and the second bit line pair is bit-wise through the bit line transfer gate pairs Q1 and Q2. It is precharged to the potential potential VBL.

In the above operation, the bit line needs to be sufficiently equalized before the sense amplifier 12 starts operation, and the second bit line pair is connected to the bit line potential (B1) through the bit line transfer gate pairs Q1 and Q2. It is necessary to be sufficiently precharged to VBL).

On the other hand, in the region where the power supply potential VCC is high (for example, 5 V), the capability of the transistors Q1 and Q2 for the bit line transfer gate is high, and the threshold voltage Vth is relatively to the power supply potential VCC. Since it is small, the second bit line pair is sufficiently precharged to the bit line potential VBL in a short time.

However, in the region where the power supply potential VCC is low, the capability of the transistors Q1 and Q2 for the bit line transfer gate is lowered, and the threshold voltage Vth cannot be independent of the power supply potential VCC. It is difficult for the two bit line pairs to be sufficiently precharged to the bit line potential VBL in a short time. As a result, if the second bit line pair is sufficiently precharged, the margin of the sense operation in the next cycle is greatly reduced, and there is a fear that the read data from the memory cell is incorrectly sensed.

The first method considered as a solution to the above problem eliminates the insertion of the transistors for the bit line transfer gates Q1 and Q2 so as to eliminate potential charge by the threshold voltage Vth of the transistor. It is precharged.

However, when the bit line transfer gate transistors Q1 and Q2 are closed as described above, the bit line capacitance on the surface becomes large during the initial sense operation of the sense amplifier 12, and high speed and reliable sense operation are difficult.

In the second method considered as the above solution, the transistor has a gate potential of the bit line transfer gate transistors Q1 and Q2 set to be higher than VCC + Vth only for a predetermined period (e.g., a period where the / RAS signal is at the H level). (Q1, Q2) are operated in the triode region, cover the potential drop by the threshold voltage (Vth) of the transistor, and sufficiently precharge the second pair of bit lines.

However, in order to increase the gate potentials of all the bit line transfer gate transistors Q1 and Q2 to be activated in the memory chip to be above VCC + Vth in a short time, a boost circuit using a large capacity and a large area capacitor is required. . In addition, the VRAM operates in an asynchronous manner, and there is a high possibility that the booster circuit may malfunction due to an operation on the serial access memory (SAM) port side, in particular, power supply noise generated during data output.

[Problem to Solve Invention]

As described above, the conventional semiconductor memory device has a problem that it is difficult to sufficiently precharge the bit line in a short time in the region of low power supply potential, the margin of the sense operation is greatly reduced, and there is a possibility of sensing wrong data. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and the bit line can be reliably sufficiently short and short even in a region having low power supply potential by simply adding a strong potential switching circuit to relatively simple noise without increasing the circuit in the memory cell array. An object of the present invention is to provide a semiconductor memory device capable of precharging and accurately sensing and outputting read data from a memory cell.

[Means for solving the problem]

The present invention provides a semiconductor memory device having a flash write function, comprising: a memory cell array in which dynamic memory cells are arranged in a matrix, a word line connected to memory cells in the same row, and memory cells in the same column, respectively; A complementary bit line pair, a column selection transfer gate pair connected to one end of said bit line pair, a data line pair connected to said column selection transfer gate pair, and each bit line of said bit line pair are inserted in series A bit line transfer gate pair of a first conductivity type for dividing the bit line pair into a first bit line pair on the memory cell side and a second bit line pair on the column selection transfer gate pair side, and a precharge connected to the first bit line pair The bit line precharge and equalization hero, which is controlled to be in an ON state during the equalization period, and two MOS transistors of the second conductivity type connected to the first bit line pair are cross-connected. A second sense amplifier for bit line potential re-memory which is driven for a period of time and two MOS transistors of a first conductivity type connected to the second bit line pair are cross-connected and driven for a predetermined period; Precharges the first MOS transistor and the second MOS transistor for flash writing, and the first MOS transistor and the second MOS transistor, each end of which is connected to a sense amplifier, each bit line of the second bit line pair, and the first MOS transistor and the second MOS transistor. A flash write control circuit for switching control according to the write data in the non-flash write mode and the flash write mode during the equalization period, and an output node connected to each other end of the first MOS transistor and the second MOS transistor, And a potential switching circuit capable of setting the potential of the node to the bit line precharge potential for bit line initial potential setting or a predetermined reference potential.

[Action]

The present invention configured as described above has a potential switching circuit, whereby the transistor for flash writing can perform not only the original flash writing operation but also the bit line equalizing operation. In this case, the potential switching circuit can be made to have a strong characteristic against noise with a relatively simple configuration.

Only by adding the above-mentioned potential switching circuit, the bit line can be sufficiently precharged in a short time and securely even in a region having low power supply potential without increasing the circuit in the memory cell array, and accurately reading data from the memory cell. Can be output.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows one end of the memory cell array constituting the core portion of the VRAM having the flash write function according to the first embodiment of the semiconductor memory device of the present invention (only two rows for simplicity of explanation).

In FIG. 1, MC is a dynamic memory cell (only two are shown for the sake of simplicity shown) arranged in a matrix to form an array of memory cells, and the capacitor is given a capacitor plate potential VPL. . WL is a word line (typically only one) is connected to memory cells in the same row of the memory cell array, and is selectively driven for a predetermined period by the word line driving signal. BL0, / BL0, BL1, and / BL1 are complementary bit line pairs (typically only two pairs are shown) connected to memory cells in the same column of the memory cell array, respectively.

(CS, CS) are respectively connected to one end of each bit line of the bit line pair, and are a column selection transfer gate selected by the same column select signal CSLi (CSL0 in this column).

In this case, column selection transfer gate pairs CS and CS of a plurality of predetermined columns are commonly selected by the column selection signal CSL0.

DQRi and / DQRi are data line pairs connected to the other ends of the column selection transfer gate pairs CS and CS, and a plurality of data line pairs DQR0 and / DQR0 connected to correspond to the plurality of commonly selected columns. DQR1, / DQR1)... Is formed.

(Q1, Q2) are respectively inserted in series with each bit line of the bit line pair, and the N-channels in which the bit line pair is decomposed into a first bit line pair on the side of the memory cell and a second bit line pair on the side of the column selection transfer gate pair It is a bit line transfer gate pair made of a type MOS transistor, and is commonly driven by the same bit line transfer gate control signal? T.

A bit line precharge equalization circuit 10 is connected to the first bit line pair, and a precharge equalization circuit 10 is connected to the first bit line pair and an equalization signal during the precharge equalization period. It is controlled on by (EQL).

A P-channel sense amplifier 11 for re-memory of bit line potential is connected to the first bit line pair, and two P-channel MOS transistors Q3 and Q4 driven by a sense enable signal SAP cross each other. Connected.

An N-channel sense amplifier 12 for detecting a potential difference between bit line pairs is connected to the second bit line pair and crosses two N-channel MOS transistors Q5 and Q6 driven by a sense enable signal / SAN. Connected.

The first flash writing circuit 13 and the second flash writing circuit 14 are connected to the respective bit lines of the second bit line pair.

In the present example, the first flash write circuit 13 includes an N-channel type MOS transistor Q7 for flash write whose one end is connected to one bit line BL0 or BL1. Similarly, the second flash write circuit 14 is composed of an N-channel second MOS transistor Q8 for flash write, one end of which is connected to the other bit line / BL0 or / BL1 in this example.

The two MOS transistors Q7 and Q8 are switched by the flash write control circuit 15 in accordance with the precharge / equalize period, the non-flash write mode and the write data in the flash write mode.

The flash write control circuit 15 controls both the first MOS transistor Q7 and the second MOS transistor Q8 in the on state during the precharge / equalization period, and in the non-flash write mode, the first MOS transistor Q8. Both the MOS transistor Q7 and the second MOS transistor Q8 are controlled in an off state, and in the flash write mode, the first MOS transistor Q7 and the second MOS in a predetermined period before driving the sense amplifier 12. Logically configured to generate a first flash write signal FWG1 and a second flash write signal FWG2 for alternatively controlling the transistor Q8 to the on state.

In the potential switching circuit 16, an output node is connected to each other end of the first MOS transistor Q7 and the second MOS transistor Q8, and the potential of the output node is set to the bit line precharge for initializing the bit line. It is set to the potential VBL (usually 1/2 of the power supply potential VCC) or a predetermined reference potential (the ground potential VSS in this example), and is configured as shown in FIG. 2, for example.

That is, the potential switching circuit 16 is connected between the VBL node, to which the bit line precharge potential VBL is applied, and the output node, and is made of an N-channel type, in which a first control signal GL is applied to a gate. The fourth NMOS transistor of the N-channel type, which is connected between the MOS transistor Q9 and the VSS node to which the predetermined reference potential VSS is applied and the output node and is supplied with the second control signal XGD to the gate. Q10 and a control signal generation circuit 17 for generating the first control signal XGL and the second control signal XGD.

The control signal generation circuit 17 is supplied with VCC and VSS as an operating power supply, and the third MOS transistor Q9 is turned on in the precharge / equalization period and the non-flash write mode, and the fourth NMOS transistor is turned on. (Q10) is turned off, and in the flash write mode, the third NMOS transistor Q9 is turned off, and the fourth NMOS transistor Q10 is turned off for a predetermined period before the sense amplifier is driven. Logic is configured to control.

That is, the control signal generation circuit 17 includes, for example, an inverter circuit 21 inverting the / RAS signal as shown in FIG. 2, an output signal of the inverter circuit 21, and a flash write mode recognition signal FW. NAND gate circuit 22 which outputs the control signal XGL in a logical manner, a delay circuit 23 for delaying the control signal XGL by a predetermined time, and an inverter circuit inverting the control signal XGL. (24), the NAND gate circuit 25 taking the logical relationship between the output signal of the inverter circuit 24 and the output signal of the delay circuit 23 and the output signal of the NAND gate circuit 25 The inverter circuit 26 outputs the control signal XGD. The H level of the control signals XGL and XGD is VCC, and the L level is VSS.

In addition, the two NMOS transistors Q9 and Q10 of the potential switching circuit 16 are provided outside the memory cell array, and the circuit configuration of the memory cell array is the same as before.

Next, operation examples of the circuits of FIGS. 1 and 2 will be described with reference to FIG.

FIG. 3 shows an example of the time change of the main signals in the non-flash write mode and in the flash write mode to explain the operation example of the circuits of FIG. 1 and FIG.

First, the operation in the non-flash recording mode will be described. When the / RAS signal is at the H level (inactive state), the equalizer signal EQL is at the H level VCC, and the precharge equalization circuit 10 is turned on.

At this time, the control signal XGL becomes VCC, the control signal XGD becomes VSS, the NMOS transistor Q9 of the potential switching circuit 16 is turned on, the NMOS transistor Q10 is turned off, and the output node is turned off. 16a becomes the VBL potential.

At this time, the flash write signals FWG1 and FWG2 are at the H level VCC, and the first flash write transistor Q7 and the second flash write transistor Q8 are turned on, respectively.

As a result, the bit line pair on the side of the P-channel sense amplifier 11 is precharged and equalized to the bit line potential VBL through the precharge-equalization circuit 10, and on the N-channel sense amplifier 12 side. The bit line pair is precharged to the bit line potential VBL through the potential switching circuit 16, the first flash writing transistor Q7, and the second flash writing transistor Q8.

At this time, since the control signal? T is at the H level VCC and the bit line transistors Q1 and Q2 are in the on state, the bit line pairs on the N-channel sense amplifier 12 side and the P-channel sense amplifier 11 side. The bit line pairs of are equalized to the coin point VBL through the bit line transfer gates Q1 and Q2.

Next, when the / RAS signal becomes L level (active state) and the row address is taken in, first, the EQL signal and flash write signals FWG1 and FWG2 become L level (inactive state), and then the precharge equalizing circuit. (10) is turned off. As a result, the bit lines are switched from the power supply potential VCC, the ground potential VSS, and the bit line potential VBL. When the word line corresponding to the inserted row address is selected as described above, the data of the memory cells of the selected row is read out to the bit line, and the sense amplifiers 11 and 12 are operated to further amplify the potential difference between the pair of bit lines. do.

Next, when the / RAS signal reaches the H level again, the EQL signal and the flash write signals FWG1 and FWG2 return to the H level, respectively, and the precharge equalization circuit 10 and the first flash write transistor Q7. ) And the second flash write transistor Q8 are turned on, respectively. As a result, the bit line on the P-channel sense amplifier 11 side is again precharged and equalized to the bit line potential VBL through the precharge-equalization circuit 10, and on the N-channel sense amplifier 12 side. The bit line pair is precharged to the bit line potential VBL through the potential switching circuit 16, the first flash writing transistor Q7, and the second flash writing transistor Q8. At this time, since the control signal? T is at the H level and the bit line transfer gates Q1 and Q2 are on, the bit line pair on the N-channel sense amplifier 12 side and the bit line pair on the P-channel sense amplifier 11 side. Is equalized on the coin VBL through the bit line transfer gates Q1 and Q2.

In the operation in the non-full write mode as described above, the bit line pair on the N-channel sense amplifier 12 side includes the potential switching circuit 16, the first flash writing transistor Q7, and the second flash writing transistor ( Since it is precharged to the bit line potential VBL via Q8), it is possible to sufficiently precharge the bit line in a short time as compared with the conventional example.

In addition, since the output node 16a of the potential switching circuit 16 during the operation in the non-flash recording mode is constant at VBL and no charge / discharge occurs, no current consumption occurs.

Next, the operation in the flash recording mode will be described. When the / RAS signal is at the H level, the equalization signal EQL is at the H level, the control signal XGL is at VCC, the control signal XGD is at VSS, and the flash write signals FWG1 and FWG2 are at H level. The operations until the bit line pair on the P-channel sense amplifier 11 side and the bit line pair on the N-channel sense amplifier 12 side are precharged and equalized to the bit line potential VBL are in the non-flash lock mode described above. Is the same as the operation.

Next, when the / RAS signal becomes L level and it is determined that the flash recording mode is set, the flash recording mode recognition signal FW is set to H level by a function decoder (not shown). At this time, the control signal XGL becomes VSS, and the NMOS transistor Q9 of the potential switching circuit 16 is turned off. Then, when the hang address is taken in, the EQL signal is first brought to the L level, and the precharge equalization circuit 10 is turned off, and the bit line is the power supply potential VCC, the ground potential VSS, the bit line potential. It is switched from (VBL). At this time, the XGL signal and the flash write signals FWG1 and FWG2 become L level, and the first flash write transistor Q7 and the second flash write transistor Q8 are turned off, respectively.

Then, before performing the actual flash write operation, the XGD signal is set to VCC, the NMOX transistor Q10 of the potential switching circuit 16 is turned on, and the output node 16a is at the VSS potential. When the word line corresponding to the inserted row address is selected as described above, the data of the memory cells of the selected row is read out to the bit line. Before and after this operation, either one of the flash write signals FWG1 and FWG2 becomes H level, and either one of the first flash write transistor Q7 and the second flash write transistor Q8 is turned on. It becomes

At this time, when writing all data 0 of the memory cells connected to the selected word line WL, the first flash write transistor Q7 connected to one of the bit line pairs (for example, BL0 and LB1) is turned on. In this state, the flash write signal FW1 becomes H level. Thus, even if data 1 has been previously written to the memory cell in advance, the first flash write transistor Q7 is turned on as described above, so that one of the bit lines BL0 and BL1 is discharged to the VSS potential. It is surely lower potential than the bit lines / BL0 and / BL1 on the other side.

On the other hand, when writing all data 1 of the memory cells connected to the selected word line, the second flash write transistor Q8 connected to the other side of the bit line pair (for example, / BL0, / BL1) is replaced. Since it is turned on, the flash write signal FWG2 becomes H level. Thus, even if data 0 has been previously written to the memory cell for a while, since the second flash write transistor Q8 is turned on as described above, the other bit lines / BL0 and BL1 are discharged to the VSS potential, so that the other bit lines are discharged. It is surely lower potential than the bit lines BL0 and BL1 on the side.

After the potential difference between the bit line pairs is generated, the flash write mode recognition signal FW becomes L level, the control signal XGD becomes VSS, and the NMOS transistor Q10 of the potential switching circuit 16 It turns off.

Thereafter, the sense amplifiers 11 and 12 operate to amplify the potential difference between the pair of bit lines. At this time, since the potentials of all the bit lines are shifted in the same direction, the same data is written to all of the memory cells connected to one word line that is finally selected.

Next, when the / RAS signal becomes H level again, the EQL signal and the flash write signals FWG1 and FWG2 return to the H level, respectively, and the control signal XGL returns to VCC, and the precharge equalization circuit ( 10) and the first flash write transistor Q7 and the second flashlock transistor Q8 are turned on, respectively, and the NMOS transistor Q9 of the potential switching circuit 16 is turned on and its output node is turned on. The potential of 16a becomes VBL. Thus, the bit line pair on the P-channel sense amplifier 11 side is again precharged and equalized to the bit line potential VBL through the precharge-equalization circuit 10, and the N-channel sense amplifier 12 side is The bit line pair is precharged to the bit line potential VBL through the potential switching circuit 16, the first flash writing transistor Q7, and the second flash writing transistor Q8.

At this time, since the control signal? T is at the H level and the bit line transistors Q1 and Q2 are in the ON state, the bit line pair on the N-channel sense amplifier 12 side and the bit line pair on the P-channel sense amplifier 11 side. Is equalized on the coin VBL through the bit line transfer gates Q1 and Q2.

By the operation in the flash write mode as described above, the flash write operation and subsequent bit line precharge / equalize operations can be normally performed.

In other words, according to the VRAM of the above embodiment, the flash write transistors Q7 and Q8 have not only the original flash write operation but also a bit line equalization operation, so that the bit lines can be short-lived even in a region having a low power supply potential. It can be precharged sufficiently surely, and the read data from the memory cell can be accurately sensed and output.

Further, in a region where the power supply potential is low, a booster circuit for raising the gate potential of the bit line flash write transistors Q1 and Q2 in the triode region is required to be higher than VCC + Vth only for a predetermined period. In addition, this step-up circuit does not cause a problem of malfunction due to, for example, power supply noise occurring at the time of data output.

In addition, since the bit line transfer gates Q1 and Q2 exist as in the prior art, and the bit line capacitance on the surface decreases during the initial sense operation of the sense amplifier, the margin during the initial sense operation of the sense amplifier may be lowered.

In addition, the two NMOS transistors Q9 and Q10 of the potential switching circuit 16 added in the above embodiment can be provided outside the memory cell array, and the circuits in the memory cell array need not be increased. Furthermore, the potential switching circuit 16 has a relatively simple configuration, and malfunctions due to noise or the like are unlikely to occur.

On the other hand, the reference numerals written in the elements of the claims of the present application together to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

[Effects of the Invention]

As described above, according to the semiconductor memory device of the present invention, the bit line can be sufficiently secured in a short time even in a region of low power supply potential by simply adding a potential switching circuit that is relatively resistant to noise, without increasing the circuit in the memory cell array. Can be precharged, and can accurately output the data read from the memory cell.

Claims (4)

A memory cell array in which dynamic memory cells MC are arranged in a row, a word line WL connected to memory cells in the same row, and complementary bit line pairs (BL0, respectively) connected to memory cells in the same column. / BL0), (BL1, / BL1)), column select transfer gates CS and CS connected to one end of the bit line pair, and data line pairs connected to the column select transfer gate pair (DQR0, / DQR0), (DQR1, / DQR1), (DQRi, / DQRi)), and each bit line pair of the bit line pair are inserted in series to insert the bit line pair for the first bit line pair and the column selection on the memory cell side. Bit line transfer gate pairs Q1 and Q2 of the first conductivity type, which are divided into second bit line pairs on the transfer gate pair side, and bit lines connected to the first bit line pair and controlled on-state in the precharge / equalization period. A precharge equalization circuit 10, bit line potential sense amplifiers 11 and 12 connected to the bit line pair and driven for a predetermined period; The first MOS transistor Q7 and the second MOS transistor Q8 for flash writing, each end of which is connected to each bit line of the second bit line pair, and the first MOS transistor and the second MOS transistor are free. A flash write control circuit 15 for controlling switching according to write data in the non-flash write mode and the flash write mode during the charge / equalization period, and an output node at each other end of the first MOS transistor and the second MOS transistor. And a potential switching circuit (16) for connecting the potential of said output node to a bit line precharge potential for bit line initial potential setting or a predetermined reference potential. 2. The flash write control circuit of claim 1, wherein the flash write control circuit controls both the first MOS transistor and the second MOS transistor to be in an on state during the precharge / equalization period, and the first MOS transistor in a non-flash write mode. And controlling both of the second MOS transistors in an off state, and selectively controlling the first MOS transistors and the second MOS transistors in an on state in a predetermined period before driving the sense amplifier in the flash write mode. Semiconductor memory device. 3. The third MOS transistor (Q9) according to claim 1 or 2, wherein the potential switching circuit is connected between a node to which the bit line precharge potential is applied and the output node and a first control signal is applied to a gate. ), A fourth MOS transistor Q10 connected between a node to which the predetermined reference potential is applied and the output node, and a second control signal is applied to a gate, and the first control signal and the second control signal. And a control signal generating circuit (17) for generating. 4. The control signal generation circuit according to claim 3, wherein the control signal generation circuit controls the third MOS transistor to be in an on state and the fourth MOS transistor to be in an off state during the precharge / equalization period and the non-flash write mode, and flash write is performed. And controlling the third MOS transistor to be in an off state in the mode, and controlling the fourth MOS transistor to be in an on state for a predetermined period of time before driving the sense amplifier.