KR960019296A

KR960019296A - Semiconductor memory device

Info

Publication number: KR960019296A
Application number: KR1019950041470A
Authority: KR
Inventors: 야스유키 카이
Original assignee: 사토 후미오; 가부시키가이샤 도시바
Priority date: 1994-11-15
Filing date: 1995-11-15
Publication date: 1996-06-17
Also published as: JPH08147965A; US5650970A; CN1107957C; CN1153983A; KR0184088B1

Abstract

[목적][purpose]

플래시기록기능을 갖춘 VRAM에 있어서, 셀어레이 내의 회로를 증가시키지 않고, 비교적 간단히 노이즈에 강한 전위절환회로를 부가하는 것만으로 전원전위가 낮은 영역에 있어서도 비트선을 단시간에 충분히 확실하게 프리차지한다.In a VRAM having a flash write function, a bit line can be precharged sufficiently and reliably in a short time even in a region of low power supply potential by simply adding a strong potential switching circuit to noise, without increasing the circuit in the cell array.

[구성][Configuration]

메모리셀 어레이의 비트선쌍을 비트선 전송게이트쌍(Q1,Q2)에 의해 메모리셀 및 프리차지ㆍ이퀄라이즈회로(10)측의 제1비트선쌍 및 열선택용 전송게이트쌍(CS,CS)측의 제2비트선쌍으로 분할하고, 제2비트선쌍의 각 비트선에 대응하여 플래시기록용의 제1MOS 트랜지스터(Q7) 및 제2MOS트랜지스터(Q8)의 각 일단을 접속하며, 그 각 타단의 전위를 전위절환회로(16)에 의해 비트선 프리차지전위(VBL) 또는 소정의 기준전위(VSS)로 설정하는 것을 특징으로 한다.The bit line pair of the memory cell array is transferred to the memory cell and the first bit line pair and column selection transfer gate pair (CS, CS) side of the memory cell and the precharge / equalization circuit 10 side by the bit line transfer gate pairs (Q1, Q2). Divided by the second bit line pair, and one end of each of the first MOS transistor Q7 and the second MOS transistor Q8 for flash writing is connected to correspond to each bit line of the second bit line pair, and the potential of the other end is The potential switching circuit 16 sets the bit line precharge potential VBL or the predetermined reference potential VSS.

Description

Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 실시예 1에 따른 VRAM의 코어부를 구성하는 메모리셀 어레이의 일부를 나타낸 회로도,1 is a circuit diagram showing a part of a memory cell array constituting a core portion of a VRAM according to Embodiment 1 of the present invention;

제2도는 제1도중의 전위절환회로의 일례를 나타낸 회로도.2 is a circuit diagram showing an example of the potential switching circuit in FIG.

Claims

Memory cell arrays in which dynamic memory cells MC are arranged in a row form, word lines WL connected to memory cells in the same row, and complementary bit line pairs BL0, / connected to memory cells in the same column, respectively. BL0), (BL1, / BL1), column select transfer gates (CS, CS) connected to one end of the bit line pair, and data line pairs (DQR0, / DQR0) connected to the column select transfer gate pair. , (DQR1, / DQR1),... And (DERi, / DQRi) and each bit line pair of the bit line pair are serially inserted to divide the bit line pair into a first bit line pair on the memory cell side and a second bit line pair on the column selection transfer gate pair side. A bit line precharge / equalization circuit 10 connected to the first conductive type bit line transfer gate pairs Q1 and Q2 and controlled to be in an on state during the precharge / equalization period, connected to the first bit line pair; Bit line potential sense amplifiers 11 and 12 connected to the bit line pair and driven for a predetermined period, a first MOS transistor Q7 for flash writing and one end connected to each bit line of the second bit line pair; A flash write control circuit 15 for switching the 2MOS transistor Q8 and the first MOS transistor and the second MOS transistor according to the write data in the non-flash write mode and the flash write mode during the precharge and equalize periods; , The first MOSFET An output node is connected to each other end of the jitter and the second MOS transistor, and a potential switching circuit 16 is provided which can set the potential of the output node to the bit line precharge potential for bit line initial potential setting or a predetermined reference potential. A semiconductor memory device, characterized in that.

2. The flash write control circuit of claim 1, wherein the flash write control circuit controls both the first MOS transistor and the second MOS transistor to be in an on state during the precharge / equalization period, and in a non-flash write mode, both the first MOS transistor is in an on state. In the non-flash write mode, both the first MOS transistor and the second MOS transistor are controlled to be in an off state, and in the flash write mode, the first MOS transistor and the second MOS transistor are alternatively selected for a predetermined period before driving the sense amplifier. The semiconductor memory device, characterized in that controlled to the on state.

3. The third MOS transistor (Q9) according to claim 1 or 2, wherein the potential switching circuit is connected between a node to which the bit line precharge potential is applied and the output node, and a first control signal is applied to a gate. And a fourth MOS transistor Q10 connected between the node to which the predetermined reference potential is applied and the output node, and receiving a second control signal to a gate, and generating the first control signal and the second control signal. And a control signal generation circuit (17) for the semiconductor memory device.

4. The control signal generation circuit according to claim 3, wherein the control signal generation circuit controls the third MOS transistor to be in an on state and the fourth MOS transistor to be in an off state in the precharge / equalization period and the non-flash write mode, and in the flash write mode. And controlling the third MOS transistor to be in an off state and controlling the fourth MOS transistor to be in an on state for a predetermined period before driving the sense amplifier.

※ Note: The disclosure is based on the initial application.