KR100334530B1 - Shared bit line driver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line driving device of a semiconductor memory, and more particularly, a part of each bit line group divided by dividing each bit line pair having a folded bit line structure and connected to a bit line sense amplifier. By selectively connecting to the bit line sense amplifier by metal wiring, the Cb: Cs ratio is improved to prevent malfunction during sensing, and a separate precharge means is provided at one end of each divided bit line group. A divided bit line driving device which speeds up a line precharge operation.

Description

Split bit line driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line driving device of a semiconductor memory, and more particularly, by dividing and selectively connecting a bit line pair connected to a bit line sense amplifier in a folded bit line manner by improving the Cb: Cs ratio. The present invention relates to a divided bit line driving apparatus which prevents a malfunction of the plurality of bit lines and has a precharge means at one end of each divided bit line group, thereby speeding up the bit line precharge operation.

In general, a pair of bit lines are connected in parallel to a cell array, and 128 cells are connected to each bit line, and different word lines are connected to a plurality of cells connected to the same bit line.

In addition, a voltage line and a control line for 1/2 Vcc precharge of the bit line pair are positioned opposite to the bit line sense amplifier. This configuration method is referred to as a "folded bit line method."

FIG. 1 is a circuit diagram showing a conventional bit line driving device. The bit line sense amplifier 10 of a CMOS latch type cross-couple structure (a detailed circuit configuration is not shown) and both sides of the bit line sense amplifier 10 are shown. A pair of global bit line pairs BL0, / BL0 and BL1, / BL1 connected to each other in parallel to each other, and a predetermined position on each of the global bit lines BL0, / BL0 and BL1, / BL1, respectively. NMOS transistors T0 to T3 serving as switching elements that are selectively turned on by the bit line separation control signals BISi and BISj to transfer data to the bit line sense amplifier 10.

In the conventional bit line driving device having the above configuration, the bit line separation control signals BISi and BISj are operated by delayed signals under the control of the row address signal and the ras signal RAS in the standby and active states. It is controlled and is shown briefly in Table 1 below.

TABLE 1

BISi (Waiting) BISi (when activated) BISj (Waiting) BISj (when activated) WL 0 (disabled) Logic high Logic high Logic high Logic high WL 0 (enabled) Logic high Logic high Logic low Logic low

As can be seen from Table 1, in the standby mode in which the low address is applied in the disabled state, the high voltage of the logic high level is applied as the bit line separation control signals BISi and BISj, and all the bit lines BL0 and / are applied. BL0, BL1, / BL1 are waiting to be connected to the bit line sense amplifier 10.

In this state, when a row address is input and one word line (assuming WL0) is activated, only the bit line separation control signal BISi corresponding thereto maintains the logic high level and the other bit line separation control signals. (BISj in this case) is transitioned to the "logic low" level, and according to the state of these bit line separation control signals BISi and BISj, two NMOS transistors (left) of the sense amplifier 10 in the figure are shown. T0 and T1 are turned on, while the two NMOS transistors T2 and T3 located on the right side are turned off.

Accordingly, one bit line pair BL0, / BL0 is connected to the bit line sense amplifier 10, and the other bit line pair BL1, / BL1 is disconnected.

At this time, since the word line to be activated is WL0, the data finally transferred to the bit line sense amplifier 10 becomes data loaded on the bit line BL0.

The conventional bit line driving device for driving the bit line by the above operation is designed to increase the number of bit line sense amplifiers 10 array as a result of the fact that a limited number of memory cells can be connected to one global bit line. There is a problem that the burden on the area.

For reference, for example, the Cb: Cs ratio of 0.18μm 64M SDRAM (where C is the capacitance, b is the bitline, and s is the storage node potential of the memory cell) is 512 rows (256 cells are bitlines). If you use 1024 ROH (meaning 512 cells are connected to the bitline), the ratio is increased to about 17.6: 1 and the burden on the bitline sense amplifier is high. The operating characteristics are worsened. Accordingly, an increase in the bit line sense amplifier 10 is essentially required.

Further, during precharging, precharge occurs only on one side of the bit line sense amplifier 10 so that its transmission rate is equal to Rb Cb = 0.9Δt (where R is resistance, C is capacitance, and b is bit line). As a result, there is a problem of delaying bit line precharge to inhibit the speed.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to improve the Cb: Cs ratio, thereby eliminating the design area burden caused by the increase of the bitline sense amplifier, and at the same time enabling a fast bitline precharge operation. The present invention provides a split bit line driving device.

In order to achieve the above object, the divided bit line driving apparatus according to the first embodiment of the present invention includes a bit line sense amplifier having a folded bit line structure.

The first bit line group adjacent to the bit line sense amplifier is directly connected to the bit line sense amplifier by dividing each bit line pair connected in parallel to both sides of the bit line sense amplifier. A bit line dividing unit for connecting a second bit line group located far away to connect a metal line to a bit line sense amplifier in parallel with the first bit line group;

A switch connected to the first bit line group and a predetermined position on the metal line, respectively, and selectively switched according to a bit line separation control signal to selectively connect the first and second bit line groups to a bit line sense amplifier. It is characterized by comprising a part.

In addition, the divided bit line driving apparatus according to the second exemplary embodiment of the present invention is connected between each pair of bit lines constituting the first and second bit line groups to perform a precharge operation by bit line equalization. It is characterized by comprising a part.

1 is a circuit diagram showing a conventional bit line driving device

2 is a circuit diagram illustrating a split bit line driving apparatus according to a first exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a split bit line driving apparatus according to a second exemplary embodiment of the present invention.

4 is a circuit diagram illustrating an example of the precharge unit illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10: bit line sense amplifier 20, 21: bit line division unit

30, 31: switching section 40 to 43: precharge section

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a circuit diagram showing a divided bit line driving apparatus according to a first embodiment of the present invention, comprising: a CMOS latch type bit line sense amplifier 10 having a folded bit line structure; The first bit line group seg_BL1, / seg_BL1 and seg_BL3, / seg_BL3 adjacent to the bit line sense amplifier by dividing each bit line pair connected in parallel to both sides of the bit line sense amplifier 10, directly, In addition, the second wiring line seg_BL0, seg_BL0, seg_BL2, and seg_BL2, which are relatively far from the bit line sense amplifier 10, may be connected to the metal lines met_BL0, / met_BL0, met_BL1, and / met_BL1, respectively. Bit line dividers 20 and 21 connected to the amplifier 10; Bit line separation control signals BIS0 to BIS3 are connected to predetermined positions on the first bit line group seg_BL1, / seg_BL1 and seg_BL3, / seg_BL3, and the metal lines met_BL0, / met_BL0 and met_BL1, and / met_BL1, respectively. It is configured to have a switching unit (30, 31) selectively switched according to the) to selectively connect the first and second bit line group to the bit line sense amplifier (10).

Hereinafter, the operation of the divided bit line driving apparatus according to the present invention having the above configuration will be described in detail with reference to the accompanying drawings. First, the state of the bit line separation control signals BIS0 to BIS3 in the standby and activation modes is determined according to the following table 2 according to the global signal (signal delayed under lath control) of the input bit line sense amplifier and the corresponding row address. Each has a logic state as shown in Table 3, and only two wordline states are shown to avoid repetition of the description.

TABLE 2

BIS0 BIS1 BIS2 BIS3 Standby On activation Standby On activation Standby On activation Standby On activation WL0Disable H H H H H H H H WL0 Enable H H L L L L L L

TABLE 3

BIS0 BIS1 BIS2 BIS3 Standby On activation Standby On activation Standby On activation Standby On activation WL3Disable H H H H H H H H WL3 Enable L L H H L L L L

As can be seen from Tables 2 and 3 above, in the standby mode in which the low address is applied in the disabled state, the high voltage of the logic high level is applied as the bit line separation control signals BIS0 to BIS3. The bit lines seg_BL0 to seg_BL3 and / seg_BL0 to / seg_BL3 are waiting to be connected to the bit line sense amplifier 10.

In this state, when a row address is input and a word line (assuming 'WL0', for example, shown in Table 2) is activated, only the bit line separation control signal BIS0 corresponding to the logic line is 'high'. The NMOS transistors T0 and T1 as switching elements are maintained at the level and the other bit line separation control signals BIS1 to BIS3 are transferred to the logic low level while the bit line separation signal BIS0 is applied to the gate terminal. Only turns on.

As a result, the bit lines seg_BL0 and / seg_BL0 connected to both ends separate the data.

In this case, the bit line separation unit 20 connects the metal wires (met_BL0, / met_BL0) connected to the data contained in the divided bit lines (seg_BL0, / seg_BL0) located relatively far from the bit line sense amplifier 10. After passing through the bit line sense amplifier 10.

In addition, even when a word line that is activated due to input of another row address is changed, bit line separation is performed by the same operation, and thus a detailed description thereof will be omitted.

FIG. 3 is a circuit diagram illustrating a split bit line driver according to a second exemplary embodiment of the present invention, wherein the basic circuit configuration of the divided bit line driver shown in FIG. 2 is precharged by bit line equalization. Each precharge unit 40 to 43 is further configured between each pair of bit lines constituting the first and second bit line groups to perform an operation.

FIG. 4 is a circuit configuration diagram showing an example of the precharge units 40 to 43 shown in FIG. 3, and is composed of NMOS transistors to which a precharge control signal pcg is applied to the gate terminal.

At this time, the precharge control signal pcg becomes a logic high pulse signal that maintains a high voltage state during the precharge operation.

Thus, the precharge units 40 to 43 connected to both ends of each of the divided bit line groups are enabled only during the subsequent precharge operation after activating the preselected bit line when the word line is activated due to the input of the row address. The pre-selected bit lines are precharged to Vcc / 2 level.

Hereinafter, since the divided bit line driving operation is the same as in the first embodiment of the present invention shown in FIG. 2, detailed operation description will be omitted.

As described above, according to the divided bit line driving apparatus according to the present invention, the Cb: Cs ratio can be improved to significantly reduce a malfunction in sensing the memory cell array.

In addition, the number of bit line sense amplifier arrays can be greatly reduced according to the use of the divided bit line structure, thereby reducing the area burden required for chip design.

In addition, since the precharge unit provided at one end of each bit line group performs the precharge operation of the corresponding bit line at high speed, it is possible to realize the high speed of the entire chip.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (3)

A semiconductor memory device having a bit line sense amplifier having a folded bit line structure, The first bit line group adjacent to the bit line sense amplifier is directly connected to the bit line sense amplifier by dividing each bit line pair connected in parallel to both sides of the bit line sense amplifier. A bit line dividing unit for connecting a second bit line group located far away to connect a metal line to a bit line sense amplifier in parallel with the first bit line group; A switch connected to the first bit line group and a predetermined position on the metal line, respectively, and selectively switched according to a bit line separation control signal to selectively connect the first and second bit line groups to a bit line sense amplifier. A divided bit line driving apparatus comprising a portion. The method of claim 1, A split bit line driving device, comprising: a precharge unit connected between each pair of bit lines constituting the first and second bit line groups, and configured to perform a precharge operation by bit line equalization. . The method of claim 2, And the precharge unit comprises a MOS transistor to which a precharge control signal is applied to a gate terminal.