US20040240246A1 - Bi-directional read write data structure and method for memory - Google Patents
Bi-directional read write data structure and method for memory Download PDFInfo
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- US20040240246A1 US20040240246A1 US10/448,776 US44877603A US2004240246A1 US 20040240246 A1 US20040240246 A1 US 20040240246A1 US 44877603 A US44877603 A US 44877603A US 2004240246 A1 US2004240246 A1 US 2004240246A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
Definitions
- the present invention relates to integrated circuit memories, and more particularly to a system and method, in a semiconductor integrated circuit memory, of transferring read and write data signals on a bi-directional primary data line between primary sense amplifiers and secondary sense amplifiers.
- DRAMs Dynamic random access memories
- SOC system-on-a-chip
- Static random access memories have generally faster access times than DRAMs, but are much less dense than DRAMs, because SRAMs require a minimum of six transistors per memory cell, all of which extend in the plane of the integrated circuit chip.
- DRAMs require only one transistor per memory cell, which is oriented vertically in state of the art DRAMs to conserve chip area. It is apparent that in order for DRAMs to compete effectively with fast access time (SRAM), especially in SOC integrated circuits, that DRAMs must provide fast access to stored information, while preserving advantages over SRAM as to density and quantity of storage.
- a content addressable memory can be designed having storage cells composed of one transistor-one capacitor cells similar to that of dynamic random access memories.
- other types of memories have utilized architecture similar to that of DRAMs as a method of reading and writing to storage cells of the memory, namely, in that data signals are transferred to and from storage cells and an external interface of the memory by way of a series of sense amplifiers.
- each bank of the DRAM 10 includes a storage cell array 16 , at least one first sense amplifier block 18 having a plurality of first sense amplifiers, and at least one local buffer block having a plurality of local buffers 20 .
- the purpose of the sense amplifiers of the first sense amplifier block 18 is to transfer signals to and from storage cells of the storage cell array 16 . Transfer of signals between the sense amplifiers of the first sense amplifier block 18 and the block 20 of local buffers is performed as follows.
- the read output signals of a number of sense amplifiers of the first sense amplifier block for example four, or eight sense amplifiers, are multiplexed into a local buffer block 20 , and the write input signals to that same number of sense amplifiers of the first sense amplifier block are demultiplexed out of the local buffer block 20 , respectively.
- the input and output signal lines of the local buffer block 20 are multiplexed onto read primary data lines RPDL, and demultiplexed from complementary write primary data lines WPDLt and WPDLc, respectively.
- these input output buses: the read primary data lines and the write primary data lines run the length of the memory 10 over all of the banks to further circuitry within off-chip driver 14 and write driver 12 which handle the transfer of write data signals to and from the memory 10 .
- the read primary data line (RPDL) is connected to an off-chip driver block 14 , while the write primary data lines (WPDLc and WPDLt) originate from the write driver 12 .
- Operation of the conventional DRAM 10 varies as to whether data is being read from or written to an array of the memory 10 , in that separate read and write buses are used for reading data from, and writing data to the memory 10 .
- read mode a data bit from a storage cell of the array 16 is transferred via a first sense amplifier of FSA block 18 to a local buffer of LBF block 20 . From there, an amplified data signal is transferred onto the RPDL bus, from which the signal is further transferred to an off-chip driver block 14 .
- write mode the data to be written into a storage cell of an array 16 is provided to a write driver 12 of the memory 10 . From there, the data bit is transmitted onto the write primary data lines WPDLt and WPDLc and through the LBF 20 to the first sense amplifier blocks 18 .
- FIG. 2 is a schematic diagram illustrating a conventional arrangement for a local buffer 22 , such as that used in LBF block 20 of DRAM 10 .
- local buffer 22 provides output onto a read primary data line RPDL, which is separate from the lines on which write input is received, WPDLc and WPDLt.
- Local buffer 20 includes a cross-coupled pair of p-type field effect transistors (PFETS) P 3 and P 4 , which act to drive the fan nodes FT and FC to complementary levels.
- PFETS p-type field effect transistors
- Fan nodes FT and FC typically carry data signals which are multiplexed with respect to the storage cell array 16 of the memory 10 , and which are demultiplexed as data signals are transferred to one of several first sense amplifiers with which the particular local buffer 20 is selectively switched.
- a pair of precharge PFETs P 1 and P 2 are provided for precharging the fan nodes FT and FC to the supply voltage between successive read or write cycles.
- a pair of pull-up PFETs P 5 and P 6 are provided to drive the voltage of a respective one of the fan nodes FT and FC up to a supply voltage, according write input received on complementary lines WPDLt and WPDLc.
- a device N 3 is provided for controlling whether a read or write operation is to be performed.
- Specific read circuitry including NOR gates O 1 and O 2 , inverter 11 , and the output driver including PFET P 7 and NFET N 4 , convert complementary read data on fan nodes FT and FC to a single output signal at RDPL.
- Operation of the local buffer 22 proceeds as follows. Prior to a read or a write operation, the fan nodes FT and FC are precharged to a given potential such as a supply voltage VDD. At that time, the primary read data line, RPDL, is tri-stated. The read operation begins such that a data signal from a storage cell of the array 16 appears on a bitline coupled thereto, and a first sense amplifier of FSA block 18 is then activated. The first sense amplifier amplifies a small voltage difference between the bitline and a complementary reference bitline to rail-to-rail complementary signals having a voltage difference of about 1V to 2V, depending upon the technology.
- column select circuitry selects the output of a particular first sense amplifier of a group of typically four or eight first sense amplifiers of FSA block 18 to be transferred to the multiplexed fan nodes FT and FC, through a pair of mulitiplexer switches (not shown).
- a logic level ‘1’ is read from a storage cell of the array 16 .
- the WR/RDN input is low to provide read operation.
- Complementary data signals arriving on a bitline pair BL and/BL from the selected first sense amplifier (not shown) of FSA block 18 are coupled to fan nodes FT and FC, respectively.
- the fan node FC which had been precharged there prior to the supply voltage VDD, is driven to ground.
- the cross-coupled PFETs P 3 and P 4 assist in quickly forcing fan node FC to ground, while fan node FT is forced to the supply voltage VDD. Because WR/RDN is at the low level, it enables NOR gates 01 and 02 .
- the beginning of the write operation is similar to the read operation, in that the fan nodes FT and FC are first precharged to VDD.
- a logic level ‘0’ is written to a storage cell of the memory array 16 of the DRAM 10 .
- the WR/RDN signal is provided at the high level at the gate of NFET NN 3 , and the complementary write primary data lines, WPDLt and WPDLc, are provided at the low ‘0’ level and the high ‘1’ level, respectively, from the write driver block 12 .
- the high level on WPDLc causes NFET N 2 to conduct and node FT is then driven to ground by the series NFETs N 2 and N 3 .
- PFETs P 3 and P 5 conduct and pull the fan node FC up to VDD. These data states of the fan nodes FT and FC are then transferred by multiplexer switches (not shown) to a bitline pair BL and /BL of a first sense amplifier of FSA block 18 for writing to a storage cell of the storage cell array 16 .
- an integrated circuit memory which includes a plurality of primary sense amplifiers coupled to provide read and write access to a multiplicity of storage cells, a plurality of second sense amplifiers, and a plurality of pairs of input/output data lines (IODLs) each coupled to a primary sense amplifier of the plurality of primary sense amplifiers.
- Each IODL pair is adapted to carry first complementary signals representing a storage bit.
- the integrated circuit memory further includes a plurality of pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier of the plurality of second sense amplifiers, and each BPDL pair being adapted to carry second complementary signals representing a storage bit.
- BPDLs bi-directional primary data lines
- a plurality of local buffers are provided, each being responsive to read control input to transfer the first complementary signals carried by the IODLs to second complementary signals carried by the BPDLs, and each being responsive to write control input to transfer the second complementary signals carried by the BPDLs to first complementary signals carried by the IODLs.
- a method for transferring a data bit signal between a primary sense amplifier and a secondary sense amplifier.
- the method includes providing a pair of input/output data lines (IODLs) coupled to a primary sense amplifier for carrying a pair of first complementary data signals.
- the method further includes transferring, in accordance with control input, a data bit signal between the pair of IODLs and a secondary sense amplifier by way of a pair of bi-directional primary data lines (BPDLs) carrying a pair of second complementary data signals.
- IODLs input/output data lines
- BPDLs bi-directional primary data lines
- FIGS. 1A and 1B are block diagrams illustrating a prior art memory configuration.
- FIG. 2 is a schematic diagram illustrating a prior art local buffer, such as that used in the memory configuration shown in FIGS. 1A and 1B.
- FIGS. 3A and 3B are block diagrams illustrating a memory configuration of an embodiment of the invention.
- FIG. 4 is a schematic diagram illustrating an embodiment of the invention.
- FIG. 5 is a schematic diagram illustrating another embodiment of the invention.
- a multi-banked DRAM 30 is provided, which can be either a stand-alone memory, or an embedded DRAM macro within a larger chip.
- the multi-banked DRAM 30 includes a plurality of banks BANK ⁇ 0> through BANK ⁇ 15>, and a plurality of second sense amplifiers 32 connected thereto, which replace the write driver 12 , and off-chip driver 14 of the conventional DRAM shown in FIGS. 1A and 1B.
- FIG. 3A the multi-banked DRAM 30 includes a plurality of banks BANK ⁇ 0> through BANK ⁇ 15>, and a plurality of second sense amplifiers 32 connected thereto, which replace the write driver 12 , and off-chip driver 14 of the conventional DRAM shown in FIGS. 1A and 1B.
- each bank of the DRAM 30 includes a storage cell array 36 , at least one primary sense amplifier block 38 having a plurality of primary sense amplifiers, and at least one local buffer block 40 having a plurality of local buffers.
- the purpose of the primary sense amplifiers of the PSA block 38 is to transfer signals to and from storage cells of the storage cell array 36 .
- Transfer of signals between primary sense amplifiers of the PSA 38 and local buffers of LBF block 40 is arranged as follows, as further shown in FIG. 4.
- the read data output signals on preferably a plurality of complementary pairs of bitlines, e.g. bitline pair BL 1 and /BL 1 of a number of sense amplifiers SA 1 , SA 2 , . . . SAn of PSA block 38 , for example two, four, or eight sense amplifiers, are multiplexed by multiplexer (MUX) switches 48 and 50 onto complementary fan nodes FT and FC, as input to a local buffer block 40 .
- a selection input SEL is provided, ultimately originating from column select input (CSL), to select a particular bitline pair, e.g.
- write data input signals to the same primary sense amplifiers of the PSA block 38 are demultiplexed a selected one of the complementary bitline pairs by the same MUX switches 48 and 50 , from the multiplexed data carried by the fan nodes FT and FC of the local buffer block 40 .
- the write data input signals and the read data output signals for only a signal pair of bitlines are transferred by way of fan nodes FT and FC to and from a primary sense amplifier, respectively, without the multiplexing and demultiplexing of bitline signals.
- the fan nodes FT and FC function as bi-directional input output data lines (IODLs) for transferring data to and from a primary sense amplifier.
- IODLs bi-directional input output data lines
- bi-directional primary data lines BPDLt and BLDLc connect a local buffer from LBF block 40 to a second sense amplifier of SSA block 32 .
- the complementary write primary data lines WPDLt and WPDLt and the read primary data line, RPDL have been combined and reduced to a pair of bi-directional data lines.
- a DRAM 30 which already provides 256 input output (IO) lines, 512 metal lines, i.e. two lines ⁇ 256 IO lines are thus eliminated from the memory.
- the resulting savings in chip area can be used to broaden the remaining BPDLs, thereby improving speed of both read and write access to the memory, or can be used to strengthen the power grid over the memory array 36 , which contributes to performance.
- a preferred embodiment of a local buffer 42 of LBF block 40 is illustrated schematically.
- Local buffer 42 operates bi-directionally, but contains fewer transistors than the prior art local buffer 22 shown and described above relative to FIG. 2, as there are no NOR gates O 1 , O 2 , separate read driver transistor pair (P 7 and N 4 ), or inverter 11 in this embodiment.
- a local buffer 42 includes two circuits 44 and 46 , each of which transfers read and write data signals bi-directionally between a fan node FT or FC in each case and the corresponding one of complementary bi-directional primary data lines BPDLt and BPDLc.
- read and precharge timing control is provided through a signal RD/PC input to the gate of NFET N 1 .
- the fan node FT is precharged to ground by NFET N 1 which turns on.
- RD/PC is low, fan node FT is allowed to float to the potential of bitline being sensed by the primary sense amplifier of PSA block 18 connected thereto.
- Fan nodes FT and FC are coupled in inverted relation to the bi-directional primary data lines BPDLc and BPDLt, respectively.
- a read data output signal appearing on fan node FT is inverted when transferred to BPDLc
- a write data input signal on BPDLc is inverted when transferred onto fan node FT.
- a read data output signal appearing on the complementary fan node FC is inverted when transferred to BPDLt
- a write data input signal on BPDLt is inverted when transferred onto FC.
- the particular circuitry of local buffer 42 is provided as follows. The initial condition for read operation provides that BPDLc and BPDLt are precharged high.
- a high signal appearing on FT is inverted onto BPDLc by NFET N 2 .
- the initial condition for a write operation provides that FT and FC are precharged low.
- a write signal WRTN at the gate of P 3 a low signal appearing on BPDLc is inverted onto FT by PFET P 1 which is connected through PFET P 3 to a voltage supply VDD to pull up the voltage on FT.
- the circuit 46 provided for transferring signals between FC and BPDLt are the same as that of the circuit 44 .
- a pair of PFETs P 5 and P 6 are provided for precharging the lines BPDLc and BPDLt, respectively.
- the PFETs are controlled by a switching signal PCN input to their gates.
- the precharge devices P 5 and P 6 have gates that are held at ground.
- signal swing on the complementary lines BPDLt and BPDLc is limited, thus shortening the time for the complementary signals thereon to reach their final levels. Amplification of the complementary signals BPDLt and BPDLc to rail-to-rail signals would then be performed by SSA 33 , By limiting signal swing in such manner, the performance and latency of the DRAM 30 can be improved.
- a storage cell of the memory array 36 is read out of the memory.
- a read operation begins with the fan nodes FT and FC being precharged to ground by a high level input to N 1 and N 3 .
- the bi-directional primary data lines BPDLt and BPDLc are precharged to VDD by low level inputs to PFETs P 5 and P 6 .
- the fan node FT rises to the high level voltage of logic level ‘1’.
- the high level causes transistor N 2 to conduct, thereby discharging the line BPDLc to ground.
- the fan node FC remains at ground, because it provides a complementary signal to the high level signal on FT. As a result, NFET N 4 does not conduct and the line BPDLt remains high, at a logic level ‘1’, indicating that a ‘1’ is read from the storage cell of the array 36 .
- the fan node FC rises to the high level of a logic level ‘1’.
- the high level causes transistor N 4 to conduct which discharges the line BPDLt to ground.
- the fan node FT remains at ground.
- NFET N 2 does not conduct and the line BPDLc remains high, at a logic level ‘1’, indicating that a ‘0’ is read from the storage cell of the array 36 .
- a write operation is performed.
- the write operation begins with the fan nodes FT and FC being precharged to ground.
- the bi-directional primary data lines BPDLt and BPDLc are precharged to VDD through PFETs P 5 and P 6 .
- the line BPDLc becomes low.
- the write control PFETs P 3 and P 4 are turned on by write control input WRTN.
- the low level on BPDLc causes transistor P 1 to conduct, thereby pulling up the voltage on line FT to the supply voltage VDD, i.e. to logic level ‘1’.
- the line BPDLt remains at a high potential, such that PFET P 2 does not conduct and fan node FC therefore remains at the complementary signal level of ground, i.e. at logic level ‘0’.
- the line BPDLt becomes low, indicating logic level ‘0’.
- the low level on BPDLt causes PFET P 2 to conduct, which then pulls the voltage of fan node FC up to the supply voltage, i.e. to logic level ‘1’.
- the line BPDLc remains at a high potential, such that PFET P 1 does not conduct and fan node FT therefore remains at ground, i.e. at logic level ‘0’.
- the fan nodes FT and FC are precharged to ground and the bi-directional primary data lines BPDLt and BPDLc are precharged to the supply voltage VDD.
- the fan nodes FT and FC are precharged to VDD while the BPDL lines are precharged to ground.
- the circuits shown in FIG. 5 are similar in operation to those of FIG. 4.
- a local buffer 52 of LBF block 40 is illustrated schematically.
- Local buffer 52 operates bi-directionally.
- a local buffer 52 includes two circuits 54 and 56 , each of which transfers read and write data signals bi-directionally between a fan node FT or FC in each case and the corresponding one of complementary bi-directional primary data lines BPDLt and BPDLc.
- read and precharge timing control is provided through a signal RDN/PCN input to the gate of PFET P 1 .
- the fan node FT is precharged to a supply voltage VDD by PFET P 1 which turns on.
- RDN/PCN is high, fan node FT is allowed to float to the potential of bitline being sensed by the primary sense amplifier of PSA block 38 connected thereto.
- fan nodes FT and FC are coupled in inverted relation to the bi-directional primary data lines BPDLc and BPDLt, respectively.
- a read data output signal appearing on fan node FT is inverted when transferred to BPDLc
- a write data input signal on BPDLc is inverted when transferred onto fan node FT.
- a read data output signal appearing on the complementary fan node FC is inverted when transferred to BPDLt
- a write data input signal on BPDLt is inverted when transferred onto FC.
- the particular circuitry of local buffer 52 is provided as follows. The initial condition for read operation provides that BPDLc and BPDLt are precharged low.
- a high level read signal RDN is provided to the gate of P 1 when the local buffer 52 is enabled. At that time, a low signal appearing on FT is inverted onto BPDLc by PFET P 2 .
- the initial condition for a write operation provides that FT and FC are precharged high.
- a write signal WRT at the gate of an NFET N 3
- a high signal appearing on BPDLc is inverted to a low signal appearing on FT by NFET N 1 which is connected through NFET N 3 to pull down the voltage on FT to ground.
- the circuit 56 provided for transferring signals between FC and BPDLt are the same as that of the circuit 44 .
- a pair of NFETs N 5 and N 6 are provided for precharging the lines BPDLc and BPDLt, respectively.
- the NFETs are controlled by a switching signal PC input to their gates.
- the bi-directional primary data lines, BPDLt and BPDLc are permitted to swing from rail to rail (logic level ‘0’ to logic level ‘1’: from ground to VDD) in each read or write access and/or be amplified at the SSA 35 .
- the precharge devices N 5 and N 6 have gates that are held at the supply voltage, e.g. VDD.
- signal swing on the complementary lines BPDLt and BPDLc is limited, thus shortening the time for the complementary signals thereon to reach their final levels.
- Amplification of the complementary signals BPDLt and BPDLc to rail-to-rail signals would then be performed by SSA 35 , By limiting signal swing in such manner, the performance and latency of the DRAM 30 can be improved.
- a storage cell of the memory array 36 (FIG. 3B) is read out of the memory.
- a read operation begins with the fan nodes FT and FC being precharged to the supply voltage VDD by a low level inputs to P 1 and P 2 .
- the bi-directional primary data lines BPDLt and BPDLc are precharged to ground, by high level input to NFETs N 5 and N 6 .
- the fan node FT falls to the low level voltage of logic level ‘0’.
- the low level causes transistor P 2 to conduct, thereby charging the line BPDLc to the supply voltage VDD.
- the fan node FC remains high, because it provides a complementary signal to the low level signal on FT.
- PFET P 4 does not conduct and the line BPDLt remains low, at a logic level ‘0’, indicating that a ‘0’ is read from the storage cell of the array 36 .
- the fan node FT remains at the high level, while the complementary signal on FC falls low.
- the low level on FC causes P 4 to conduct, thereby causing the line BPDLt to be pulled up to the supply voltage VDD. Since FT remains at the high level, PFET P 2 does not conduct and the line BPDLc remains low, at a logic level ‘0’.
- a write operation is performed.
- the write operation begins with the fan nodes FT and FC being precharged high.
- the bi-directional primary data lines BPDLt and BPDLc are precharged to ground through NFETs N 5 and N 6 .
- the complementary line BPDLc rises to high, i.e. to logic level ‘1’.
- the write control NFETs N 3 and N 4 are turned on by write control input WRT.
- the high level on BPDLc causes N 1 to conduct, thereby pulling down the voltage on line FT to ground, i.e. to logic level ‘0’.
- the line BPDLt remains at a low potential, such that NFET N 2 does not conduct and fan node FC therefore remains at the complementary signal level of high, i.e. at logic level ‘1’.
- the line BPDLt rises to high, indicating logic level ‘1’.
- the high level on BPDLt causes N 2 to conduct, which then pulls the voltage of the complementary fan node FC down to ground, i.e. to logic level ‘0’.
- the line BPDLc remains at a low potential, such that NFET N 1 does not conduct and fan node FT therefore remains at the supply voltage VDD,, i.e. at logic level ‘1’.
- a system and method are provided for transferring data signals between a pair of input output lines coupled to a primary sense amplifier and a pair of bi-directional primary data lines coupled to a second sense amplifier. In such manner, the performance of read and write access to the memory can be improved, as well as the density of the integrated circuit can be increased.
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Abstract
Description
- The present invention relates to integrated circuit memories, and more particularly to a system and method, in a semiconductor integrated circuit memory, of transferring read and write data signals on a bi-directional primary data line between primary sense amplifiers and secondary sense amplifiers.
- In a typical integrated circuit memory, the maximum speed of memory access from outside the memory is determined by the performance of the memory array. The speed of access in reading data from the memory cell array and writing data to the array is a limiting factor, both of which are heavily affected by the particular architecture for transferring read and write data signals to and from the memory cell array. Dynamic random access memories (DRAMs) represent a particularly dense form of integrated circuit memory in which a large amount of storage can be provided within a small area of an integrated circuit, making DRAMs an attractive option for low-cost, electronic memory, whether provided in a separate chip, or as an embedded memory of a system-on-a-chip (SOC) integrated circuit.
- Static random access memories (SRAMs) have generally faster access times than DRAMs, but are much less dense than DRAMs, because SRAMs require a minimum of six transistors per memory cell, all of which extend in the plane of the integrated circuit chip. On the other hand, DRAMs require only one transistor per memory cell, which is oriented vertically in state of the art DRAMs to conserve chip area. It is apparent that in order for DRAMs to compete effectively with fast access time (SRAM), especially in SOC integrated circuits, that DRAMs must provide fast access to stored information, while preserving advantages over SRAM as to density and quantity of storage.
- Moreover, recently, there has been a trend towards hybrid types of memory. For example, a content addressable memory can be designed having storage cells composed of one transistor-one capacitor cells similar to that of dynamic random access memories. In addition, other than DRAMs, other types of memories have utilized architecture similar to that of DRAMs as a method of reading and writing to storage cells of the memory, namely, in that data signals are transferred to and from storage cells and an external interface of the memory by way of a series of sense amplifiers.
- Conventional integrated circuit memories utilize separate read and write data buses. These solutions occupy larger silicon area and impede aggressively dense chip/macro targets.
- As illustrated in FIGS. 1A and 1B, a conventional configuration for a multi-banked DRAM is shown, which can be either a stand-alone memory, or an embedded DRAM macro within a larger chip. As shown in FIG. 1A, the multi-banked DRAM includes a plurality of banks BANK<0> through BANK<15>, and a
write driver 12, and an off-chip driver 14. As shown in the inset of FIG. 1B, each bank of theDRAM 10, for example, BANK<xx>, includes astorage cell array 16, at least one firstsense amplifier block 18 having a plurality of first sense amplifiers, and at least one local buffer block having a plurality oflocal buffers 20. The purpose of the sense amplifiers of the firstsense amplifier block 18 is to transfer signals to and from storage cells of thestorage cell array 16. Transfer of signals between the sense amplifiers of the firstsense amplifier block 18 and theblock 20 of local buffers is performed as follows. The read output signals of a number of sense amplifiers of the first sense amplifier block, for example four, or eight sense amplifiers, are multiplexed into alocal buffer block 20, and the write input signals to that same number of sense amplifiers of the first sense amplifier block are demultiplexed out of thelocal buffer block 20, respectively. The input and output signal lines of thelocal buffer block 20, in turn, are multiplexed onto read primary data lines RPDL, and demultiplexed from complementary write primary data lines WPDLt and WPDLc, respectively. As shown in FIG. 1A, these input output buses: the read primary data lines and the write primary data lines run the length of thememory 10 over all of the banks to further circuitry within off-chip driver 14 and writedriver 12 which handle the transfer of write data signals to and from thememory 10. The read primary data line (RPDL) is connected to an off-chip driver block 14, while the write primary data lines (WPDLc and WPDLt) originate from thewrite driver 12. - Operation of the
conventional DRAM 10 varies as to whether data is being read from or written to an array of thememory 10, in that separate read and write buses are used for reading data from, and writing data to thememory 10. In read mode, a data bit from a storage cell of thearray 16 is transferred via a first sense amplifier ofFSA block 18 to a local buffer ofLBF block 20. From there, an amplified data signal is transferred onto the RPDL bus, from which the signal is further transferred to an off-chip driver block 14. In write mode, the data to be written into a storage cell of anarray 16 is provided to awrite driver 12 of thememory 10. From there, the data bit is transmitted onto the write primary data lines WPDLt and WPDLc and through theLBF 20 to the firstsense amplifier blocks 18. - FIG. 2 is a schematic diagram illustrating a conventional arrangement for a local buffer22, such as that used in
LBF block 20 ofDRAM 10. As illustrated, local buffer 22 provides output onto a read primary data line RPDL, which is separate from the lines on which write input is received, WPDLc and WPDLt.Local buffer 20 includes a cross-coupled pair of p-type field effect transistors (PFETS) P3 and P4, which act to drive the fan nodes FT and FC to complementary levels. Fan nodes FT and FC typically carry data signals which are multiplexed with respect to thestorage cell array 16 of thememory 10, and which are demultiplexed as data signals are transferred to one of several first sense amplifiers with which the particularlocal buffer 20 is selectively switched. In addition, a pair of precharge PFETs P1 and P2 are provided for precharging the fan nodes FT and FC to the supply voltage between successive read or write cycles. In addition, a pair of pull-up PFETs P5 and P6 are provided to drive the voltage of a respective one of the fan nodes FT and FC up to a supply voltage, according write input received on complementary lines WPDLt and WPDLc. A device N3 is provided for controlling whether a read or write operation is to be performed. Specific read circuitry including NOR gates O1 and O2, inverter 11, and the output driver including PFET P7 and NFET N4, convert complementary read data on fan nodes FT and FC to a single output signal at RDPL. - Operation of the local buffer22 proceeds as follows. Prior to a read or a write operation, the fan nodes FT and FC are precharged to a given potential such as a supply voltage VDD. At that time, the primary read data line, RPDL, is tri-stated. The read operation begins such that a data signal from a storage cell of the
array 16 appears on a bitline coupled thereto, and a first sense amplifier ofFSA block 18 is then activated. The first sense amplifier amplifies a small voltage difference between the bitline and a complementary reference bitline to rail-to-rail complementary signals having a voltage difference of about 1V to 2V, depending upon the technology. In atypical DRAM 10, column select circuitry then selects the output of a particular first sense amplifier of a group of typically four or eight first sense amplifiers ofFSA block 18 to be transferred to the multiplexed fan nodes FT and FC, through a pair of mulitiplexer switches (not shown). - Further operation then proceeds as follows. In an example, a logic level ‘1’ is read from a storage cell of the
array 16. The WR/RDN input is low to provide read operation. Complementary data signals arriving on a bitline pair BL and/BL from the selected first sense amplifier (not shown) ofFSA block 18 are coupled to fan nodes FT and FC, respectively. Then, the fan node FC, which had been precharged there prior to the supply voltage VDD, is driven to ground. The cross-coupled PFETs P3 and P4 assist in quickly forcing fan node FC to ground, while fan node FT is forced to the supply voltage VDD. Because WR/RDN is at the low level, it enables NORgates - The beginning of the write operation is similar to the read operation, in that the fan nodes FT and FC are first precharged to VDD. In an example, a logic level ‘0’ is written to a storage cell of the
memory array 16 of theDRAM 10. The WR/RDN signal is provided at the high level at the gate of NFET NN3, and the complementary write primary data lines, WPDLt and WPDLc, are provided at the low ‘0’ level and the high ‘1’ level, respectively, from thewrite driver block 12. The high level on WPDLc causes NFET N2 to conduct and node FT is then driven to ground by the series NFETs N2 and N3. At the same time, PFETs P3 and P5 conduct and pull the fan node FC up to VDD. These data states of the fan nodes FT and FC are then transferred by multiplexer switches (not shown) to a bitline pair BL and /BL of a first sense amplifier ofFSA block 18 for writing to a storage cell of thestorage cell array 16. - According to an aspect of the invention, an integrated circuit memory is provided which includes a plurality of primary sense amplifiers coupled to provide read and write access to a multiplicity of storage cells, a plurality of second sense amplifiers, and a plurality of pairs of input/output data lines (IODLs) each coupled to a primary sense amplifier of the plurality of primary sense amplifiers. Each IODL pair is adapted to carry first complementary signals representing a storage bit. The integrated circuit memory further includes a plurality of pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier of the plurality of second sense amplifiers, and each BPDL pair being adapted to carry second complementary signals representing a storage bit.
- According to this aspect of the invention, in the integrated circuit memory, a plurality of local buffers are provided, each being responsive to read control input to transfer the first complementary signals carried by the IODLs to second complementary signals carried by the BPDLs, and each being responsive to write control input to transfer the second complementary signals carried by the BPDLs to first complementary signals carried by the IODLs.
- According to another aspect of the invention, a method is provided for transferring a data bit signal between a primary sense amplifier and a secondary sense amplifier. The method includes providing a pair of input/output data lines (IODLs) coupled to a primary sense amplifier for carrying a pair of first complementary data signals. The method further includes transferring, in accordance with control input, a data bit signal between the pair of IODLs and a secondary sense amplifier by way of a pair of bi-directional primary data lines (BPDLs) carrying a pair of second complementary data signals.
- FIGS. 1A and 1B are block diagrams illustrating a prior art memory configuration.
- FIG. 2 is a schematic diagram illustrating a prior art local buffer, such as that used in the memory configuration shown in FIGS. 1A and 1B.
- FIGS. 3A and 3B are block diagrams illustrating a memory configuration of an embodiment of the invention.
- FIG. 4 is a schematic diagram illustrating an embodiment of the invention.
- FIG. 5 is a schematic diagram illustrating another embodiment of the invention.
- A first circuit embodiment will now be described, with reference to FIGS. 3A and 3B. In this embodiment, a
multi-banked DRAM 30 is provided, which can be either a stand-alone memory, or an embedded DRAM macro within a larger chip. As shown in FIG. 3A, themulti-banked DRAM 30 includes a plurality of banks BANK<0> through BANK<15>, and a plurality ofsecond sense amplifiers 32 connected thereto, which replace thewrite driver 12, and off-chip driver 14 of the conventional DRAM shown in FIGS. 1A and 1B. As shown in the inset of FIG. 3B, each bank of theDRAM 30, for example, BANK<xx>, includes astorage cell array 36, at least one primarysense amplifier block 38 having a plurality of primary sense amplifiers, and at least onelocal buffer block 40 having a plurality of local buffers. The purpose of the primary sense amplifiers of thePSA block 38 is to transfer signals to and from storage cells of thestorage cell array 36. - Transfer of signals between primary sense amplifiers of the
PSA 38 and local buffers ofLBF block 40 is arranged as follows, as further shown in FIG. 4. The read data output signals on preferably a plurality of complementary pairs of bitlines, e.g. bitline pair BL1 and /BL1 of a number of sense amplifiers SA1, SA2, . . . SAn ofPSA block 38, for example two, four, or eight sense amplifiers, are multiplexed by multiplexer (MUX) switches 48 and 50 onto complementary fan nodes FT and FC, as input to alocal buffer block 40. A selection input SEL is provided, ultimately originating from column select input (CSL), to select a particular bitline pair, e.g. BL1 and /BL1 of the plurality of bitline pairs, in multiplexed relation to the fan nodes FT and FC. Similarly, write data input signals to the same primary sense amplifiers of thePSA block 38 are demultiplexed a selected one of the complementary bitline pairs by the same MUX switches 48 and 50, from the multiplexed data carried by the fan nodes FT and FC of thelocal buffer block 40. Alternatively, the write data input signals and the read data output signals for only a signal pair of bitlines are transferred by way of fan nodes FT and FC to and from a primary sense amplifier, respectively, without the multiplexing and demultiplexing of bitline signals. In either case, the fan nodes FT and FC function as bi-directional input output data lines (IODLs) for transferring data to and from a primary sense amplifier. - As further shown in FIG. 3B, bi-directional primary data lines BPDLt and BLDLc connect a local buffer from
LBF block 40 to a second sense amplifier ofSSA block 32. However, unlike the prior art arrangement shown in FIGS. 1B, in this embodiment, the complementary write primary data lines WPDLt and WPDLt and the read primary data line, RPDL, have been combined and reduced to a pair of bi-directional data lines. In aDRAM 30 which already provides 256 input output (IO) lines, 512 metal lines, i.e. two lines×256 IO lines are thus eliminated from the memory. The resulting savings in chip area can be used to broaden the remaining BPDLs, thereby improving speed of both read and write access to the memory, or can be used to strengthen the power grid over thememory array 36, which contributes to performance. - As shown in FIG. 4, a preferred embodiment of a
local buffer 42 ofLBF block 40 is illustrated schematically.Local buffer 42 operates bi-directionally, but contains fewer transistors than the prior art local buffer 22 shown and described above relative to FIG. 2, as there are no NOR gates O1, O2, separate read driver transistor pair (P7 and N4), or inverter 11 in this embodiment. As shown in FIG. 4, alocal buffer 42 includes twocircuits circuit 44, read and precharge timing control is provided through a signal RD/PC input to the gate of NFET N1. When the RD/PC signal is high, the fan node FT is precharged to ground by NFET N1 which turns on. On the other hand, when RD/PC is low, fan node FT is allowed to float to the potential of bitline being sensed by the primary sense amplifier ofPSA block 18 connected thereto. - Fan nodes FT and FC are coupled in inverted relation to the bi-directional primary data lines BPDLc and BPDLt, respectively. Thus, a read data output signal appearing on fan node FT is inverted when transferred to BPDLc, and a write data input signal on BPDLc is inverted when transferred onto fan node FT. Similarly, a read data output signal appearing on the complementary fan node FC is inverted when transferred to BPDLt, and a write data input signal on BPDLt is inverted when transferred onto FC. The particular circuitry of
local buffer 42 is provided as follows. The initial condition for read operation provides that BPDLc and BPDLt are precharged high. When enabled by a read signal RD at the gate of N1, a high signal appearing on FT is inverted onto BPDLc by NFET N2. On the other hand, the initial condition for a write operation provides that FT and FC are precharged low. When enabled by a write signal WRTN at the gate of P3, a low signal appearing on BPDLc is inverted onto FT by PFET P1 which is connected through PFET P3 to a voltage supply VDD to pull up the voltage on FT. Thecircuit 46 provided for transferring signals between FC and BPDLt are the same as that of thecircuit 44. - A pair of PFETs P5 and P6 are provided for precharging the lines BPDLc and BPDLt, respectively. The PFETs are controlled by a switching signal PCN input to their gates. When PFETs P5 and P6 are arranged in such manner, the bi-directional primary data lines, BPDLt and BPDLc, are permitted to swing from rail to rail in each read or write access and/or be amplified at the
SSA 33. In an alternative embodiment, the precharge devices P5 and P6 have gates that are held at ground. In the alternative arrangement, signal swing on the complementary lines BPDLt and BPDLc is limited, thus shortening the time for the complementary signals thereon to reach their final levels. Amplification of the complementary signals BPDLt and BPDLc to rail-to-rail signals would then be performed bySSA 33, By limiting signal swing in such manner, the performance and latency of theDRAM 30 can be improved. - In an example of operation, a storage cell of the
memory array 36 is read out of the memory. With respect tolocal buffer 42 of FIG. 4, a read operation begins with the fan nodes FT and FC being precharged to ground by a high level input to N1 and N3. At about the same time, the bi-directional primary data lines BPDLt and BPDLc are precharged to VDD by low level inputs to PFETs P5 and P6. When a logic level ‘1’ is read from a storage cell of thearray 36, the fan node FT rises to the high level voltage of logic level ‘1’. The high level causes transistor N2 to conduct, thereby discharging the line BPDLc to ground. The fan node FC remains at ground, because it provides a complementary signal to the high level signal on FT. As a result, NFET N4 does not conduct and the line BPDLt remains high, at a logic level ‘1’, indicating that a ‘1’ is read from the storage cell of thearray 36. On the other hand, when a logic level ‘0’ is read from the memory cell, the fan node FC rises to the high level of a logic level ‘1’. The high level causes transistor N4 to conduct which discharges the line BPDLt to ground. The fan node FT remains at ground. As a result, NFET N2 does not conduct and the line BPDLc remains high, at a logic level ‘1’, indicating that a ‘0’ is read from the storage cell of thearray 36. - In another example, a write operation is performed. The write operation begins with the fan nodes FT and FC being precharged to ground. The bi-directional primary data lines BPDLt and BPDLc are precharged to VDD through PFETs P5 and P6. When a logic level ‘1’ is to be written to the
storage array 36, the line BPDLc becomes low. At that time, the write control PFETs P3 and P4 are turned on by write control input WRTN. The low level on BPDLc causes transistor P1 to conduct, thereby pulling up the voltage on line FT to the supply voltage VDD, i.e. to logic level ‘1’. The line BPDLt remains at a high potential, such that PFET P2 does not conduct and fan node FC therefore remains at the complementary signal level of ground, i.e. at logic level ‘0’. On the other hand, when a logic level ‘0’ is to be written to the memory cell, the line BPDLt becomes low, indicating logic level ‘0’. The low level on BPDLt causes PFET P2 to conduct, which then pulls the voltage of fan node FC up to the supply voltage, i.e. to logic level ‘1’. At that time, the line BPDLc remains at a high potential, such that PFET P1 does not conduct and fan node FT therefore remains at ground, i.e. at logic level ‘0’. - In the embodiment described above, the fan nodes FT and FC are precharged to ground and the bi-directional primary data lines BPDLt and BPDLc are precharged to the supply voltage VDD. In another embodiment, as described below relative to FIG. 5, the fan nodes FT and FC are precharged to VDD while the BPDL lines are precharged to ground. The circuits shown in FIG. 5 are similar in operation to those of FIG. 4.
- As shown in FIG. 5, in this embodiment, a local buffer52 of
LBF block 40 is illustrated schematically. Local buffer 52 operates bi-directionally. As shown in FIG. 5, a local buffer 52 includes twocircuits circuit 54, read and precharge timing control is provided through a signal RDN/PCN input to the gate of PFET P1. When the RDN/PCN signal is low, the fan node FT is precharged to a supply voltage VDD by PFET P1 which turns on. On the other hand, when RDN/PCN is high, fan node FT is allowed to float to the potential of bitline being sensed by the primary sense amplifier ofPSA block 38 connected thereto. - As shown in FIG. 5, fan nodes FT and FC are coupled in inverted relation to the bi-directional primary data lines BPDLc and BPDLt, respectively. Thus, a read data output signal appearing on fan node FT is inverted when transferred to BPDLc, and a write data input signal on BPDLc is inverted when transferred onto fan node FT. Similarly, a read data output signal appearing on the complementary fan node FC is inverted when transferred to BPDLt, and a write data input signal on BPDLt is inverted when transferred onto FC. The particular circuitry of local buffer52 is provided as follows. The initial condition for read operation provides that BPDLc and BPDLt are precharged low. A high level read signal RDN is provided to the gate of P1 when the local buffer 52 is enabled. At that time, a low signal appearing on FT is inverted onto BPDLc by PFET P2. On the other hand, the initial condition for a write operation provides that FT and FC are precharged high. When enabled by a write signal WRT at the gate of an NFET N3, a high signal appearing on BPDLc is inverted to a low signal appearing on FT by NFET N1 which is connected through NFET N3 to pull down the voltage on FT to ground. The
circuit 56 provided for transferring signals between FC and BPDLt are the same as that of thecircuit 44. - A pair of NFETs N5 and N6 are provided for precharging the lines BPDLc and BPDLt, respectively. The NFETs are controlled by a switching signal PC input to their gates. When NFETs N5 and N6 are arranged in such manner, the bi-directional primary data lines, BPDLt and BPDLc, are permitted to swing from rail to rail (logic level ‘0’ to logic level ‘1’: from ground to VDD) in each read or write access and/or be amplified at the
SSA 35. In an alternative embodiment, the precharge devices N5 and N6 have gates that are held at the supply voltage, e.g. VDD. In the alternative arrangement, signal swing on the complementary lines BPDLt and BPDLc is limited, thus shortening the time for the complementary signals thereon to reach their final levels. Amplification of the complementary signals BPDLt and BPDLc to rail-to-rail signals would then be performed bySSA 35, By limiting signal swing in such manner, the performance and latency of theDRAM 30 can be improved. - In an example of operation, a storage cell of the memory array36 (FIG. 3B) is read out of the memory. With respect to local buffer 52 of FIG. 5, a read operation begins with the fan nodes FT and FC being precharged to the supply voltage VDD by a low level inputs to P1 and P2. At about the same time, the bi-directional primary data lines BPDLt and BPDLc are precharged to ground, by high level input to NFETs N5 and N6. When a logic level ‘0’ is read from a storage cell of the
array 36, the fan node FT falls to the low level voltage of logic level ‘0’. The low level causes transistor P2 to conduct, thereby charging the line BPDLc to the supply voltage VDD. The fan node FC remains high, because it provides a complementary signal to the low level signal on FT. As a result, PFET P4 does not conduct and the line BPDLt remains low, at a logic level ‘0’, indicating that a ‘0’ is read from the storage cell of thearray 36. On the other hand, when a logic level ‘1’ is read from the memory cell, the fan node FT remains at the high level, while the complementary signal on FC falls low. The low level on FC causes P4 to conduct, thereby causing the line BPDLt to be pulled up to the supply voltage VDD. Since FT remains at the high level, PFET P2 does not conduct and the line BPDLc remains low, at a logic level ‘0’. - In another example, a write operation is performed. The write operation begins with the fan nodes FT and FC being precharged high. The bi-directional primary data lines BPDLt and BPDLc are precharged to ground through NFETs N5 and N6. When a logic level ‘0’ is to be written to the
storage array 36, the complementary line BPDLc rises to high, i.e. to logic level ‘1’. At that time, the write control NFETs N3 and N4 are turned on by write control input WRT. The high level on BPDLc causes N1 to conduct, thereby pulling down the voltage on line FT to ground, i.e. to logic level ‘0’. The line BPDLt remains at a low potential, such that NFET N2 does not conduct and fan node FC therefore remains at the complementary signal level of high, i.e. at logic level ‘1’. On the other hand, when a logic level ‘1’ is written to the memory cell, the line BPDLt rises to high, indicating logic level ‘1’. The high level on BPDLt causes N2 to conduct, which then pulls the voltage of the complementary fan node FC down to ground, i.e. to logic level ‘0’. At that time, the line BPDLc remains at a low potential, such that NFET N1 does not conduct and fan node FT therefore remains at the supply voltage VDD,, i.e. at logic level ‘1’. - As described in the foregoing, a system and method are provided for transferring data signals between a pair of input output lines coupled to a primary sense amplifier and a pair of bi-directional primary data lines coupled to a second sense amplifier. In such manner, the performance of read and write access to the memory can be improved, as well as the density of the integrated circuit can be increased.
- While the invention has been described in accordance with certain preferred embodiments thereof, those skilled in the art will understand the many modifications and enhancements which can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.
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JP2016170303A (en) * | 2015-03-13 | 2016-09-23 | シナプティクス・ジャパン合同会社 | Semiconductor device and electronic equipment |
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