US20090190425A1 - Sense amplifier read line sharing - Google Patents

Sense amplifier read line sharing Download PDF

Info

Publication number
US20090190425A1
US20090190425A1 US12/257,739 US25773908A US2009190425A1 US 20090190425 A1 US20090190425 A1 US 20090190425A1 US 25773908 A US25773908 A US 25773908A US 2009190425 A1 US2009190425 A1 US 2009190425A1
Authority
US
United States
Prior art keywords
read line
sense amplifier
global read
memory
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/257,739
Inventor
Gil I. Winograd
Andreas Gotterba
Esin Terzioglu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novelics Corp
Original Assignee
Novelics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novelics Corp filed Critical Novelics Corp
Priority to US12/257,739 priority Critical patent/US20090190425A1/en
Publication of US20090190425A1 publication Critical patent/US20090190425A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/227—Timing of memory operations based on dummy memory elements or replica circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Definitions

  • the present invention relates to memories and memory devices, and more particularly to memory global read line sharing architectures.
  • a memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) has memory cells arranged in rows and columns. The rows correspond to word lines whereas columns correspond to bit lines. These bit lines travel in the column direction to sense amplifiers that make bit decisions during read operations in an SRAM and during both read and write operations in a DRAM.
  • a memory cell is accessed by asserting the corresponding word line so that an access transistor conducts to couple the memory cell to the corresponding bit line.
  • a sense amplifier may then read the contents of the accessed memory cell by sensing the voltage on the corresponding bit line.
  • a conventional sense amplifier Having sensed the voltage on the bit line, a conventional sense amplifier provides its bit decision on an output line that may be designated as a “global read line.”
  • the global read line couples to input/output (I/O) circuits so that the resulting bit decision may be relayed to external circuits.
  • I/O input/output
  • a sense amplifier Prior to a read operation, it is conventional to pre-charge the global read lines to a power supply voltage VDD. If a sense amplifier determines that the sensed bit line carries a logical one voltage state (assuming a logic high operation), the sense amplifier grounds the pre-charged global read line. Because the global read lines often run the entire column height of the memory, pre-charging and discharging them during read operations consumes substantial power.
  • memory architectures are disclosed in which a plurality of sense amplifiers are multiplexed with regard to a single global read line.
  • the global read line couples between the shared sense amplifier and a corresponding I/O circuit.
  • a memory includes: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.
  • FIG. 1 illustrates a memory having multiplexed sense amplifiers with respect to a given global read line
  • FIG. 2 is a circuit diagram of the multiplexing of FIG. 1 for an SRAM embodiment
  • FIG. 3 is a circuit diagram of the multiplexing of FIG. 1 for a DRAM embodiment.
  • Memory 100 includes a plurality of bit lines 110 arranged in columns that intersect with a plurality of word lines 115 .
  • the bit lines are pre-charged to a suitable voltage such as one-half a power supply voltage VDD.
  • a selected word line may then be charged to the power supply voltage VDD.
  • the increased word line voltage then turns on access transistors (not illustrated) so that the bit lines couple to memory cells (not illustrated) at the word line/bit line intersections.
  • the bit line voltage will change from the pre-charged state: in an active-high logic operation, the bit line voltage will increase from the pre-charged state if the accessed memory cell is storing a logical one whereas the bit line voltage will decrease from the pre-charged state if the accessed memory cell is storing a logical zero.
  • memory 100 there is one active bit line per sense amplifier.
  • alternative embodiments may have bit line multiplexing with respect to a given sense amplifier as disclosed in commonly-assigned U.S. application Ser. No. 12/018,996, the contents of which are incorporated by reference.
  • each sense amplifier it is conventional for each sense amplifier to couple to a corresponding global read line to provide its bit decision to I/O circuits. The I/O circuits then drive an output line so that the external world may know the results of the read operation.
  • a plurality of sense amplifiers multiplex onto each global read line.
  • this multiplexing is 4:1 such that there are four sense amplifiers per global read line but it will be appreciated that such a multiplexing may be varied either higher or lower from four.
  • a given sense amplifier may be selected from the multiplexed group such that the remaining sense amplifiers do not couple to the shared global read line.
  • Each global read line couples to a corresponding I/O circuit 120 that may latch the bit decision carried by the global read line and drive the bit decision externally from the memory on output lines q. In this fashion, a word may be read from memory 100 over the output lines q such that an i th bit in the word is carried on output line q[i], an (i+1) th bit is carried on output line q[i+1], and so on.
  • memory 100 saves substantial power because fewer global read lines need be charged and discharged. Moreover, memory 100 achieves reduced leakage currents because there is only one pre-charge of the global read line per multiplexed group of sense amplifiers.
  • the multiplexing of the sense amplifiers may be implemented in a number of fashions depending upon the type of memory.
  • the multiplexing of SRAM sense amplifiers is illustrated in FIG. 2 .
  • a pre-charge circuit Prior to a read operation, a pre-charge circuit (not illustrated) pre-charges the global read line to a power supply voltage VDD.
  • a controller 200 decodes an read address to generate an active low sense amplifier selection signal SENX [0:3] to select a particular sense amplifier 101 from the group of multiplexers (this embodiment is similar to that shown in FIG. 1 in that a 4:1 sense amplifier multiplexing occurs with respect to a given global read line 105 ).
  • Each sense amplifier is isolated from ground through an NMOS transistor M 1 .
  • the gate of M 1 is driven by a corresponding NOR gate 205 output signal SEN that represents the logical NOR of the sense amplifier's SENX signal as well as an active low read enable signal Readx.
  • the SEN signal is thus acting as a sense command for the corresponding sense amplifier. Because only one of the SENX signals (for example, SENX[0]) will be pulled low during a read operation, only the corresponding M 1 transistor will conduct, thereby activating the corresponding sense amplifier to perform a sense operation on its accessed bit line (the bit lines of FIG. 1 are not illustrated in FIG. 2 for illustration clarity).
  • an SRAM sense amplifier it is conventional for an SRAM sense amplifier to comprise a comparator that will drive its output signal low if the accessed bit line couples to a logic high memory cell.
  • each sense amplifier's output signal drives a corresponding inverter 210 that in turn drives a corresponding NMOS transistor M 2 that couples between ground and the global read line. Accordingly, if a sense amplifier is sensing a logic high state on its accessed bit line, the corresponding M 2 transistor will conduct, thereby pulling the global read line to ground.
  • numerous alternative SRAM sense amplifier multiplexing embodiments may be implemented.
  • the sense amplifiers could directly couple to ground but be isolated from the power supply voltage VDD through a PMOS transistor that would only conduct if both the corresponding SENX signal and the read enable signal Readx were low.
  • the read enable signal Readx may also be used to open the pass transistors (not illustrated) between the accessed bit lines and the corresponding sense amplifiers. Since a sense command must be generated to fire the sense amplifier after the bit line development in conventional SRAMs, it may be seen that the multiplexing scheme of FIG. 2 is implemented with relatively little overhead—just the provision of however many SENX lines are necessary, depending upon how many sense amplifiers are multiplexed onto a given global read line.
  • each DRAM sense amplifier 101 is isolated from ground by an NMOS transistor M 1 whose gate is controlled by an active high global enable signal (global to both read and write operations).
  • the sense amplifier provides its active low output signal to a NOR gate 300 that also receives an active low output enable signal OEx[i], where i represents the ith DRAM sense amplifier within the multiplexed group.
  • a controller circuit (not illustrated but analogous to the controller of FIG. 2 ) will generate OEx[i] based upon a decoding of a read address. If OEx[i] and the sense amplifier output signal are both low, an output signal from the corresponding NOR gate 300 will go high, thereby causing a pull-down NMOS transistor M 2 to conduct such that the global read line is pulled to ground through M 2 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.

Description

    RELATED APPLICATION
  • This application claims the benefit of U.S. Provisional Application No. 60/982,219, filed Oct. 24, 2007, the contents of which are hereby incorporated by reference.
    • FIELD OF THE INVENTION
  • The present invention relates to memories and memory devices, and more particularly to memory global read line sharing architectures.
    • BACKGROUND OF THE INVENTION
  • A memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) has memory cells arranged in rows and columns. The rows correspond to word lines whereas columns correspond to bit lines. These bit lines travel in the column direction to sense amplifiers that make bit decisions during read operations in an SRAM and during both read and write operations in a DRAM. A memory cell is accessed by asserting the corresponding word line so that an access transistor conducts to couple the memory cell to the corresponding bit line. A sense amplifier may then read the contents of the accessed memory cell by sensing the voltage on the corresponding bit line.
  • Having sensed the voltage on the bit line, a conventional sense amplifier provides its bit decision on an output line that may be designated as a “global read line.” The global read line couples to input/output (I/O) circuits so that the resulting bit decision may be relayed to external circuits. Prior to a read operation, it is conventional to pre-charge the global read lines to a power supply voltage VDD. If a sense amplifier determines that the sensed bit line carries a logical one voltage state (assuming a logic high operation), the sense amplifier grounds the pre-charged global read line. Because the global read lines often run the entire column height of the memory, pre-charging and discharging them during read operations consumes substantial power.
  • Accordingly, there is a need in the art for memories having lower power consumption with regard to their global read lines.
    • SUMMARY OF THE INVENTION
  • To reduce power consumption, memory architectures are disclosed in which a plurality of sense amplifiers are multiplexed with regard to a single global read line. The global read line couples between the shared sense amplifier and a corresponding I/O circuit.
  • In accordance with one aspect of the invention, a memory is thus provided that includes: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.
  • Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
    • BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 illustrates a memory having multiplexed sense amplifiers with respect to a given global read line;
  • FIG. 2 is a circuit diagram of the multiplexing of FIG. 1 for an SRAM embodiment; and
  • FIG. 3 is a circuit diagram of the multiplexing of FIG. 1 for a DRAM embodiment.
    •
  • To allow cross-referencing among the figures, like elements in the figures are provided like reference numerals.
    • DETAILED DESCRIPTION
  • Turning now to FIG. 1, a memory 100 is illustrated in which a plurality of sense amplifiers 101 are multiplexed onto a given global read line 105. Memory 100 includes a plurality of bit lines 110 arranged in columns that intersect with a plurality of word lines 115. To perform a read operation, the bit lines are pre-charged to a suitable voltage such as one-half a power supply voltage VDD. A selected word line may then be charged to the power supply voltage VDD. The increased word line voltage then turns on access transistors (not illustrated) so that the bit lines couple to memory cells (not illustrated) at the word line/bit line intersections. Because of the coupling of the memory cell to the bit line, the bit line voltage will change from the pre-charged state: in an active-high logic operation, the bit line voltage will increase from the pre-charged state if the accessed memory cell is storing a logical one whereas the bit line voltage will decrease from the pre-charged state if the accessed memory cell is storing a logical zero.
  • In memory 100, there is one active bit line per sense amplifier. However, it will be appreciated that alternative embodiments may have bit line multiplexing with respect to a given sense amplifier as disclosed in commonly-assigned U.S. application Ser. No. 12/018,996, the contents of which are incorporated by reference. As discussed in the background section, it is conventional for each sense amplifier to couple to a corresponding global read line to provide its bit decision to I/O circuits. The I/O circuits then drive an output line so that the external world may know the results of the read operation. However, in memory 100 a plurality of sense amplifiers multiplex onto each global read line. In memory 100, this multiplexing is 4:1 such that there are four sense amplifiers per global read line but it will be appreciated that such a multiplexing may be varied either higher or lower from four. As will be explained further herein, a given sense amplifier may be selected from the multiplexed group such that the remaining sense amplifiers do not couple to the shared global read line. Each global read line couples to a corresponding I/O circuit 120 that may latch the bit decision carried by the global read line and drive the bit decision externally from the memory on output lines q. In this fashion, a word may be read from memory 100 over the output lines q such that an ith bit in the word is carried on output line q[i], an (i+1)th bit is carried on output line q[i+1], and so on.
  • As compared to a conventional memory without global read line sharing, memory 100 saves substantial power because fewer global read lines need be charged and discharged. Moreover, memory 100 achieves reduced leakage currents because there is only one pre-charge of the global read line per multiplexed group of sense amplifiers.
  • The multiplexing of the sense amplifiers may be implemented in a number of fashions depending upon the type of memory. For example, the multiplexing of SRAM sense amplifiers is illustrated in FIG. 2. Prior to a read operation, a pre-charge circuit (not illustrated) pre-charges the global read line to a power supply voltage VDD. A controller 200 decodes an read address to generate an active low sense amplifier selection signal SENX [0:3] to select a particular sense amplifier 101 from the group of multiplexers (this embodiment is similar to that shown in FIG. 1 in that a 4:1 sense amplifier multiplexing occurs with respect to a given global read line 105). Each sense amplifier is isolated from ground through an NMOS transistor M1. The gate of M1 is driven by a corresponding NOR gate 205 output signal SEN that represents the logical NOR of the sense amplifier's SENX signal as well as an active low read enable signal Readx. The SEN signal is thus acting as a sense command for the corresponding sense amplifier. Because only one of the SENX signals (for example, SENX[0]) will be pulled low during a read operation, only the corresponding M1 transistor will conduct, thereby activating the corresponding sense amplifier to perform a sense operation on its accessed bit line (the bit lines of FIG. 1 are not illustrated in FIG. 2 for illustration clarity).
  • It is conventional for an SRAM sense amplifier to comprise a comparator that will drive its output signal low if the accessed bit line couples to a logic high memory cell. To pull the global read line low for such a logic-high-storing memory cell, each sense amplifier's output signal drives a corresponding inverter 210 that in turn drives a corresponding NMOS transistor M2 that couples between ground and the global read line. Accordingly, if a sense amplifier is sensing a logic high state on its accessed bit line, the corresponding M2 transistor will conduct, thereby pulling the global read line to ground. It will be appreciated that numerous alternative SRAM sense amplifier multiplexing embodiments may be implemented. For example, rather than activating a selected sense amplifier though a grounding transistor M1, the sense amplifiers could directly couple to ground but be isolated from the power supply voltage VDD through a PMOS transistor that would only conduct if both the corresponding SENX signal and the read enable signal Readx were low.
  • The read enable signal Readx may also be used to open the pass transistors (not illustrated) between the accessed bit lines and the corresponding sense amplifiers. Since a sense command must be generated to fire the sense amplifier after the bit line development in conventional SRAMs, it may be seen that the multiplexing scheme of FIG. 2 is implemented with relatively little overhead—just the provision of however many SENX lines are necessary, depending upon how many sense amplifiers are multiplexed onto a given global read line.
  • Turning now to FIG. 3, the multiplexing of DRAM sense amplifiers is illustrated. For illustration clarity, just a single DRAM sense amplifier 101 is shown from the group that will multiplex onto a given global read line 105. As contrasted with SRAM operation, a DRAM sense amplifier is slower as it must use gain and a regenerative latch function that are not necessary in an SRAM. Thus, each DRAM sense amplifier 101 is isolated from ground by an NMOS transistor M1 whose gate is controlled by an active high global enable signal (global to both read and write operations). The sense amplifier provides its active low output signal to a NOR gate 300 that also receives an active low output enable signal OEx[i], where i represents the ith DRAM sense amplifier within the multiplexed group. Thus a controller circuit (not illustrated but analogous to the controller of FIG. 2) will generate OEx[i] based upon a decoding of a read address. If OEx[i] and the sense amplifier output signal are both low, an output signal from the corresponding NOR gate 300 will go high, thereby causing a pull-down NMOS transistor M2 to conduct such that the global read line is pulled to ground through M2.
  • The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. For example, although the global read line is generally a uni-directional in that the bit decision from the sense amplifier flows through the global read line to the corresponding I/O circuit, the global read line could also be made bi-directional. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.

Claims (1)

1. A memory, comprising:
a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation;
an I/O circuit to receive the global read line; and
a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.
US12/257,739 2007-10-24 2008-10-24 Sense amplifier read line sharing Abandoned US20090190425A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/257,739 US20090190425A1 (en) 2007-10-24 2008-10-24 Sense amplifier read line sharing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98221907P 2007-10-24 2007-10-24
US12/257,739 US20090190425A1 (en) 2007-10-24 2008-10-24 Sense amplifier read line sharing

Publications (1)

Publication Number Publication Date
US20090190425A1 true US20090190425A1 (en) 2009-07-30

Family

ID=40582628

Family Applications (10)

Application Number Title Priority Date Filing Date
US12/031,504 Abandoned US20090109772A1 (en) 2007-10-24 2008-02-14 Ram with independent local clock
US12/108,258 Active US7738314B2 (en) 2007-10-24 2008-04-23 Decoder with memory
US12/108,282 Active US7852688B2 (en) 2007-10-24 2008-04-23 Efficient sense command generation
US12/108,206 Abandoned US20090109778A1 (en) 2007-10-24 2008-04-23 Low-power sense amplifier
US12/258,231 Active US7903497B2 (en) 2007-10-24 2008-10-24 Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
US12/257,739 Abandoned US20090190425A1 (en) 2007-10-24 2008-10-24 Sense amplifier read line sharing
US12/968,261 Abandoned US20110141840A1 (en) 2007-10-24 2010-12-14 Nor-or decoder
US13/295,780 Abandoned US20120235707A1 (en) 2007-10-24 2011-11-14 Nor-or decoder
US13/961,722 Active US8861302B2 (en) 2007-10-24 2013-08-07 NOR-OR decoder
US14/514,175 Active US9214208B2 (en) 2007-10-24 2014-10-14 NOR-OR Decoder

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US12/031,504 Abandoned US20090109772A1 (en) 2007-10-24 2008-02-14 Ram with independent local clock
US12/108,258 Active US7738314B2 (en) 2007-10-24 2008-04-23 Decoder with memory
US12/108,282 Active US7852688B2 (en) 2007-10-24 2008-04-23 Efficient sense command generation
US12/108,206 Abandoned US20090109778A1 (en) 2007-10-24 2008-04-23 Low-power sense amplifier
US12/258,231 Active US7903497B2 (en) 2007-10-24 2008-10-24 Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer

Family Applications After (4)

Application Number Title Priority Date Filing Date
US12/968,261 Abandoned US20110141840A1 (en) 2007-10-24 2010-12-14 Nor-or decoder
US13/295,780 Abandoned US20120235707A1 (en) 2007-10-24 2011-11-14 Nor-or decoder
US13/961,722 Active US8861302B2 (en) 2007-10-24 2013-08-07 NOR-OR decoder
US14/514,175 Active US9214208B2 (en) 2007-10-24 2014-10-14 NOR-OR Decoder

Country Status (1)

Country Link
US (10) US20090109772A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102820052A (en) * 2011-06-09 2012-12-12 台湾积体电路制造股份有限公司 SRAM multiplexing apparatus

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4267002B2 (en) * 2006-06-08 2009-05-27 エルピーダメモリ株式会社 System with controller and memory
US20090085552A1 (en) * 2007-09-29 2009-04-02 Olivier Franza Power management using dynamic embedded power gate domains
US20090109772A1 (en) * 2007-10-24 2009-04-30 Esin Terzioglu Ram with independent local clock
US20090243694A1 (en) * 2008-03-31 2009-10-01 Todd Mellinger Voltage converting driver apparatus
CN102265349B (en) * 2008-11-05 2014-06-18 奈克斯特生物测定学公司 Non-binary decoder architecture and control signal logic for reducing circuit complexity
KR101593602B1 (en) * 2009-01-14 2016-02-15 삼성전자주식회사 Semiconductor memory device
EP2234272A3 (en) * 2009-03-23 2015-09-30 Oticon A/S Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor
US8116139B2 (en) * 2010-01-29 2012-02-14 Sandisk Technologies Inc. Bit line stability detection
US8959291B2 (en) 2010-06-04 2015-02-17 Lsi Corporation Two-port memory capable of simultaneous read and write
US8345497B2 (en) 2010-06-23 2013-01-01 International Business Machines Corporation Internal bypassing of memory array devices
US8345490B2 (en) * 2010-06-23 2013-01-01 International Business Machines Corporation Split voltage level restore and evaluate clock signals for memory address decoding
US8351278B2 (en) 2010-06-23 2013-01-08 International Business Machines Corporation Jam latch for latching memory array output data
US8599642B2 (en) 2010-06-23 2013-12-03 International Business Machines Corporation Port enable signal generation for gating a memory array device output
US8446791B2 (en) * 2010-12-03 2013-05-21 Oracle International Corporation Process tolerant large-swing sense amplfier with latching capability
TWI455148B (en) * 2010-12-13 2014-10-01 Vanguard Int Semiconduct Corp Integrated device for accessing multi-port input read/write event
US8861301B2 (en) * 2012-06-08 2014-10-14 Freescale Semiconductor, Inc. Clocked memory with latching predecoder circuitry
US8743651B2 (en) * 2012-06-08 2014-06-03 Freescale Semiconductor, Inc. Clocked memory with word line activation during a first portion of the clock cycle
US8724423B1 (en) 2012-12-12 2014-05-13 Lsi Corporation Synchronous two-port read, two-port write memory emulator
US8923089B2 (en) 2012-12-21 2014-12-30 Lsi Corporation Single-port read multiple-port write storage device using single-port memory cells
US9318173B2 (en) 2013-07-19 2016-04-19 Micron Technology, Inc. Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
KR102378537B1 (en) * 2015-11-06 2022-03-25 에스케이하이닉스 주식회사 Word line driver for screening gidl, semiconductor memory apparatus and test method using the same
KR20170075431A (en) * 2015-12-23 2017-07-03 에스케이하이닉스 주식회사 Semiconductor memory device
US9865333B2 (en) 2016-04-19 2018-01-09 Stmicroelectronics International N.V. Temperature compensated read assist circuit for a static random access memory (SRAM)
US9742408B1 (en) * 2016-09-23 2017-08-22 International Business Machines Corporation Dynamic decode circuit with active glitch control
US10725782B2 (en) * 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
US10534554B2 (en) 2017-10-13 2020-01-14 Silicon Storage Technology, Inc. Anti-hacking mechanisms for flash memory device
US10374604B1 (en) 2018-08-12 2019-08-06 International Business Machines Corporation Dynamic decode circuit low power application
TWI719684B (en) 2019-10-24 2021-02-21 瑞昱半導體股份有限公司 Communication system and operation method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449202B1 (en) * 2001-08-14 2002-09-10 International Business Machines Corporation DRAM direct sensing scheme

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786277A (en) * 1971-07-22 1974-01-15 Siemens Ag Circuit arrangement of mos transistors operating according to the dynamic principle for decoding the addresses for an mos memory
US4048629A (en) * 1975-09-02 1977-09-13 Motorola, Inc. Low power mos ram address decode circuit
US4011549A (en) * 1975-09-02 1977-03-08 Motorola, Inc. Select line hold down circuit for MOS memory decoder
US4843264A (en) * 1987-11-25 1989-06-27 Visic, Inc. Dynamic sense amplifier for CMOS static RAM
US4878198A (en) * 1988-01-25 1989-10-31 Visic, Incorporated Static ram with common data line equalization
US5291076A (en) * 1992-08-31 1994-03-01 Motorola, Inc. Decoder/comparator and method of operation
US5519872A (en) * 1993-12-30 1996-05-21 Intel Corporation Fast address latch with automatic address incrementing
US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
US5737270A (en) * 1996-07-15 1998-04-07 International Business Machines Corporation Precharged wordline decoder with locally-controlled clock
JP3825862B2 (en) * 1997-02-27 2006-09-27 株式会社ルネサステクノロジ Synchronous dynamic semiconductor memory device
CN1202530C (en) * 1998-04-01 2005-05-18 三菱电机株式会社 Static semiconductor memory device operating at high speed under lower power supply voltage
US6314489B1 (en) * 1998-07-10 2001-11-06 Nortel Networks Limited Methods and systems for storing cell data using a bank of cell buffers
US6172531B1 (en) * 1999-02-16 2001-01-09 International Business Machines Corporation Low power wordline decoder circuit with minimized hold time
GB0000738D0 (en) * 2000-01-13 2000-03-08 Element 14 Inc Decoder circuit
US6181626B1 (en) * 2000-04-03 2001-01-30 Lsi Logic Corporation Self-timing circuit for semiconductor memory devices
US6483754B1 (en) * 2001-05-16 2002-11-19 Lsi Logic Corporation Self-time scheme to reduce cycle time for memories
US6538932B2 (en) * 2001-06-13 2003-03-25 International Business Machines Corporation Timing circuit and method for a compilable DRAM
KR100454259B1 (en) * 2001-11-02 2004-10-26 주식회사 하이닉스반도체 Semiconductor Memor Device having a Monitoring Circuit
US6728130B1 (en) * 2002-10-22 2004-04-27 Broadcom Corporation Very dense SRAM circuits
JP2004199759A (en) * 2002-12-17 2004-07-15 Fujitsu Ltd Semiconductor storage device
US6963517B2 (en) * 2003-08-11 2005-11-08 Chao-Wu Chen Parallel asynchronous propagation pipeline structure to access multiple memory arrays
US7170320B2 (en) * 2005-02-04 2007-01-30 International Business Machines Corporation Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering
US7362640B2 (en) * 2005-12-29 2008-04-22 Mosaid Technologies Incorporated Apparatus and method for self-refreshing dynamic random access memory cells
US7339842B1 (en) * 2006-08-16 2008-03-04 Arm Limited Timing control for sense amplifiers in a memory circuit
US7518947B2 (en) * 2006-09-28 2009-04-14 Freescale Semiconductor, Inc. Self-timed memory having common timing control circuit and method therefor
US7349288B1 (en) * 2006-10-05 2008-03-25 International Business Machines Corporation Ultra high-speed Nor-type LSDL/Domino combined address decoder
US7848173B1 (en) * 2006-10-17 2010-12-07 Marvell International Ltd. Address decoder
JP2008135116A (en) * 2006-11-28 2008-06-12 Toshiba Corp Semiconductor memory device
US20090109772A1 (en) * 2007-10-24 2009-04-30 Esin Terzioglu Ram with independent local clock

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449202B1 (en) * 2001-08-14 2002-09-10 International Business Machines Corporation DRAM direct sensing scheme

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102820052A (en) * 2011-06-09 2012-12-12 台湾积体电路制造股份有限公司 SRAM multiplexing apparatus
US8750053B2 (en) 2011-06-09 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM multiplexing apparatus
US9208857B2 (en) 2011-06-09 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM multiplexing apparatus

Also Published As

Publication number Publication date
US20090109766A1 (en) 2009-04-30
US20090109778A1 (en) 2009-04-30
US9214208B2 (en) 2015-12-15
US20110141840A1 (en) 2011-06-16
US7852688B2 (en) 2010-12-14
US20090109789A1 (en) 2009-04-30
US7903497B2 (en) 2011-03-08
US7738314B2 (en) 2010-06-15
US8861302B2 (en) 2014-10-14
US20090109772A1 (en) 2009-04-30
US20090190389A1 (en) 2009-07-30
US20150162062A1 (en) 2015-06-11
US20120235707A1 (en) 2012-09-20
US20130321028A1 (en) 2013-12-05

Similar Documents

Publication Publication Date Title
US20090190425A1 (en) Sense amplifier read line sharing
US10789998B2 (en) Memory bank signal coupling buffer and method
US9171634B2 (en) Memory device and method of controlling leakage current within such a memory device
US6711051B1 (en) Static RAM architecture with bit line partitioning
US8325549B2 (en) Global bit select circuit interface with simplified write bit line precharging
US7643357B2 (en) System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture
US7336546B2 (en) Global bit select circuit with dual read and write bit line pairs
US7379347B1 (en) Memory device and method for performing write operations in such a memory device
US7286425B2 (en) System and method for capacitive mis-match bit-line sensing
JPH09190695A (en) Semiconductor memory having multi-bank structure
US9536597B2 (en) Low-power SRAM cells
US10593395B2 (en) Multiple data rate memory
US8325543B2 (en) Global bit select circuit interface with false write through blocking
US8179708B2 (en) Anti-cross-talk circuitry for ROM arrays
US20200327931A1 (en) A memory unit
US6940743B2 (en) Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data
US7804725B2 (en) Write driving circuit and semiconductor memory apparatus using the same
US6816397B1 (en) Bi-directional read write data structure and method for memory
US6434079B2 (en) Semiconductor memory device for distributing load of input and output lines
US6226216B1 (en) Sectional column activated memory
US7286383B1 (en) Bit line sharing and word line load reduction for low AC power SRAM architecture
US11462263B2 (en) Burst-mode memory with column multiplexer
JP2001014852A (en) Semiconductor storage
KR20230020429A (en) Precharge circuit for memory
US6320807B1 (en) Apparatus and method for a high-speed memory

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION