TWI455148B - Integrated device for accessing multi-port input read/write event - Google Patents

Integrated device for accessing multi-port input read/write event Download PDF

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TWI455148B
TWI455148B TW099143442A TW99143442A TWI455148B TW I455148 B TWI455148 B TW I455148B TW 099143442 A TW099143442 A TW 099143442A TW 99143442 A TW99143442 A TW 99143442A TW I455148 B TWI455148 B TW I455148B
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event
read
write
sram
input
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TW099143442A
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TW201225104A (en
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Jui Lung Chen
Tien Hui Huang
Chieh Yao Chuang
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Vanguard Int Semiconduct Corp
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Description

用以存取多埠輸入讀寫事件的積體裝置Integrated device for accessing multiple input and read and write events

本發明係有關於一種積體裝置,且特別有關於一種使用單埠靜態隨機存取記憶體(Static Random Access Memory,SRAM)來存取多埠輸入讀寫事件的積體裝置。The present invention relates to an integrated device, and more particularly to an integrated device for accessing multiple input and write events using a static random access memory (SRAM).

靜態隨機存取記憶體(Static Random Access Memory,SRAM)因具有讀寫速度快、不用進行刷新動作、增加CPU、GPU處理效率、良好的抗雜訊能力等優點,因此常做為快取記憶體使用。隨著積體電路製程的進步及材料科學的發展,積體電路的操作頻率及運算能力快速地提昇,適當地增加SRAM有助於減少CPU存取資料的次數,使得系統產生熱量減少。Static Random Access Memory (SRAM) is often used as a cache memory because of its high read/write speed, no need to perform refresh operations, increased CPU and GPU processing efficiency, and good anti-noise capability. use. With the advancement of the integrated circuit process and the development of materials science, the operating frequency and computing power of the integrated circuit are rapidly increased. Appropriately increasing the SRAM helps to reduce the number of times the CPU accesses the data, and the system generates heat reduction.

如第1圖所示,現有的系統晶片(System on a chip)或顯示器的驅動IC常使用雙埠SRAM 2以供處理器,例如微控制器(Microcontroller Unit)1來進行雙埠資料的讀寫。而因為雙埠SRAM字元線數與位元線數皆是單埠SRAM的兩倍,電晶體數目也較單埠SRAM要多,因此有著電路複雜龐大且佔有面積大的缺點。As shown in FIG. 1, a conventional system on a chip or a display driver IC often uses a dual-slice SRAM 2 for a processor, such as a microcontroller (Microcontroller Unit) 1, to perform reading and writing of data. . Because the number of double-stroke SRAM word lines and the number of bit lines are twice that of SRAM, and the number of transistors is more than that of SRAM, it has the disadvantages of complicated circuit and large occupied area.

因此也有一種作法如第2圖所示,是使用單埠SRAM 3再加上一時序控制電路4來提供微控制器1進行雙埠資料的讀寫。時序控制電路4會將A埠或B埠兩者當中先到達的讀寫事件輸出給單埠SRAM 3執行讀寫,並暫停後到達的另一讀寫事件的輸入,直到單埠SRAM 3完成先到達的讀寫事件後,才使後到達的讀寫事件輸入並且輸出至單埠 SRAM 3。如此一來,時序控制電路4的時序必須與單埠SRAM 3的工作速度同步,微控制器1則必須等待單埠SRAM 3完成一個讀寫事件後,才能將下一個讀寫事件輸入時序控制電路4,最後造成系統整體的速度下降。Therefore, there is also a method as shown in Fig. 2, which uses the 單埠SRAM 3 plus a timing control circuit 4 to provide the microcontroller 1 for reading and writing data. The timing control circuit 4 outputs the read/write event that arrives first among A埠 or B埠 to the SRAM 3 to perform reading and writing, and suspends the input of another read/write event that arrives until the SRAM 3 is completed. After the read and write events are reached, the post-arrival read and write events are input and output to 單埠 SRAM 3. In this way, the timing of the timing control circuit 4 must be synchronized with the operating speed of the 單埠SRAM 3, and the microcontroller 1 must wait for the SRAM 3 to complete a read/write event before inputting the next read/write event into the timing control circuit. 4, and finally caused the overall speed of the system to decline.

如上所述,傳統上使用雙埠SRAM會造成的佔有面積過大,而使用單埠SRAM與時序控制電路則會造成的系統速度下降。As mentioned above, the traditional use of double-turn SRAM will result in an excessively large footprint, while the use of 單埠SRAM and timing control circuitry will result in a system speed drop.

有鑑於上述問題,本發明係提供一種用以存取多埠輸入讀寫事件的積體裝置,包括:一單埠SRAM;以及一事件佇列,連接至該單埠SRAM,具有複數個輸入埠及複數個串聯的事件儲存器,該等事件儲存器分別存放透過該等輸入埠而接收之對該單埠SRAM的一讀寫事件。In view of the above problems, the present invention provides an integrated device for accessing multiple input and write events, including: a SRAM; and an event queue connected to the SRAM having a plurality of inputs埠And a plurality of serial event storages for storing a read/write event for the SRAM received through the input ports.

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該事件佇列更具有一事件執行單元,連接至該等複數個串聯的事件儲存器與該單埠SRAM之間,根據該單埠SRAM的執行速度,控制該等事件儲存器所存放的該讀寫事件的資料移動至該單埠SRAM。In the integrated device for accessing a plurality of input and read and write events according to the present invention, the event queue further has an event execution unit connected between the plurality of serially connected event memories and the top SRAM. According to the execution speed of the 單埠SRAM, the data of the read/write event stored in the event storage is controlled to move to the 單埠SRAM.

具體而言,該事件執行單元在該單埠SRAM完成一讀寫事件時,會通知該事件執行單元前一級的該事件儲存器輸出所存放的下一個要執行的讀寫事件給該事件執行單元。Specifically, the event execution unit notifies the event execution unit of the previous stage of the event execution unit to output the next read and write event to be executed to the event execution unit when the read/write event is completed by the event SRAM. .

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該等複數個串聯的事件儲存器中非第一級的事件儲存器的其中一者,若沒有存放一讀寫事件而具有空位,會通 知前一級的事件儲存器輸出所存放的一讀寫事件給該非第一級的事件儲存器的其中一者。In an integrated device for accessing a plurality of input and read and write events according to the present invention, one of the plurality of event storages of the plurality of serially connected event storages does not store a read/write event With vacancies, it will pass The event storage of the previous stage outputs a read and write event stored to one of the non-first level event stores.

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該事件佇列更具有一事件分配器,具有該等複數個輸入埠用以輸入該等複數個讀寫事件;及一輸出埠,依序輸出該等複數個讀寫事件給該等複數個串聯的事件儲存器;In the integrated device for accessing a plurality of input and write events according to the present invention, the event queue further has an event dispatcher having the plurality of inputs for inputting the plurality of read and write events; An output buffer sequentially outputs the plurality of read and write events to the plurality of serial event storages;

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該事件佇列更具有一事件觸發器,根據該讀寫事件來觸發該事件分配器中可先輸入的該輸入埠。In the integrated device for accessing a plurality of input and write events according to the present invention, the event queue further has an event trigger for triggering the input that can be input first in the event dispatcher according to the read/write event. .

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該事件分配器更設有一優先權處理邏輯電路,用以設定優先執行的讀寫事件。In the integrated device for accessing a plurality of input and read and write events according to the present invention, the event dispatcher further includes a priority processing logic circuit for setting a read/write event that is preferentially executed.

在根據本發明用以存取多埠輸入讀寫事件的積體裝置中,該事件執行單元更可以控制一輸出分配器,決定該單埠SRAM的一輸出會透過該輸出分配器的複數輸出埠中的一輸出埠來輸出。In the integrated device for accessing a plurality of input and write events according to the present invention, the event execution unit further controls an output distributor to determine that an output of the UI SRAM is transmitted through the complex output of the output distributor. An output in the output is output.

如上所述,本發明提供一種由單埠SRAM與事件佇列的架構,同時解決了使用雙埠SRAM的大面積問題,以及使用單埠SRAM與時序控制電路的系統速度下降的問題。As described above, the present invention provides an architecture consisting of a 單埠SRAM and an event queue, while solving the problem of large area using a double 埠SRAM and a system speed reduction using a 單埠SRAM and a timing control circuit.

為使本發明之上述及其他目的、特徵和優點能更明顯易懂,下文特舉一具體之實施例,並配合所附圖式第做詳細說明。The above and other objects, features and advantages of the present invention will become more <

第3圖係顯示本發明使用單埠SRAM與事件佇列供微控制器進行資料讀寫的架構。如第3圖所示,單埠SRAM 3 與微控制器1之間具有一事件佇列5,取代習知技術的時序控制電路4。Figure 3 shows the architecture of the present invention using a 單埠SRAM and event queue for the microcontroller to read and write data. As shown in Figure 3, 單埠SRAM 3 There is an event queue 5 between the microcontroller 1 and the timing control circuit 4 of the prior art.

第4圖係顯示本發明的事件佇列5的詳細架構。如第4圖所示,事件佇列5具有一個事件分配器51、一個事件觸發器52、複數個事件儲存器53a、53b(第4圖以兩個為例)、以及一個事件執行單元54。一個讀寫事件會依序經由事件分配器51、事件儲存器53a、事件儲存器53b、事件執行單元54後到達單埠SRAM 3。Figure 4 is a diagram showing the detailed architecture of the event queue 5 of the present invention. As shown in FIG. 4, the event queue 5 has an event dispatcher 51, an event trigger 52, a plurality of event stores 53a, 53b (four in the case of FIG. 4), and an event execution unit 54. A read/write event will arrive at the SRAM 3 via the event dispatcher 51, the event store 53a, the event store 53b, and the event execution unit 54 in sequence.

事件分配器51包括兩個輸入埠DIN A、DIN B。而事件觸發器52包括兩個輸入控制端CTL A、CTL B,會根據讀寫事件來觸發事件分配器51的哪一個輸入埠可先行輸入讀寫事件。因此事件分配器51會依序將兩個輸入埠DIN A、DIN B的讀寫事件輸出至事件儲存器53a。The event distributor 51 comprises two inputs 埠 DIN A, DIN B. The event trigger 52 includes two input control terminals CTL A, CTL B, which triggers the input of the event dispatcher 51 according to the read/write event, and can input the read/write event first. Therefore, the event dispatcher 51 sequentially outputs the read and write events of the two inputs 埠 DIN A, DIN B to the event storage 53a.

事件儲存器53a可存放一個讀寫事件,包括一移位端shift及一空位端empty(未圖示),並且更包括一記憶單元(未圖示)可以決定此事件儲存器53a是否具有空位,如果有空位,則允許讀寫事件進入,並將事件儲存器53a的輸入埠關閉,到下一級的事件儲存器53b有空位時,才將讀寫事件輸入下一級的事件儲存器53b並設定自己具有空位,打開事件儲存器53a的輸入埠允許新讀寫事件輸入。事件儲存器53b的構造及功能皆與事件儲存器53a相同,在此不重複說明。The event storage 53a can store a read/write event, including a shift end shift and a vacant end empty (not shown), and further includes a memory unit (not shown) to determine whether the event storage 53a has a vacancy. If there is a space, the read/write event is allowed to enter, and the input port of the event store 53a is closed. When the event store 53b of the next stage has a space, the read/write event is input to the event store 53b of the next stage and the user is set. With a vacancy, the input to open event store 53a allows for new read and write event inputs. The structure and function of the event storage 53b are the same as those of the event storage 53a, and the description thereof will not be repeated.

因此具體而言,當事件分配器51輸出的一個讀寫事件輸入事件儲存器53a時,若事件儲存器53b沒有存放讀寫事件而具有空位的情況下,事件儲存器53b會透過空位端 empty輸出信號(例如,高位準信號)至事件儲存器53a的移位端shift,通知事件儲存器53a將輸入的讀寫事件移動至事件儲存器53b;若事件儲存器53b存放有讀寫事件而不具有空位的情況下,事件儲存器53b會透過空位端empty輸出信號(例如,低位準信號)至事件儲存器53a的移位端shift,通知事件儲存器53a先存放輸入的讀寫事件。而事件儲存器53b所輸出的讀寫事件會輸入事件執行單元54,輸出後事件儲存器53b即具有空位。Therefore, in particular, when a read/write event output from the event dispatcher 51 is input to the event store 53a, if the event store 53b does not store a read/write event and has a vacancy, the event store 53b passes through the vacancy side. The empty output signal (for example, a high level signal) to the shift terminal shift of the event storage 53a notifies the event storage 53a to move the input read/write event to the event storage 53b; if the event storage 53b stores the read/write event In the case where there is no vacancy, the event storage 53b transmits a signal (for example, a low level signal) to the shift terminal shift of the event storage 53a through the empty end, and notifies the event storage 53a to store the input read/write event. The read/write event output by the event storage 53b is input to the event execution unit 54, and the output event storage 53b has a vacancy.

事件執行單元54包括一空位端empty、一輸出控制端output control、一執行端exec。事件執行單元54將由事件儲存器53b輸入的讀寫事件輸出給單埠SRAM 3的輸入埠DIN,並輸出一控制信號至單埠SRAM 3的控制端CTL來執行讀寫。其中事件執行單元54會根據單埠SRAM 3的執行速度來控制前一級的事件儲存器53b是否進行資料移動。具體來說,當單埠SRAM 3的動作端ACT告知單埠SRAM 3的執行端exec單埠SRAM 3讀寫動作完成時,事件執行單元54便會透過空位端empty輸出信號(例如,高位準信號)至事件儲存器53b的移位端shift,通知事件儲存器53b將輸入的讀寫事件移動至事件執行單元54。而事件執行單元54更有控制一輸出分配器6輸出的功能,事件執行單元54透過輸出控制端output control輸出控制信號至輸出分配器6的輸出控制端output control,決定單埠SRAM 3的輸出端output輸出的信號進入輸出分配器6的輸出端output後會由兩個輸出埠中的哪一個輸出埠來輸出。The event execution unit 54 includes a slot end empty, an output control end output control, and an execution end exec. The event execution unit 54 outputs the read/write event input from the event storage 53b to the input 埠DIN of the 單埠SRAM 3, and outputs a control signal to the control terminal CTL of the 單埠SRAM 3 to perform reading and writing. The event execution unit 54 controls whether the event storage 53b of the previous stage performs data movement according to the execution speed of the 單埠SRAM 3. Specifically, when the action terminal ACT of the 單埠SRAM 3 informs the execution end of the 單埠SRAM 3 that the read and write operations of the exec 單埠SRAM 3 are completed, the event execution unit 54 outputs a signal through the empty terminal (for example, a high level signal). ) to the shift terminal shift of the event storage 53b, the notification event storage 53b moves the input read/write event to the event execution unit 54. The event execution unit 54 further has a function of controlling the output of the output distributor 6. The event execution unit 54 outputs an output control signal to the output control terminal output control of the output distributor 6 through the output control terminal to determine the output of the SRAM 3. The output signal of the output enters the output of the output distributor 6 and is output by which of the two output ports.

藉由上述架構,當多埠的讀寫事件輸入事件佇列5時,讀寫事件會往串聯的事件儲存器53a、53b存放,因此只要有一個事件儲存器53a(或53b)具有空位,微控制器1就可將雙埠輸入的讀寫事件全部輸入事件佇列5中,而不需要停下來等待單埠SRAM 3完成讀寫動作。系統處理速度也因此可得到提昇。With the above architecture, when a plurality of read and write events are input to the event queue 5, the read and write events are stored in the event storages 53a, 53b connected in series, so that only one event storage 53a (or 53b) has a space, micro The controller 1 can input all the read and write events of the double input into the event queue 5 without stopping to wait for the SRAM 3 to complete the read and write operations. The system processing speed can therefore be improved.

再者就佔有面積而言,使用單埠SRAM 3的佔有面積大約是雙埠SRAM 2的佔有面積的70%左右,而使用事件佇列5僅增加10%左右的面積,因此本發明使用單埠SRAM 3與事件佇列5比起傳統上使用雙埠SRAM 2有著面積減小的優點。Further, in terms of the occupied area, the occupied area of the 單埠SRAM 3 is about 70% of the occupied area of the double 埠SRAM 2, and the use event 伫5 is only increased by about 10%, so the present invention uses 單埠The SRAM 3 has the advantage of having an area reduction compared to the event queue 5 conventionally using the double-turn SRAM 2.

本發明除了可使用單埠SRAM與事件佇列以事件驅動方式來模擬雙埠存取SRAM外,也可增加事件佇列中的事件儲存器數目來模擬多埠存取的檔案暫存器(file register)。再者本發明也可在事件分配器加上一優先權處理邏輯電路,以便設定不能等待的讀寫事件優先執行。因此雖已詳細說明較佳的實施例,但以上實施例僅為本發明的範例而非限定於此,本發明實際的範圍將由申請專利範圍來界定。In addition to using the 單埠SRAM and event queues to simulate dual-access SRAM in an event-driven manner, the present invention can also increase the number of event stores in the event queue to simulate a multi-access file register (file). Register). Furthermore, the present invention can also add a priority processing logic circuit to the event dispatcher to set the read and write events that cannot be waited for. Having thus described the preferred embodiments, the above embodiments are merely illustrative of the invention, and the scope of the invention is defined by the scope of the claims.

1‧‧‧微控制器1‧‧‧Microcontroller

2‧‧‧雙埠SRAM2‧‧‧Double SRAM

3‧‧‧單埠SRAM3‧‧‧單埠SRAM

4‧‧‧時序控制電路4‧‧‧Sequence Control Circuit

5‧‧‧事件佇列5‧‧‧ event queue

51‧‧‧事件分配器51‧‧‧Event distributor

52‧‧‧事件觸發器52‧‧‧ event trigger

53a、53b‧‧‧事件儲存器53a, 53b‧‧‧ event storage

54‧‧‧事件執行單元54‧‧‧Event Execution Unit

6‧‧‧輸出分配器6‧‧‧Output distributor

DIN、DIN A、DINB‧‧‧輸入埠DIN, DIN A, DINB‧‧‧ input埠

CTL、CTL A、CTL B‧‧‧控制端CTL, CTL A, CTL B‧‧‧ control terminal

shift‧‧‧移位端Shift‧‧‧ shifting end

empty‧‧‧空位端Empty‧‧‧vacancy

exec‧‧‧執行端Exec‧‧‧executive

output‧‧‧輸出端Output‧‧‧output

output control‧‧‧輸出控制端Output control‧‧‧output control terminal

ACT‧‧‧動作端ACT‧‧‧ action side

CTL‧‧‧控制端CTL‧‧‧ control terminal

第1圖係顯示傳統上使用雙埠SRAM供微控制器進行資料讀寫的架構。Figure 1 shows the architecture that traditionally uses dual-turn SRAMs for microcontrollers to read and write data.

第2圖係顯示傳統上使用單埠SRAM供微控制器進行資料讀寫的架構。Figure 2 shows the architecture that traditionally uses 單埠SRAM for microcontrollers to read and write data.

第3圖係顯示本發明使用單埠SRAM與事件佇列供微 控制器進行資料讀寫的架構。Figure 3 shows the use of 單埠SRAM and event queues for the present invention. The controller performs the structure of reading and writing data.

第4圖係顯示本發明的事件佇列的詳細架構。Figure 4 is a diagram showing the detailed architecture of the event queue of the present invention.

3‧‧‧單埠SRAM3‧‧‧單埠SRAM

5‧‧‧事件佇列5‧‧‧ event queue

51‧‧‧事件分配器51‧‧‧Event distributor

52‧‧‧事件觸發器52‧‧‧ event trigger

53a、53b‧‧‧事件儲存器53a, 53b‧‧‧ event storage

54‧‧‧事件執行單元54‧‧‧Event Execution Unit

6‧‧‧輸出分配器6‧‧‧Output distributor

DIN、DIN A、DINB‧‧‧輸入埠DIN, DIN A, DINB‧‧‧ input埠

CTL、CTL A、CTL B‧‧‧控制端CTL, CTL A, CTL B‧‧‧ control terminal

shift‧‧‧移位端Shift‧‧‧ shifting end

empty‧‧‧空位端Empty‧‧‧vacancy

exec‧‧‧執行端Exec‧‧‧executive

output‧‧‧輸出端Output‧‧‧output

output control‧‧‧輸出控制端Output control‧‧‧output control terminal

ACT‧‧‧動作端ACT‧‧‧ action side

Claims (7)

一種用以存取多埠輸入讀寫事件的積體裝置,包括:一單埠靜態隨機存取記憶體(Static Random Access Memory,SRAM);以及一事件佇列,連接至該單埠SRAM,具有複數個輸入埠及複數個串聯的事件儲存器,該等事件儲存器分別存放透過該等輸入埠而接收之對該單埠SRAM的一讀寫事件,其中該事件佇列更具有一事件執行單元,連接至該等複數個串聯的事件儲存器與該單埠SRAM之間,根據該單埠SRAM的執行速度,控制該等事件儲存器所存放的該讀寫事件的資料移動至該單埠SRAM。 An integrated device for accessing a plurality of input and write events, comprising: a static random access memory (SRAM); and an event queue connected to the 單埠SRAM, having a plurality of input ports and a plurality of event storages connected in series, the event storages respectively storing a read/write event received by the input ports for the top SRAM, wherein the event queue has an event execution unit And connecting to the plurality of serially connected event storages and the 單埠SRAM, according to the execution speed of the 單埠SRAM, controlling the data of the read/write event stored in the event storage to move to the 單埠SRAM . 如申請專利範圍第1項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該事件執行單元在該單埠SRAM完成一讀寫事件時,會通知該事件執行單元前一級的該事件儲存器輸出所存放的下一個要執行的讀寫事件給該事件執行單元。 The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event execution unit notifies the event execution unit before the read/write event is completed by the event SRAM. The event store outputs the next read and write event to be executed to the event execution unit. 如申請專利範圍第1項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該等複數個串聯的事件儲存器中非第一級的事件儲存器的其中一者,若沒有存放一讀寫事件而具有空位,會通知前一級的事件儲存器輸出所存放的一讀寫事件給該非第一級的事件儲存器的其中一者。 An integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein one of the plurality of event storages of the plurality of serially connected event stores is not the first level If there is no hang-up event for storing a read/write event, the event storage of the previous level is notified to output a read/write event stored to one of the event stores of the non-first level. 如申請專利範圍第1項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該事件佇列更具有一事件分配器,具有:該等複數個輸入埠,用以輸入該等複數個讀寫事件;及一輸出埠,依序輸出該等複數個讀寫事件給該等 複數個串聯的事件儲存器。 The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event queue further has an event dispatcher having: the plurality of input ports for inputting And a plurality of read and write events; and an output buffer, sequentially outputting the plurality of read and write events to the A plurality of concatenated event stores. 如申請專利範圍第4項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該事件佇列更具有一事件觸發器,根據該讀寫事件來觸發該事件分配器中可先輸入的該輸入埠。 The integrated device for accessing a plurality of input and read and write events, as described in claim 4, wherein the event queue further has an event trigger, and the event dispatcher is triggered according to the read/write event. Enter the input 先 first. 如申請專利範圍第4項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該事件分配器更設有一優先權處理邏輯電路,用以設定優先執行的讀寫事件。 The integrated device for accessing a plurality of input and read and write events, as described in claim 4, wherein the event dispatcher further includes a priority processing logic circuit for setting a read/write event that is preferentially executed. 如申請專利範圍第1項所述之用以存取多埠輸入讀寫事件的積體裝置,其中該事件執行單元更可以控制一輸出分配器,決定該單埠SRAM的一輸出會透過該輸出分配器的複數輸出埠中的一輸出埠來輸出。 The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event execution unit further controls an output distributor to determine that an output of the UI SRAM is transmitted through the output. An output 埠 of the complex output 埠 of the splitter is output.
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