JPH04283494A - Dynamic ram - Google Patents

Abstract

PURPOSE:To avoid the futile power consumption and to save the electric power. CONSTITUTION:The ON, OFF control of nMOSes 31, 33 forming a transfer gate connected to one side of bit lines BL1, BL2 of the bit paired lines, is performed with a transfer gate control signal BT1 and the ON, OFF control of nMOSes 32, 34 forming a transfer gate connected to the other bit lines, BL1 bar, BL2 bar of the bit paired lines, is performed with a transfer gate control signal BT2. At the rewriting time, only nMOS forming a transfer gate connected to the bit line connected to a selected memory cell is made ON, and nMOS forming a transfer gate connected to the bit line which a selected memory cell is not connected to, is made not ON.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a dynamic RAM (
dynamic random access memo
ry. The present invention relates to a DRAM (hereinafter referred to as a DRAM) in which a bit line and a sense amplifier can be separated by a transfer gate.

0002

2. Description of the Related Art Conventionally, a DRAM of this type, the main part of which is shown in FIG. 3, has been proposed. In the figure, 1
, 2 is a row decoder, 3-6 are inverters forming buffers, Φ1 and Φ2 are word line selection signals, WL1-WL4 are word lines, 7-14 are memory cells, 15-22 are capacitors forming storage elements, 23- 30 is a cell selection switch n
MOS, BL1, BL1 bar, BL2, BL2 bar are bit lines, 31, 32, 33, 34 are nMOS which form transfer gates, BT is ON, O of nMOS 31 to 34.
Transfer gate control signal for controlling FF, 35, 3
6 is a sense amplifier; LE1 bar and LE2 bar are sense amplifier activation signals for activating sense amplifiers 35 and 36;
37 and 38 are column gates, 39 and 40 are nMOS forming the column gate 37, and 41 and 42 are column gates 3.
8, CL1 and CL2 are column selection signals, DB and DB bar are data buses, 43 is a data bus amplifier, and SBE bar is a data bus amplifier activation signal for activating the data bus amplifier 43.

FIG. 4 is a time chart for explaining the operation of such a conventional DRAM. When a logic "1" is written in the memory cell 7 (when the capacitor 15 is charged), the memory This shows a case where cell 7 is selected. In this case, first, word line WL1 becomes H
level, the nMOS23 is turned on, and the data in the memory cell 7 is output to the bit line BL1.

0004
] Next, the transfer gate control signal BT is set to L level, the nMOSs 31 and 32 are turned off, and then,
The sense amplifier activation signal LE1 bar is set to L level,
Sense amplifier 35 is activated. As a result, the voltages of the bit lines BL1 and BL1 bar between the sense amplifier 35 and the nMOSs 31 and 32 (hereinafter referred to as bit lines in the sense amplifier) start rising and falling, respectively.

[0005] After that, the column selection signal CL1 is set to H level, the nMOSs 39 and 40 are turned on, and furthermore, the data bus amplifier activation signal SBE is set to L level, and the data bus amplifier 43 is activated. As a result, data buses DB and DB bar become H level and L level, respectively.

Next, the transfer gate control signal BT is set to H level, and the nMOSs 31 and 32 are turned on. As a result, the voltages of the bit lines BL1 and BL1 bar in the memory cell array section (hereinafter referred to as intra-cell bit lines) rise and fall, respectively, and rewriting to the memory cell 7 is performed.

In such a conventional DRAM, for example, when reading data from the memory cell 7, when activating the sense amplifier 35, the bit lines BL1, BL1 are turned off by turning off the nMOS 31, 32 forming the transfer gate. Separate the bar and sense amplifier 35
Since the load can be kept light, so-called sense margin can be improved.

[0008]

[Problem to be solved by the invention] However, DRA
Since M performs destructive reading, it is necessary to rewrite data after reading it, but in the conventional DRAM shown in FIG.
The OSs 31 and 32 are turned on. Therefore, regarding the bit line BL1 bar to which the memory cell 7 is not connected,
When discharging is performed (charging is performed if logic "0" has been written to the memory cell 7) and then resetting the bit lines BL1 and BL1, the bit line BL1 is charged. (If a logic "0" has been written in the memory cell 7, it is necessary to discharge the memory cell 7.) This poses a problem in that power is wasted.

[0009] In view of the above, the present invention provides a DR that avoids wasteful power consumption and achieves power saving.
The purpose is to provide AM.

0010

[Means for Solving the Problems] A DRAM according to the present invention is provided in each column, and memory cells each having a capacitor as a storage element are connected to each other, and one bit line and the other bit line, which form a pair with each other, are connected to each other. a sense amplifier connected to the bit line through one transfer gate and to the other bit line through the other transfer gate, and between this sense amplifier and the one and the other transfer gates. In a dynamic RAM configured with one pair of data lines and the other pair connected to each other through provided column gates, one control line and the other control line separately control the one transfer gate and the other transfer gate. When rewriting, only the transfer gate connected to the bit line to which the selected memory cell is connected is turned on, and the transfer gate connected to the other bit line is not turned on. be.

[0011]

[Operation] In the present invention, during rewriting, transfer gates connected to bit lines to which selected memory cells are not connected are not turned on, so bit lines to which selected memory cells are not connected are not turned on. is not charged or discharged during rewriting, and therefore is not charged or discharged when resetting thereafter.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. The difference between this embodiment and the conventional example is that two transfer gate control lines 44 and 45 are provided, and a pair of bit lines is connected. nMO connected to one bit line BL1, BL2
ON/OFF control of S31 and S33 is performed by transfer gate control signal BT1 via transfer gate control line 44.
and the other bit line BL1 bar of the bit line pair, BL
ON, O of nMOS32, 34 connected to 2 bars
FF control is performed using a transfer gate control signal BT2 via a transfer gate control line 45.

FIG. 2 is a time chart for explaining the operation of this embodiment. When a logic "1" is written in the memory cell 7 (when the capacitor 15 is charged), the memory cell 7 is selected.

In this case, first, the word line WL1 is set to H level, the nMOS 23 is turned on, and the data in the memory cell 7 is read out to the bit line BL1.
Transfer gate control signal BT2 is set to L level, nMOS32 is turned off, and bit line BL1 bar and sense amplifier 35 are separated.

Next, transfer gate control signal BT1
is set to L level, nMOS31 is turned off, bit line BL1 and sense amplifier 35 are disconnected, and then sense amplifier activation signal LE1 is set to L level, and sense amplifier 35 is activated. As a result, the voltages on the bit lines BL1 and BL1 bar in the sense amplifier start to rise and fall, respectively.

Thereafter, the column selection signal CL1 is set to H level to turn on the nMOSs 39 and 40, and furthermore, the data bus amplifier activation signal SBE is set to L level to activate the data bus amplifier 43. As a result, data buses DB and DB bar become H level and L level, respectively.

Next, transfer gate control signal BT1
is set to H level, and the nMOS 31 is turned on. As a result, the voltage of the intra-cell bit line BL1 rises, and rewriting to the memory cell 7 is performed.

In this embodiment, the bit line BL
1 bar remains at the reset level and is not charged or discharged. Therefore, wasteful power consumption can be avoided and power savings can be achieved.

[0020]

As described above, according to the present invention, during rewriting, transfer gates connected to bit lines to which the selected memory cell is not connected are not turned on. A bit line to which is not connected will not be charged or discharged during rewriting, and therefore will not be charged or discharged when resetting thereafter. Therefore, wasteful power consumption can be avoided and power savings can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing main parts of a conventional DRAM.

FIG. 4 is a time chart for explaining the operation of a conventional DRAM.

[Explanation of symbols]

Claims (1)

[Claims] 1. A memory cell provided in each column, connected to a memory cell having a capacitor as a storage element, one bit line and the other bit line forming a pair with each other, and one transfer gate connected to the one bit line. and a sense amplifier connected to the other bit line via the other transfer gate, and a column gate provided between the sense amplifier and the one and the other transfer gates. In a dynamic RAM configured with one data line and the other data line forming a pair, one control line and the other control line are respectively provided to separately control the one transfer gate and the other transfer gate. A dynamic RAM characterized in that only a transfer gate connected to a bit line to which a memory cell is connected is turned on, and a transfer gate connected to the other bit line is not turned on.