JPH08147978A - Semiconductor storage - Google Patents

Abstract

PURPOSE: To reduce the power consumption in a semiconductor storage provided with a read-only bit line. CONSTITUTION: When a memory cell C is selected by a reading word line WLR, a precharged charge stored in a reading bit line BLR is discharged by a discharge circuit 7 based on cell information stored in the memory cell C, and the cell information is read out on the reading bit line BLR, and the reading bit line BLR is selected by a column selection signal CL, and the cell information of the required memory cell C is outputted as the read-out data. A switching circuit 8 operating based on the column selection signal CL is connected between the discharge circuit 7 and the reading bit line BLR. The switching circuit 8 prevents the discharge of the precharged charge on the reading bit line BLR by the discharge circuit 7 when the reading bit line BLR is not selected by the column selection signal CL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a read-only port.

Some SRAMs, which are one type of semiconductor memory device, have a read-only port. In such an SRAM, a write-only bit line and a read-only bit line are provided, and charge transfer between the memory cell and the read-only bit line is prevented during a read operation, thereby improving the read speed. Is being pursued.
With the recent demand for lower power consumption of semiconductor memory devices, it is necessary to reduce the power consumption of such SRAMs.

[0003]

2. Description of the Related Art A conventional example of an SRAM having a read-only port will be described with reference to FIG. A large number of memory cells C11 to Cmn are connected between each pair of a large number of pairs of write bit lines BL1, bars BL1 to BLm, and bar BLm. That is, each pair of the bit line BL1, the bar BL1 to BLm, and the bar BLm in the memory cell C11 to Cmn is
It is connected to the data storage unit 1 via a transfer transistor Ttr composed of an N-channel MOS transistor.

The transfer transistor Ttr is connected to any of a large number of write word lines WL1 to WLn, and one of the word lines WL1 to WLn is selected by a row decoder (not shown) during a write operation. It

Discharge bit lines BLS1 to BLSm are arranged adjacent to the write bit lines BL1 to BLm, and the write bit lines BL1 to BLm.
Read bit lines BLR1 to BLRm are arranged adjacent to.

Each of the discharge bit lines BLS1 to BLSm
And the memory cells C11 to Cmn are connected to the read bit lines BLR1 to BLRm. That is, each pair of bit lines BLR1, BLS1 to BLRm, BLSm has an N channel M in each memory cell C11 to Cmn.
The read transistors Trd1 and Trd2, which are OS transistors, are connected to each other.

The gate of the transistor Trd1 is connected to the bit line / bar BL1 of each data storage unit 1.
~ The transistor T connected to the terminal on the side of the BLm
The gate of rd2 is a read word line WLR1 to WLRn.
Connected to either of.

The discharge bit lines BLS1 to BLSm are connected to the ground GND and the read bit line B is connected.
Each of LR1 to BLRm is connected to the sense amplifier 2 via a column selection transistor Tcs. The sense amplifier 2 uses the read bit lines BLR1 to BLR.
The cell information input from any one of Rm is output as read data Dout.

The write bit lines BL1, bar BL
1 to BLm and BLm are respectively connected to the write amplifier 3 via the column selecting transistor Tcs, and the column selecting signals CL1 to CLm for each column are provided to the inverter circuit 4 at the gate of the column selecting transistor Tcs.
It is input via a and 4b. Write data Din is input to the write amplifier 3 during a write operation.

The column selection signals CL1 to CLm are output from the column decoder, and one of the column selection signals CL1 to CLm becomes H level based on the column address signal. Then, when any of the column selection signals CL1 to CLm becomes H level, the column selection transistor Tcs of the column is turned on.

The read bit lines BLR1 to BLR
A precharge circuit 5 is connected to each m, and the precharge circuit 5 precharges the read bit lines BLR1 to BLRm to the power supply Vcc level prior to the cell information read operation.

The write bit lines BL1, bar BL
An equalizer circuit 6 is connected between each pair of 1 to BLm and BLm, and the equalizer circuit 6 reads the read bit lines BL1 and BL1 prior to the cell information write operation.
Each pair of bars BL1 to BLm and bar BLm is precharged to the power supply Vcc level.

The operation of the SRAM thus configured will be described. At the time of a write operation, the write bit line BL1, bars BL1 to BLm, bar BLm are first supplied to the power source Vcc by the equalizer circuit 6 prior to the write operation.
Precharged to level.

Next, when any one of the write bit line pairs is selected by the column selection signals CL1 to CLm,
Write data is output from the write amplifier 3 to the bit line pair. Then, the write operation is performed on one memory cell selected by the write word line from the memory cells connected to the bit line pair.

In the read operation, the read bit lines BLR1 to BLRm are precharged to the power supply Vcc level by the precharge circuit 5 prior to the read operation.

Next, the read word lines WLR1 to WR
When any one of LRn is selected, the read transistor Trd2 connected to the word line is turned on. In each of the memory cells C11 to Cmn, the data storage unit 1
If the cell information input to the gate of the reading transistor Trd1 from H is H level, the reading transistor Trd1 is turned on, and if the cell information is L level,
The transistor Trd1 is turned off.

When the read transistors Trd1 and Trd2 are turned on, the read bit lines BLR1 to BLRm.
Is connected to the discharge bit lines BLS1 to BLSm, and the read bit lines BLR1 to BLRm are set to the ground GND level.

When the transistor Trd1 is turned off, the read bit lines BLR1 to BLRm are not connected to the bit lines BLS1 to BLSm and their precharge levels are maintained.

Therefore, one of the word lines is selected,
Moreover, when any of the read bit lines BLR1 to BLRm is selected by the column selection signals CL1 to CLm,
The cell information read from the selected memory cell is input to the sense amplifier 2, and the sense amplifier 2 outputs the cell information as read data Dout.

[0020]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the RAM, when any of the read word lines WLR1 to WLRn is selected, cell information is read from the memory cells connected to the word line to the read bit lines BLR1 to BLRm.

Each read bit line BLR1 to BLRm
When the cell information read out at 1 is at the L level, the charges precharged on the bit lines BLR1 to BLRm are discharged to the discharge bit lines BLS1 to BLSm. Then, one of the read bit lines BLR1 to BLRm is selected by the column selection signals CL1 to CLm, and the cell information read to the selected bit line is output as the read data Dout via the sense amplifier 2. It

Therefore, even in a column that is not selected,
When the read cell information is at the L level, the precharge charges of the read bit lines BLR1 to BLRm are drained to the ground GND without being effectively used. Then, in the next cycle of the read operation, the read bit lines BLR1 to BLR1 having the ground GND level.
The precharge operation is performed again on the LRm by the precharge circuit 5.

As a result, a large amount of precharge current flows during the precharge operation of the read bit lines BLR1 to BLRm performed in each cycle of the read operation, resulting in an increase in power consumption.

Further, in such an SRAM, the row address has increased and the number of word lines has increased with the increase in storage capacity in recent years. Further, as the column address increases, the read bit lines BLR1 to BLR1 to
The number of BLRm is also increasing.

Therefore, the read bit lines BLR1 to BLR1.
As the number of LRm increases, the precharge charge that is not effectively used increases, and the power consumption further increases. In addition, as the number of word lines increases, the number of read transistors connected to each of the read bit lines BLR1 to BLRm also increases. As a result, the parasitic capacitance of each read bit line BLR1 to BLRm increases,
The pre-charge current increases and the power consumption increases.

An object of the present invention is to reduce the power consumption of a semiconductor memory device having a read-only bit line.

[0027]

FIG. 1 shows the first aspect of the present invention.
FIG. That is, the write word line WL for selecting the memory cell C at the time of writing the cell information.
And a write bit line BL and a read word line WL for selecting a memory cell C during a cell information read operation.
R and a read bit line BLR, a precharge circuit 5 for precharging the read bit line BLR prior to the read operation, and the read word line WLR provided in the memory cell C, respectively. Discharge circuit 7 connected to the read bit line BLR
When the memory cell C is selected by the read word line WLR, the semiconductor memory device including is stored in the read bit line BLR based on the cell information stored in the memory cell C. The precharge charge is discharged by the discharge circuit 7, and the read bit line BL
The cell information is read to R, and the read bit line BL
R is selected by the column selection signal CL, and the cell information of the desired memory cell C is output as read data. Between the discharge circuit 7 and the read bit line BLR,
A switching circuit 8 that operates based on the column selection signal CL is connected. The switching circuit 8 prevents the discharge circuit 7 from discharging the precharge charge of the read bit line BLR when the read bit line BLR is not selected by the column selection signal CL.

In claim 2, as shown in FIG.
The discharge circuit includes a discharge bit line BLS for discharging precharge charges of the read bit line BLR,
Switch circuits Trd1, Trd for opening and closing the connection between the read bit line BLR and the discharge bit line BLS based on the cell information and the selection of the read word line WLR.
2, the switching circuit pulls down the discharge bit line BLS to the potential of the low potential side power supply GND when the read bit line BLR is selected based on the column select signal CL, and outputs the column select signal. When the read bit line BLR is not selected based on CL, the potential of the discharge bit line BLS is raised to the precharge potential of the read bit line BLR.

In claim 3, as shown in FIG.
The switching circuit is configured by connecting the discharge bit line BLS to the output terminal of an inverter circuit 4a that inverts the column selection signal CL.

In claim 4, as shown in FIG.
The discharge bit line BLS is shared by two adjacent columns, and the switching circuit pulls down the discharge bit line BLS to the ground level when one of the adjacent columns is selected.

In claim 5, as shown in FIG.
Each of the read bit lines BLR is an N channel M
The N-channel MOS transistor Trn is connected to the gate of the OS transistor Trn and is interposed in series with the data bus DB that is precharged prior to the read operation, and one end of the data bus DB is turned on during the read operation Trn. To the ground GND, and the sense amplifier 2 is connected to the other end of the data bus DB.

[0032]

According to the present invention, the read bit line BLR of the column not selected by the column selection signal CL is prevented from being discharged by the discharge circuit 7 of the column.

In the second aspect, the column selection signal CL
When the read bit line BLR is selected based on
The potential of the discharge bit line BLS connected to the read bit line BLR via the switch circuit is the low potential side power source G.
The voltage is lowered to the ND level, and the switch circuit selects whether or not to connect the read bit line BLR to the discharge bit line BLS.

In the third aspect, when the read bit line BLR is selected based on the H level column selection signal, the potential of the discharge bit line BLS is set to the low potential side power source based on the output signal of the inverter circuit 4a. It is lowered to the GND level.

According to the fourth aspect, when one of the two adjacent columns is selected, the discharge bit line BLS common to the columns is pulled down to the ground level. In the fifth aspect, the read bit lines BLR of the unselected columns are all at the H level, and the read bit lines BLR of the selected column are at the H level or the L level based on the cell information. Therefore, when the read bit line BLR of the selected column becomes H level, the input data of the sense amplifier 2 becomes L level, and when the read bit line BLR of the selected column becomes L level, the input of the sense amplifier 2 becomes The data becomes H level.

[0036]

FIG. 2 shows a first embodiment of an SRAM embodying the present invention. In this embodiment, the discharge bit line BLS1 is used.
The configuration is similar to that of the conventional example except for the configurations of BLSm to BLSm.

Discharge bit lines BLS1 to BL of each column
Sm is a column selection signal CL for selecting each column
1 to CLm are connected to the output terminal of the inverter circuit 4a.

The write operation of the SRAM thus constructed is similar to that of the conventional example. During read operation,
Prior to the read operation, the precharge circuit 5 precharges the read bit lines BLR1 to BLRm.

Next, for example, the read word line WLR
When 1 is selected, the column selection signal CL1 becomes H level, and the read bit line BLR1 is selected,
The memory cell C11 is selected, and the cell information of the memory cell C11 is read out to the bit line BLR1.

At this time, the H level column selection signal CL
1, the output signal of the inverter circuit 4a becomes L level, and the discharge bit line BLS1 becomes ground GND level. In this state, when the read transistor Trd1 is turned on based on the cell information stored in the data storage section 1 of the memory cell C11, the transistors Trd1 and Trd are turned on.
When 2 is turned on, the bit line BLR1 becomes the ground GND level, and the cell information at the L level is read out to the bit line BLR1.

On the other hand, when the read transistor Trd1 is turned off based on the cell information stored in the data storage section 1 of the memory cell C11, the bit line BLR1 is maintained at the precharge level and the cell information at the H level is kept. It is read to the same bit line BLR1. Then, the cell information read on the bit line BLR1 is output as read data Dout via the sense amplifier 2.

In addition, other column selection signals CL2 to CLm
Becomes the L level, the discharge bit lines BLS2 to BL
Sm is maintained at H level. Therefore, even if the cell information is read from the other memory cells connected to the read word line WLR1 to the read bit lines BLR2 to BLRm, the precharge charges of the bit lines BLR2 to BLRm are not removed.

Next, when the precharge operation is performed prior to the read operation of the next cycle, the precharge current flows only to the read bit line BLR1 when the L-level cell information is read.

As described above, in this SRAM, the precharge current is required in the next cycle only for the read bit line selected by the column selection signal during the read operation and reading out the cell information of the L level, and other than that. The precharge current does not flow through the read bit line. Therefore, the precharge current can be reduced and the power consumption can be reduced.

FIG. 3 shows a second embodiment embodying the present invention. In this embodiment, the discharge bit lines BLS of two adjacent columns are made common. Each bit line BLS is set to the ground GND level when either of the columns on both sides thereof is selected. For that purpose, the column selection signal input to the adjacent columns may be input to the NOR circuit, and the output terminal of the NOR circuit may be connected to the discharge bit line BLS.

In the SRAM thus constructed, when one of the adjacent columns is selected, the discharge bit line BLS connected to the column becomes the ground GND level, and the other discharge bit lines BLS are at the H level. Maintained at.

In the selected column and the column sharing the discharge bit line BLS with the selected column, if the cell information of the selected memory cell is at L level, the read bit line BLR of the column is selected. Pre-charged through the discharge bit line BLS to the ground G
Although it is drained to ND, the precharge charge of the read bit line BLR is not drained in other columns.

Therefore, as in the first embodiment, the precharge current can be reduced and the power consumption can be reduced. Moreover, since the discharge bit lines BLS of the adjacent columns are shared, the number of the same bit lines BLS can be reduced and the circuit area can be reduced.

FIG. 4 shows a data read circuit constructed by utilizing the present invention. The structure of the memory cell array is the same as that of the first embodiment. Then, during the read operation, the discharge bit line BLS of the selected column
Only becomes the ground GND level, and the bit lines BLS of the other columns are maintained at the H level.

The read bit line BLR of each column is
Each is connected to the gate of an N-channel MOS transistor Trn, and each transistor Trn is interposed in series with the data bus DB.

One end of the data bus DB is an N channel M
It is connected to the ground GND via the OS transistor Trn, and the sense amplifier enable signal SE is input to the gate of the transistor Trn.

The other end of the data bus DB is connected to the input terminal of the sense amplifier 2, and the read data Dout is output from the sense amplifier 2. Data bus DB connected to the read bit line BLR and the sense amplifier 2
A P-channel MOS transistor Trp forming a precharge circuit is connected to the
The precharge signal PRC is input to the gate of rp.

Therefore, the L-level precharge signal PR
When C is input, each transistor Trp is turned on,
Each read bit line BLR and data bus DB are precharged to the power supply Vcc level.

Next, the operation of such a data read circuit will be described. Before the read operation, when the precharge signal PRC becomes L level, the read bit line B
The LR and the data bus DB are precharged. Also,
The sense amplifier enable signal SE is maintained at L level.

Next, when the read operation is started and one of the columns is selected, the discharge bit line BLS of the selected column becomes the L level and the discharge bit line BLS of the other columns becomes the H level. Become.

Then, the read bit line BLR of the unselected column becomes H level regardless of the cell information, and the transistor Trn connected to the bit line BLR concerned.
Is turned on.

Further, the read bit line BLR of the selected column is maintained at the precharge level if the read cell information is at the H level, and if the read cell information is at the L level. The precharged charge is supplied to the ground GN via the discharge bit line BLS of the column.
Overtaken by D.

Next, when the H-level sense amplifier enable signal SE is input, the read cell information becomes H level.
In the case of the level, all the transistors Trn interposed in the data bus DB are turned on, the precharge charge of the data bus DB is drained to the ground GND, and the sense amplifier 2
Input signal becomes L level.

On the other hand, when the read cell information is at L level, the transistor Trn interposed in the data bus DB is present.
1 is turned off, the precharge charge of the data bus DB is not removed, and the input signal of the sense amplifier 2 becomes H level.

Therefore, since the input signal of the sense amplifier 2 changes based on the read cell information, the change of this input signal is output from the same sense amplifier 2 as the read data Dout.

As described above, in this embodiment, the cell bit read from the selected column is stored in the data bus DB by utilizing the fact that the read bit line BLR of the unselected column is maintained at the H level. You can read it.

Further, it is not necessary to lay out signal wiring for column selection near the data bus DB. Therefore, in addition to the effect of the first embodiment, the degree of freedom of the wiring layout can be improved.

The technical ideas other than the claims which can be understood from the above-mentioned embodiments will be described below together with their effects. (1) In claim 2, the discharge bit line is shared by a plurality of adjacent columns, and the switching circuit grounds the discharge bit line when one of the plurality of columns is selected. Lower to level. In addition to the effect of the invention of claim 1, the circuit area can be reduced. (2) In claim 1, each of the read bit lines is connected to a gate of an N-channel MOS transistor, and the N-channel MOS transistor is serially connected to a data bus which is precharged to a low potential side power supply level prior to a read operation. , One end of the data bus is connected to a high-potential side power source through a switch circuit that is turned on during a read operation, and the other end of the data bus is connected to a sense amplifier. In addition to the effect of the first aspect of the invention, it is possible to improve the degree of freedom in the layout of the signal wiring for selecting the column.

[0064]

As described in detail above, according to the first aspect of the invention, the power consumption of the semiconductor memory device having the read bit line can be reduced.

According to the second aspect of the invention, only the precharge charge of the read bit line selected based on the column selection signal is selected by the switch circuit to be discharged to the discharge bit line. Power consumption during a read operation can be reduced.

According to the third aspect of the invention, only the precharge charge of the read bit line selected based on the column selection signal can be discharged with a simple structure. According to the invention of claim 4, in addition to the effect of the invention of claim 1, the circuit area can be reduced.

According to the invention of claim 5, in addition to the effect of the invention of claim 1, the degree of freedom in the layout of the signal wiring for selecting the column can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment.

FIG. 4 is a circuit diagram showing a read circuit using the first embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 5 precharge circuit 7 discharge circuit 8 switching circuit BL write bit line BLR read bit line WL write word line WLR read word line C memory cell CL column select signal

Claims (5)

[Claims] 1. A write word line and a write bit line for selecting a memory cell during a cell information write operation, and a read word line and a read bit line for selecting a memory cell during a cell information read operation, A precharge circuit for precharging the read bit line prior to a read operation; a discharge circuit provided in each of the memory cells and connected to the read word line and the read bit line; When a memory cell is selected by the read word line, the precharge charge accumulated in the read bit line is discharged by the discharge circuit based on cell information stored in the memory cell, and the read circuit is read. The cell information is read out to the read bit line, and the read bit line is selected by the column selection signal. A semiconductor memory device for outputting cell information of the memory cell as read data, wherein a switching circuit that operates based on the column selection signal is connected between the discharge circuit and the read bit line, A semiconductor memory device, wherein a switching circuit prevents the discharge circuit from discharging precharge charges of the read bit line when the read bit line is not selected by the column selection signal. 2. The discharge circuit includes a discharge bit line for discharging precharge charges of the read bit line, and the read bit line based on the cell information and the selection of the read word line. And a switching circuit for opening and closing the connection with the discharge bit line, wherein the switching circuit connects the discharge bit line to the low potential side power source when the read bit line is selected based on a column selection signal. 2. The semiconductor according to claim 1, wherein the potential of the discharge bit line is raised to a precharge potential of the read bit line when the read bit line is not selected based on a column selection signal. Storage device. 3. The switching circuit is configured by connecting the discharge bit line to an output terminal of an inverter circuit that inverts the column selection signal.
The semiconductor memory device described. 4. The discharge bit line is shared by two adjacent columns, and the switching circuit pulls down the discharge bit line to a ground level when one of the adjacent columns is selected. Claim 2 characterized by the above-mentioned.
The semiconductor memory device described. 5. The read bit lines are respectively connected to the gates of N-channel MOS transistors, and the N-channel MOS transistors are interposed in series with a data bus to be precharged prior to a read operation, and one end of the data bus is connected. 2. The semiconductor memory device according to claim 1, wherein is connected to the ground via a switch circuit that is turned on during a read operation, and a sense amplifier is connected to the other end of the data bus.