JPH09219095A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EPROM dispensing with equipment of overlapped parts as preventive measures of malfunctions of sense amplifiers due to charge shares. SOLUTION: In an EPROM of precharge and discharge system, in a precharge circuit 16 precharging data lines DLs and bit lines BLs before reading out data from memory arrays 10a, 10b, the precharge driving force with respect to the memory cell array of a reference side is set larger than the precharge driving force with respect to the memory cell array of a read side and a timing is set so that dischargings are started almost as soon as precharging are completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory mounted in a non-volatile memory integrated circuit or a logic integrated circuit, and more particularly to a precharge / discharge type non-volatile semiconductor memory.

[0002]

2. Description of the Related Art In non-volatile semiconductor memories such as EPROM (ultraviolet erasable / rewritable ROM), EEPROM (electrically erasable / rewritable ROM), mask ROM, etc. Precharge / discharge by precharging the reference side bit line and discharging the read side bit line / reference side bit line during data read to generate a potential difference between them and sense amplification of this potential difference by a sense amplifier. The method is often adopted.

FIG. 3 is a circuit diagram showing a part of a conventional precharge / discharge type EPROM. In FIG. 3, 10a is the first memory cell array,
10b is a second memory cell array. In each of the memory cell arrays, a plurality of transistors for memory cells are arranged in a matrix. The cell transistor is composed of an NMOS transistor having a double-layer gate structure of a floating gate and a control gate. One row of memory cells in the memory cell array is a reference cell 11r for generating a reference potential, and the remaining plurality of rows have a plurality of rows. The memory cell is the read cell 11 for storing data.

WL is a word line, and a plurality of cell transistors 1 for read cells in the same row of the memory cell array.
1 is commonly connected to each control gate and is selectively driven by a word line signal from a row decoder (not shown).

RWL is a reference word line, which is commonly connected to the respective control gates of a plurality of cell transistors 11r for reference cells in the same row of the memory cell array, and a reference word line from a row decoder (not shown). It is selectively driven by a signal.

BL is a bit line, which is commonly connected to the drains of a plurality of read cell transistors and one reference cell transistor 11r in the same column of the memory cell array.

SL is a source line of the memory cell array, which is commonly connected to the sources of the plurality of cell transistors 11 in the same column, and the source lines of a plurality of columns (four columns in this example) are collectively connected. A discharge NMOS transistor 12 is connected between the collectively connected source line SL and a ground potential (VSS) node, and a discharge signal DIS is applied to its gate.

Reference numeral 13 denotes an NMOS transistor for column selection, one end of which is connected to each bit line BL, and is selectively driven by a column selection signal from a column decoder (not shown). Then, the other ends of the respective column selection transistors 13 in a plurality of columns (four columns in this example) are collectively connected.

Reference numeral 14 is an NMOS transistor 14 for clamping the bit line potential, one end of which is connected to the collective connection terminal of the plurality of column selecting transistors 13. The NMOS transistor 14 for clamping the bit line potential is
It is for clamping the bit line potential at the time of reading, and an I-type transistor whose threshold voltage is around 0V is used, and its gate has a bias potential Vbias of about 1V.
Is given.

Reference numeral 15 is the two memory cell arrays 10 described above.
It is a latch type sense amplifier which is provided commonly to a and 10b and senses and amplifies a potential difference generated between the pair of data lines DL during data reading.

The sense amplifier 15 is composed of a flip-flop circuit in which one input end of each of the two two-input NOR gates 151 is cross-connected to the other output end of each of the two input NOR gates 151. Memory cell array 10a, 1
0b bit line potential clamp transistor 14
The data line DL on the other end side of is connected.

Reference numeral 31 is between the pair of data lines DL and a VCC node to which a normal power supply potential VCC is applied (that is, V
The precharge circuit is composed of a precharge PMOS transistor 311 connected between the CC node and a pair of input nodes of the sense amplifier 15), and the gate of the precharge PMOS transistor 311 has a precharge signal / PR. Is given.

The read cell 11 has a high gate threshold in a written state and a low gate threshold in a non-written state, and the reference cell 11r has a low gate threshold and gm of the reference cell. Is smaller than gm of the read cell.

FIG. 4 is a timing waveform chart showing an example of a data read operation in the EPROM of FIG. As is well known, in the data read operation of the EPROM of FIG. 3, the address of the memory cell to be selected is determined, and one memory cell array (for example, 10 memory cells) to be selected is selected.
After the read cell of a) and the reference cell of the other memory cell array (for example, 10b) are selected, the precharge signal / PR becomes "L" level before data reading. As a result, the precharge transistor 311
Is turned on, and the data line DL and the bit line BL are precharged to the "H" level (power supply potential Vcc).

At this time, if the selected read cell transistor 11 is in the ON state, the common source line SL connected thereto via this transistor 11 is also precharged, and the selected reference cell transistor 1
The common source line SL connected to it via 1r (on state) is precharged.

Next, when the precharge signal / PR becomes "H" level and the precharge is completed, the data read operation is started. At this time, the discharge signal DIS
Is at the "H" level, the common source line SL, the bit line BL connected to the read cell transistor 11 in the ON state and the corresponding data line DL, and the bit line connected to the reference cell transistor 11r. BL and the corresponding data line DL are discharged.

Then, after a lapse of a predetermined time, a predetermined polarity value Δ between the read side data line DL and the reference side data line DL according to the stored data of the selected read cell 11.
When a potential difference of V or more occurs, the potential of the output node of the sense amplifier 15 becomes "L" level or "H" level according to the stored data, and the read data OUT is output through an output buffer (not shown).

In the data read operation as described above, on the reference side, when the reference cells 11r of each column are selected, all the reference cells 11r of each column are turned on, and the reference cells 11r of the selected column ( The current flowing in the ON state) is the reference cell 1 of the non-selected column via the common source line SL.
The load capacitance of the data line DL on the reference side is relatively large because it flows around 1r (on state).

On the other hand, on the read side, when the read cells 11 of each column are selected, only an arbitrary number of read cells 11 having a low gate threshold value are turned on. In this case, if the read cell 11 of the selected column is in the ON state, the current flowing therethrough is the common source line SL.
Of the read cells 11 in the non-selected column to flow around the read cells in the ON state. If the read cells 11 in the selected column are in the OFF state, no sneak current is generated.

Therefore, depending on the state of the storage data of the read cell 11 group connected to the common source line SL, 2
Not only when the parasitic load capacitance of the reference side data line DL and the parasitic load capacitance of the read side data line DL when the memory cell arrays 10a and 10b are precharged are equal, The parasitic load capacitance may be larger than the parasitic load capacitance of the data line DL on the read side.

The data line D on the reference side as in the former case
When the parasitic load capacitance of L and the parasitic load capacitance of the data line DL on the read side are equal, the potential of the common source line SL on the reference side and the potential of the common source line SL on the read side are equal after the completion of precharge. . Here, since the gm of the reference cell is set to be smaller than the gm of the read cell 11 in advance, if the common source line SL and the data line DL on the read side are discharged when the data read operation (discharge) is started. , The potential of the data line DL on the read side drops faster than the potential of the data line DL on the reference side.
5 can correctly detect and amplify the stored data in the read cell 11.

On the other hand, if the parasitic load capacitance of the data line DL on the reference side is larger than the parasitic load capacitance of the data line DL on the read side as in the latter case, on the reference side after the end of precharge. Common source line S
The potential of L becomes lower than that of the common source line SL on the lead side (becomes an unbalanced state).

When the data read operation (discharge) is started in such an unbalanced state, when the common source line SL and the data line DL on the read side are discharged, the potential of the data line DL on the read side is exceeded. Also the common source line SL and the data line DL on the reference side
There is a possibility that the potential of 2 decreases faster, and there is a risk of malfunction in which the sense amplifier 15 erroneously detects and amplifies the stored data in the non-written state of the read cell 11 as the stored data in the written state.

Therefore, in order to eliminate the imbalance between the potential of the common source line SL on the reference side after the precharge and the potential of the common source line SL on the read side within the precharge period, before the end of the precharge. I am trying to start the discharge. That is, part of the precharge period and the discharge period are overlapped.

However, as described above, the provision of the overlap portion between the precharge period and the discharge period as a measure for preventing malfunction due to charge sharing substantially shortens the discharge period, speeding up the read operation or operating power supply. This is an obstacle to lowering the voltage of.

As a measure for preventing malfunction due to charge sharing without providing an overlapping part,
A method of discharging even during the precharge period has been proposed, but this method causes an increase in current consumption and is not suitable for application to a semiconductor memory such as a battery drive which requires low power consumption.

[0027]

As described above, the bit line on the read side and the bit line on the reference side are precharged before the data is read, and the data is read between the read side data line and the reference side data line during data reading. In a precharge / discharge type EPROM in which the potential difference between the two is sense-amplified by a sense amplifier, the conventional method in which an overlap portion is provided between the precharge period and the discharge period as a measure for preventing malfunction due to charge sharing is an obstacle to high-speed read operation. There was a problem of becoming.

According to the present invention, the bit line on the read side and the bit line on the reference side are precharged before the data is read, and the potential difference between the data line on the read side and the data line on the reference side is read by the sense amplifier during data reading. It is an object of the present invention to provide a non-volatile semiconductor memory of a precharge / discharge type which is sense-amplified and which does not require an overlapping part as a measure for preventing malfunction due to charge sharing.

[0029]

According to the present invention, the bit line on the read side and the bit line on the reference side are precharged before the data is read, and the data line on the read side and the data line on the reference side are connected during data reading. In a non-volatile semiconductor memory of a precharge / discharge system in which a potential difference between the two is sense-amplified by a sense amplifier, the precharge circuit has a precharge driving force for a memory cell array on a reference side rather than a precharge driving force for a memory cell array on a read side. Is set larger, and the timing is set so that the discharge starts at almost the same time as the precharge ends.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an E of a precharge / discharge system according to the first embodiment of the present invention.
1 schematically shows a part of a PROM.

In FIG. 1, 10a is a first memory cell array and 10b is a second memory cell array. In each of the memory cell arrays, a plurality of transistors for memory cells are arranged in a matrix. The cell transistor comprises an NMOS transistor having a two-layer gate structure of a floating gate and a control gate,
One row of memory cells of the memory cell array is a reference cell 11r for generating a reference potential, and the remaining memory cells of a plurality of rows are read cells 11 for storing data.

WL is a word line, and a plurality of cell transistors 1 for read cells in the same row of the memory cell array.
1 is commonly connected to each control gate and is selectively driven by a word line signal from a row decoder (not shown).

RWL is a reference word line, which is commonly connected to the respective control gates of a plurality of cell transistors 11r for reference cells in the same row of the memory cell array, and a reference word line from a row decoder (not shown). It is selectively driven by a signal.

BL is a bit line, which is commonly connected to the drains of a plurality of read cell transistors and one reference cell transistor 11r in the same column of the memory cell array.

SL is a source line of the memory cell array, which is commonly connected to the sources of the plurality of cell transistors 11 in the same column, and the source lines of a plurality of columns (four columns in this example) are collectively connected. A discharge NMOS transistor 12 is connected between the collectively connected source line SL and a ground potential (VSS) node, and a discharge signal DIS is applied to its gate.

Reference numeral 13 denotes an NMOS transistor for column selection, one end of which is connected to each bit line BL, and is selectively driven by a column selection signal from a column decoder (not shown). Then, the other ends of the respective column selection transistors 13 in a plurality of columns (four columns in this example) are collectively connected.

Reference numeral 14 denotes an NMOS transistor 14 for clamping the bit line potential, one end of which is connected to the collective connection terminal of the plurality of column selecting transistors 13. The NMOS transistor 14 for clamping the bit line potential is
It is for clamping the bit line potential at the time of reading, and an I-type transistor whose threshold voltage is around 0V is used, and its gate has a bias potential Vbias of about 1V.
Is given.

Reference numeral 15 is the above two memory cell arrays 10
It is a latch type sense amplifier which is provided commonly to a and 10b and senses and amplifies a potential difference generated between the pair of data lines DL during data reading.

The sense amplifier 15 is composed of a flip-flop circuit in which one input end of each of the two two-input NOR gates 151 is cross-connected to the other output end of each of the two input NOR gates 151. Memory cell array 10a, 1
0b bit line potential clamp transistor 14
The data line DL on the other end side of is connected.

The read cell 11 has a high gate threshold value in the written state and a low gate threshold value in the non-written state, and the reference cell 11r has a low gate threshold value. The gm is set smaller than the gm of the read cell 11.

Further, in the present embodiment, as the precharge circuit 16 connected between the pair of data lines DL and the VCC node to which the normal power supply potential VCC is applied, the precharge driving for the memory cell array on the read side is performed. The precharge driving force for the memory cell array on the reference side is set to be larger than the force. Also,
The timing is set so that the discharge period starts at almost the same time as the end of the precharge period.

As a specific example of the precharge circuit 16, in this example, the precharge circuit 16 is provided between the VCC node and the pair of data lines DL (that is, between the VCC node and the pair of input nodes of the sense amplifier 15). Correspondingly connected first
Of the precharge PMOS transistor 161 and the second precharge PMOS transistor 162, and are similarly connected between the VCC node and the pair of input nodes of the sense amplifier 15 (that is, the first precharge PMOS transistor 161). Precharging transistor 161 and second
And a third precharge PMOS transistor 163 and a fourth precharge PMOS transistor 163, which are connected in parallel corresponding to the precharge transistor 162, respectively.
And a transistor 164.

In this case, the transconductances of the first to fourth precharge transistors are correspondingly gm1 and gm.
When expressed by m2, gm3, and gm4, it is set to have a relationship of gm1 = gm4 <gm2 = gm3. In this example, the first
~ When the gate width of the fourth precharge transistor is correspondingly represented by W1, W2, W3, and W4, it is set to have a relationship of W1: W2: W3: W4 = 1: 4: 4: 1. There is.

The gates of the first precharge transistor 161 and the second precharge transistor 162 have a first precharge signal / PRa at their gates.
Is supplied to the third precharge transistor 163.
The second precharge signal / PRb is applied to each gate of the fourth precharge transistor 163.

In this case, the first memory cell array 1
0a read cell 11 / second memory cell array 10b
If the reference cell 11r of
Precharge signal / PRa is controlled to "L" level (active state), and second precharge signal / PRb is controlled to "H" level (inactive state).

On the other hand, the second memory cell array 1
0b read cell 11 / first memory cell array 10a
If the reference cell 11r of
Precharge signal / PRb is controlled to "L" level (active state), and first precharge signal / PRa is controlled to "H" level (inactive state).

With this configuration, when the read cell 11 of the first memory cell array 10a / the reference cell 11r of the second memory cell array 10b is selected, the first precharge signal / PRa is used to generate the first precharge signal. Since the charging transistor 161 and the second precharging transistor 162 having a larger driving force than this are turned on, in the precharge completion state, the reference side and the read side are irrespective of the state of the stored data of the read cell 11. The common source line SL is evenly precharged, or the common source line SL on the reference side is precharged in a larger amount than the common source line SL on the read side.

On the other hand, the second memory cell array 1
0b read cell 11 / first memory cell array 10a
If the reference cell 11r of
Since the fourth precharge transistor 164 and the third precharge transistor 163 having a larger driving force than this are turned on by the precharge signal / PRb of, the state of the storage data of the read cell 11 in the precharge end state is Regardless of this, the common source line SL is evenly precharged on the reference side and the read side, or the common source line SL on the reference side is precharged more than the common source line SL on the read side. It becomes a state.

Next, the data read operation in the EPROM of FIG. 1 will be described with reference to the timing waveforms shown in FIG. After the address of the memory cell to be selected is determined and the read cell 11 of one memory cell array to be selected and the reference cell 11r of the other memory cell array are selected, the precharge signal / PR is set to the “L” level before data reading. become. As a result, the precharge circuit 16 is turned on, and the data line DL and the bit line BL are precharged to the "H" level (power supply potential VCC).

At this time, if the selected read cell transistor 11 is in the on state, the common source line SL is also precharged via this transistor, and the common source is supplied via the selected reference cell transistor 11r (on state). Line SL is precharged.

In this case, in the precharge completed state, the common source line SL on the read side and the common source line on the reference side are irrespective of the state of the storage data of the read cells 11 sharing the common source line SL with the selected column. SL
Are evenly precharged, or the common source line SL on the reference side is more than the common source line SL on the read side.
Is more precharged.

Next, the precharge signal / PR goes to "H" level to end the precharge, and the discharge signal DIS goes to "H" level to start the data read operation. At this time, the common source line SL, the bit line BL connected to the read cell transistor 11 in the ON state and the corresponding data line DL, the bit line BL connected to the reference cell transistor 11r and the corresponding data The lines DL are discharged respectively.

As a result, depending on the ON / OFF state of the selected read cell transistor 11 and the read current of the reference cell transistor 11r, a predetermined time elapses between the read side data line DL and the reference side data line DL. A potential difference of not less than a predetermined value ΔV of the polarity is generated according to the storage data of the selected read cell 11. This potential difference is detected and amplified by the sense amplifier 15, and the potential of the output node of the sense amplifier 15 is "L" according to the stored data.
It becomes the level or the "H" level, and is output as read data through an output buffer (not shown).

In the data read operation as described above, on the reference side, the reference word line RWL
When the reference cell 11r of each column is selected by, all the reference cells 11r of each column are turned on, and the reference cell 11r of the selected column is selected.
The current flowing in r (on state) passes through the common source line SL and the reference cell 11r (on state) of the unselected column
The data line D on the reference side
The load capacity of L is relatively large.

On the other hand, on the read side, when the read cell 11 of each column is selected by the word line, an arbitrary number of read cells 11 whose gate thresholds are set low.
Only turned on. In this case, if the read cell 11 of the selected column is in the ON state, the current flowing through the read cell 11 of the non-selected column passes through the common source line SL.
Among them, the sneak current flows into the read cell 11 in the ON state and flows, and if the read cell 11 in the selected column is in the OFF state, the sneak current does not occur.

Therefore, depending on the state of the storage data of the read cell 11 group connected to the common source line SL, 2
Not only when the parasitic load capacitance of the reference side data line DL and the parasitic load capacitance of the read side data line DL when the memory cell arrays 10a and 10b are precharged are equal, The parasitic load capacitance may be larger than the parasitic load capacitance of the data line DL on the read side. However, in the precharge completion state by the precharge circuit 16 of this example, the common source line SL on the reference side and the read side. Common source line SL is uniformly precharged (the above-mentioned unbalanced state of the precharge amount due to the unbalanced state of the parasitic load capacitance is eliminated) or the common source line SL on the reference side. A larger amount is precharged than the common source line SL on the read side.

When the common source line SL is uniformly precharged on the reference side and the read side as in the former case, gm of the reference cell is previously g of the read cell.
Since it is set smaller than m, when the common source line and data line on the read side are discharged when the data read operation (discharge) is started (when the read cell is in the non-write state or the ON state), the read side The potential of the data line of # 1 drops faster than the potential of the data line of the reference side.

On the contrary, like the latter, the common source line SL on the reference side is the common source line S on the lead side.
If the precharge is larger than L, the potential of the read side data line DL is discharged when the read side common source line SL and the data line DL are discharged when the data read operation (discharge) is started. Decreases faster than the potential of the data line DL on the reference side.

In other words, regardless of the state of the stored data of the read cell group connected to the common source line SL,
Data line DL on the read side due to the start of discharge
Is discharged (the read cell is in the non-write state or the ON state), the data line DL on the read side is always present.
Since the potential of the voltage V.sub.2 drops faster than the potential of the data line DL on the reference side, the sense amplifier 15 can correctly detect and amplify the data stored in the read cell.

On the other hand, when the data line on the read side is not discharged (the read cell is in the written state,
In the off state), the potential of the data line DL on the reference side drops faster than the potential of the data line on the read side, so that the sense amplifier 15 can correctly detect and amplify the stored data in the read cell. .

Therefore, unlike the conventional example, it is not necessary to start the discharge before the end of the precharge (that is, the precharge period and a part of the discharge period are overlapped), and the discharge period can be sufficiently secured. It is possible to speed up the operation or reduce the voltage of the operating power supply.

FIG. 3 schematically shows a part of the precharge / discharge type EPROM according to the second embodiment of the present invention. Compared with the EPROM shown in FIG. 1, the EPROM shown in FIG. 3 has (1) a configuration of the first precharge circuit 31 connected between the VCC node and the data line DL pair, and (2) VCC. Node and the common source line S
The second precharge circuit 32 is additionally connected to L, and the other parts are the same, and are therefore denoted by the same reference numerals as in FIG.

As a concrete example of the first precharge circuit 31, the fifth precharge PMOS transistors 311 of substantially the same size are connected between the Vcc node and the data line DL pair, and their respective gates are connected. Is supplied with a precharge signal / PR.

As a concrete example of the second precharge circuit 32, a sixth precharge PMOS transistor 32 is provided between the VCC node and the common source line SL.
1 and I-type NMOS for common source line potential clamp
A transistor 322 is connected in series, the precharge signal / PR is applied to the gate of the sixth precharge transistor 321, and a common source line potential clamp N
The bias potential Vbias is applied to the gate of the MOS transistor 322.

With such a configuration, during the precharge period, the fifth precharge transistor 311 and the sixth precharge transistor 321 are turned on by the precharge signal / PR, so that in the precharge end state. The common source line SL on the reference side and the common source line SL on the read side are evenly precharged regardless of the state of the stored data in the read cell 11.

Therefore, in the data read operation, the sense amplifier 15 can correctly detect and amplify the stored data read from the read cell transistor 11 as in the EPROM of FIG.

[0067]

As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory that does not require an overlapping portion as a measure for preventing malfunction of the sense amplifier due to charge sharing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of an EPROM according to a first embodiment of the present invention.

2 is a timing waveform chart showing an example of a read operation of a cell transistor in FIG.

FIG. 3 is a circuit diagram showing a part of an EPROM according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of a conventional EPROM.

5 is a timing waveform chart showing an example of a read operation of the cell transistor in FIG.

[Explanation of symbols]

 10a ... 1st memory cell array, 10b ... 2nd memory cell array, 11 ... Read cell transistor, 11r ... Reference cell transistor, 12 ... Discharge transistor, 13 ... Column selection transistor, 14 ... Bit line potential clamping transistor, 15 ... Sense amplifier, 16 ... Precharge circuit, 161 ... 1st precharge transistor, 162 ... 2nd precharge transistor, 163 ... 3rd precharge transistor, 164 ... 4th precharge transistor , BL ... bit line, WL ... word line, RWL ... reference word line, SL ... source line, DL ... data line.

Claims (7)

[Claims] 1. An ON state / when selected according to stored data
A non-volatile read cell transistor for data storage whose threshold value is set to be in the off state and a non-volatile reference cell transistor for reference whose threshold value is set to be in the on state when selected are arranged in a matrix. A first memory cell array and a second memory cell array; a plurality of word lines commonly connected to the control gates of read cell transistors in the same row in each memory cell array; and a reference in the same row in each memory cell array. A reference word line commonly connected to a control gate of a cell transistor, and a plurality of bits commonly connected to a plurality of read cell transistors and a drain of one reference cell transistor in the same column in each memory cell array. Line and each of the above A plurality of source lines commonly connected to respective sources of a plurality of read cell transistors and one reference cell transistor in the same column in the memory cell array and a plurality of source lines in each of the memory cell arrays are collectively connected. A common source line, and is connected between the common source line and a ground potential node,
A discharge circuit that is controlled to be in an ON state when reading data from the memory cell array, and a column selection transistor in which one end is connected to each bit line in each memory cell array and the other ends are collectively connected. And a bit line potential clamping transistor having one end connected to a collective connection end of each column selection transistor in each of the plurality of columns in each of the memory cell arrays, a data line connected to the other end, and a bias potential applied to a gate, The memory cell array is commonly provided to the two memory cell arrays, and
A pair of input nodes is connected to each data line of each memory cell array, and a latch-type sense amplifier that detects and amplifies a potential difference generated between the data lines of the two memory cell arrays at the time of reading data and a power supply potential are applied. A precharge circuit connected between the power supply node and the pair of data lines, the precharge circuit being controlled so as to precharge the data lines and the bit lines before reading data from the memory cell array. In the precharge circuit, the precharge driving force for the reference side memory cell array is set to be larger than the precharge driving force for the read side memory cell array, and at the same time as the end of the precharge by the precharge circuit, the precharge driving force is set. Start the discharge by the discharge circuit. Nonvolatile semiconductor memory, wherein the timing is set. 2. The precharge circuit includes a first precharge PMOS transistor and a second precharge PMOS transistor connected between the power supply node and a pair of input nodes of a sense amplifier, respectively. And a third precharging PMOS transistor and a fourth precharging PMOS transistor which are similarly connected between the power supply node and the pair of input nodes of the sense amplifier, respectively. Corresponding transconductances of the second, third, and fourth precharge transistors are gm1, gm2,
When expressed by gm3 and gm4, it is set to have a relationship of gm1 <gm2 gm3 <gm4, and the first precharge signal is applied to each gate of the first precharge transistor and the second precharge transistor. And a second precharge signal is applied to the gates of the third precharge transistor and the fourth precharge transistor, and the read cell of the first memory cell array / the reference of the second memory cell array is provided. When the cell is selected, the first precharge signal is controlled to the active state and the second precharge signal is controlled to the inactive state, and the read cell of the second memory cell array / the reference cell of the first memory cell array is controlled. Is selected, the second precharge signal is active, the first precharge signal is The nonvolatile semiconductor memory according to claim 1, characterized in that it is controlled in an inactive state. 3. The non-volatile semiconductor memory according to claim 1, wherein the relationships among the gm1, gm2, gm3 and gm4 are gm1 = gm4 and gm2 = gm3. 4. The non-volatile according to claim 1, wherein the transconductance of the reference cell transistor is set smaller than the transconductance of the read cell transistor. Semiconductor memory. 5. An ON state at the time of selection according to stored data /
A non-volatile read cell transistor for data storage whose threshold value is set to be in the off state and a non-volatile reference cell transistor for reference whose threshold value is set to be in the on state when selected are arranged in a matrix. A first memory cell array and a second memory cell array; a plurality of word lines commonly connected to the control gates of read cell transistors in the same row in each memory cell array; and a reference in the same row in each memory cell array. A reference word line commonly connected to a control gate of a cell transistor, and a plurality of bits commonly connected to a plurality of read cell transistors and a drain of one reference cell transistor in the same column in each memory cell array. Line and each of the above A plurality of source lines commonly connected to respective sources of a plurality of read cell transistors and one reference cell transistor in the same column in the memory cell array and a plurality of source lines in each of the memory cell arrays are collectively connected. A common source line, and is connected between the common source line and a ground potential node,
A discharge circuit that is controlled to be in an ON state when reading data from the memory cell array, and a column selection transistor in which one end is connected to each bit line in each memory cell array and the other ends are collectively connected. And a bit line potential clamping transistor having one end connected to a collective connection end of each column selection transistor in each of the plurality of columns in each of the memory cell arrays, a data line connected to the other end, and a bias potential applied to a gate, The memory cell array is commonly provided to the two memory cell arrays, and
A pair of input nodes are connected to each data line of each memory cell array, and a latch type sense amplifier that detects and amplifies a potential difference generated between the data lines of the two memory cell arrays at the time of reading data, a power supply node and the above A first precharge circuit connected between a pair of data lines and controlled to precharge the data lines and bit lines before reading data from the memory cell array; the power supply node and the common source Connected between the wire and
A second precharge circuit that is controlled to precharge the common source line before reading data from the memory cell array, and the discharge is performed substantially at the same time when the precharge by the first precharge circuit is completed. A non-volatile semiconductor memory, wherein timing is set so that discharge by a circuit starts. 6. The first precharge circuit is configured such that fifth precharge PMOS transistors having substantially the same size are connected between the power supply node and the data line pair, and the respective gates are precharged. A signal is applied, and the second precharge circuit includes a sixth precharge PMOS between the power supply node and the common source line.
NMO for transistor and common source line potential clamp
S transistors are connected in series, the gate of the sixth precharge transistor is supplied with the precharge signal, and the gate of the common source line potential clamping NMOS transistor is supplied with the bias potential. The nonvolatile semiconductor memory according to claim 5. 7. The non-volatile semiconductor memory according to claim 5, wherein the transconductance of the reference cell transistor is set smaller than the transconductance of the read cell transistor.