JPH0652681A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To prevent a standby current from defect when the defect in short- circuit is replaced by a redundant circuit by providing a transfer gate composed of a MOS between a 1/2.VCC power source line and a bit line pair. CONSTITUTION:When the device shifts over from an active to an inactive state, a word line WL1 becomes a low level after writing information in a storage capacitor C1, transfer gates Tr1, Tr2 are turned off, a differential amplifier circuit 10 and bit lines D, -D (inverted value) are released. Also, the balance signal TG2 becomes a high level at the same time a signal TG1 becomes low, the transfer gates Tr4, Tr5 are turned on and the bit lines D, -D are balanced so as to be an 1/2.VCC. In an active state, a signal TG3 becomes high, a transfer gate Tr6 is turned on and the bit lines D, -D are charged to the 1/2.VCC through the transfer gates Tr4, Tr5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device,
In particular, it relates to a folded bit line type dynamic memory.

[0002]

2. Description of the Related Art A conventional folded bit line type dynamic memory has a circuit configuration as shown in FIG. 3 and shows signal timing diagrams as shown in FIG.

In FIG. 3, a MOS transistor Tr
7, Tr8, Tr10, Tr11, MOS transistor Tr9, storage capacitor C2, bit lines D, D (inverted value), word line WL2, signals TG4, TG5
, The 1/2 · VCC power supply line, and the differential amplifier circuit 20 are shown.

FIG. 4 shows the waveform of the row address strobe (RAS), the waveform of the signal TG4 and TG5 lines, the waveform of the word line WL2, and the waveforms of the bit lines D and D (inversion value) in FIG.

When the row address strobe RAS of FIG. 4 becomes high, the signal TG4 becomes higher than the power supply voltage VCC,
A pulse returning to VCC is generated at a certain time, and the pulse is generated by the Nch MOS transistor Tr7 of FIG.
When input to Tr8, bit lines D, D (inverted value)
Becomes the VCC and GND levels by the differential amplifier circuit, respectively.

Then, when the word line WL2 is high, the level of the bit line D is applied to the storage capacitor C2. Then, when the writing to the storage capacitor C2 is completed, the word line WL2 becomes low, and then the balance of the bit line pair and the signal TG for connecting to the 1 / 2.VCC power supply
5 goes high. Then, the bit line pair D, D
(Inverted value) is fixed at 1 / 2.VCC level, and is always 1 / 2.until the next activation state (RAS "L").
A 1/2 VCC level is applied to D and D (inverted value) by the VCC power supply.

In the folded bit line system,
The bit line on the side not connected to the memory cell serves as the reference potential of the differential amplifier circuit. In addition, the information of the memory cell is high,
Since there is no difference in sensitivity when judging low,
The reference potential is 1/2 VCC.

[0008]

In recent years, the degree of integration of semiconductor integrated circuits has advanced, and the capacity of memory cells has increased. Then, the area of the memory cell also increases, and a redundant circuit is included in order to increase the manufacturing yield.

Therefore, in the conventional folded bit line type dynamic memory, when a short circuit between the word line and the bit line occurs, the word line and the bit line can be replaced by using a redundant circuit. Then, in the activated state, it can operate normally, but in the deactivated state, the bit line is 1 /
Since the word line is fixed to GND at 2 · VCC, the current consumption increases due to the short circuit between the word line and the bit line. Therefore, there is a problem that the standby current becomes defective.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated device in which the current consumption due to a short circuit between lines does not increase and a standby current defect does not occur.

[0011]

In the semiconductor integrated device of the present invention, the differential amplifier circuit for memory cell information and the bit line pair are opened via the transfer gate immediately after transition from the active state to the inactive state. And a means for balancing the bit line pair through a transfer gate and for floating the bit line pair in the inactive state, and a word line for selecting the cell at a high level after the activation state. It is characterized in that a means for charging the bit line pair to a desired initial voltage is provided.

[0012]

1 is a circuit diagram showing a semiconductor integrated device according to an embodiment of the present invention, and FIG. 2 is a timing chart of each signal of FIG.

Referring to FIG. 1, in the embodiment of the present invention, a transfer gate Tr6 composed of a MOS transistor is arranged between a 1 / 2.VCC power supply line and a bit line pair in a conventional circuit (see FIG. 2). ing.

The operation of the circuit of this embodiment will be described with reference to the timing chart of FIG. In FIG. 2, the row address strobe (RAS) changes to the high (HIGH) level to shift from the active state to the inactive state. At that time, the storage capacity C1
After writing information to the word line WL1 goes low (L
OW), the signal TG1 goes low so as to open the bit lines D, D (inverted value) and the differential amplifier circuit 10. The transfer gates Tr1 and Tr2 are turned off,
The differential amplifier circuit 10 and the bit line are opened.

The balance signal TG of the bit line pair
2 goes high at the same time as signal TG1 goes low,
Transfer gate (Nch / MOS transistor)
Tr4 and Tr5 are turned on, and the bit lines D and D (inversion value) are connected and balanced. Here, since the bit lines D and D (inverted value) are set to VCC and GND before the balance, the bit lines D and D (inverted value) become 1/2 · VCC when balanced. Bit line D, D
Since the (inverted value) is floating, the level becomes a little lower than 1/2 · VCC when the inactivity becomes long. Therefore, when activated (RAS goes from low to high), the 1 / 2.VCC power supply and bit lines D, D
The signal TG3 connecting to (inversion value) becomes high, and the transfer gate (Nch / MOS transistor) Tr
6 turns on and charges the bit line to 1/2 · VCC. However, the transfer gate Tr6 is turned off before a word line is selected and it goes from low to high.

As described above, in the semiconductor integrated device of this embodiment, a signal for floating the bit line when the dynamic memory cell of the folded bit line system is inactivated, a signal for balancing, and 1 / 2.VCC.
It has a signal connected to a power supply and a transfer gate having the signal as an input.

[0017]

As described above, according to the present invention, since the bit line is set to ½ · VCC to be in the floating state especially when it is inactive, a short circuit between the word line and the bit line occurs, and a redundant circuit is generated. When replaced by, the current only flows from the bit line to the word line for a moment and the standby current does not increase significantly,
Therefore, it is not a defective product, and has an effect of preventing a decrease in yield in manufacturing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated device of one embodiment of the present invention.

FIG. 2 is a timing diagram showing signals at various points in the embodiment of FIG.

FIG. 3 is a circuit diagram showing a conventional dynamic memory cell.

FIG. 4 is a timing diagram showing signals of various parts in FIG.

[Explanation of symbols]

Tr1 to Tr12 Nch MOS transistor WL1, WL2 Word line D, D (inverted value) Bit line TG1, TG4 Control signal for connecting bit line and differential amplifier circuit TG2, TG5 Balanced signal of bit line pair TG3 bit line Connection signal with 1/2 / VCC power supply C1, C2 Storage capacity 10, 20 Differential amplifier circuit

Claims (1)

[Claims] 1. A means for opening a differential amplifier circuit for memory cell information and a bit line pair via a transfer gate immediately after transition from an active state to an inactive state, and thereafter, the bit line pair is provided with a transfer gate. A means for balancing the bit line pair in the inactive state and a floating means for setting the bit line pair to a desired initial level after the active state until the word line for cell selection becomes high level. A semiconductor integrated device comprising means for charging to a voltage.