JPH04313900A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize an effective testing by computing a nondefective/defective dis crimination information and outputting that information to the external through the use of an exclusive logic sum operation of the read out data from a memory cell array and the holding data of a pattern register. CONSTITUTION:Prescribed data for a testing are read out into a pattern register 19 through an input buffer 21 and furthermore, the data are written into a memory cell array 10 through a write driver 20. The data read out into the array 10 are used together with the read out data RD and the stored data PR of the register 19 at a discriminating circuit 25 to perform the array 10's nondefective/defective discrimination. When the output of an exclusive logic circuit 32 of the circuit 25 is zero, it means that the write data to the array 10 are correctly read out and when the output of the circuit 32 is one, it means that the write data to the array 10 are not correctly read out. These compacted information are outputted to the external through a selector 24 and an output driver 22 and the nondefective/defective condition decision of the array 10 is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device equipped with a test function for a memory cell array capable of storing data, and is particularly applicable to a multi-bit dynamic RAM. Regarding technology.

0002

2. Description of the Related Art Conventionally, a testing device called a tester has been used in testing semiconductor memory devices. This tester has the function of generating address information and test data patterns, and the function of comparing data. It is possible to determine whether the semiconductor memory device is good or bad.

[0003] An example of a document describing tasting of a semiconductor memory device is Japanese Patent Laid-Open No. 64-628.
There is a publication No. 99.

0004

[Problems to be Solved by the Invention] As mentioned above, a tester for a semiconductor memory device has a built-in comparator for comparing test data read from the semiconductor memory device with its expected value. The inventor investigated this and found that in testers for semiconductor memory devices such as dynamic RAM, which have increasingly large storage capacities, the built-in It has been found that as the number of comparators increases, the test equipment becomes expensive. Furthermore, if the number of comparators built into such a tester is reduced, the number of semiconductor memory devices that can be simultaneously tested by one tester is reduced, resulting in an increase in test cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can reduce the circuit scale of a tester and efficiently perform testing of a semiconductor memory device using the tester.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory cell array capable of storing data, a holding means for holding test data of this memory cell array, and a write/read control means for controlling writing and reading of this test data to and from the memory cell array. a determining means for determining the quality of the memory cell array based on the read data from the memory cell array of the data written in the memory cell array by the write/read control means and the data held by the holding means; and this quality determination information. When a semiconductor memory device is formed including an external output control means for controlling an external output, the pass/fail determination information is compressed by an exclusive OR operation of read data from the memory cell array and data held by the holding means. The discriminating means includes a logic circuit for making external output possible. In a more specific aspect, the logic circuit can be formed to include a first logic circuit for checking quality and a second logic circuit for checking the state of data; The first logic circuit includes a selective logic inverting circuit for selectively inverting the logic state of read data from the memory cell array on a bit-by-bit basis depending on the logic state of data held by the holding means; The second logic circuit may be configured to include an exclusive OR circuit that obtains an exclusive OR of the outputs of the logic inverting circuit, and the second logic circuit reads data read from the memory cell array and data held by the holding means. It can be formed to include a plurality of exclusive OR circuits for obtaining the exclusive OR of , bit by bit, and an OR circuit for obtaining the OR of the plurality of exclusive OR circuits. To easily configure the selective logic inversion circuit, an inverter for inverting the logic of read data from the memory cell array bit by bit, and a logic inverter by this inverter depending on the logic state of the data held in the holding means. It is preferable to include a selector capable of selecting inverted data and data before logical inversion. In addition, in order to enable testing of more data lines at the same time, it is preferable to use the read data used for quality determination in the above-mentioned determination means as data before selection by the column selection circuit operated in response to the column address. . Furthermore, in order to be able to arbitrarily select the external terminal used for external output of the pass/fail determination information, a selector for selecting an external terminal used for external output of the pass/fail determination information is provided in the external output control means. can be included. In order to reduce external control signals as much as possible when testing semiconductor memory devices, only the row address counter that generates row addresses, the column address counter that generates column addresses, and the memory cell array are tested. It is preferable to provide an address multiplexer which supplies the output of the row address counter and the output of the column address counter to a subsequent stage circuit instead of the input address signal from the outside.

[0009]

[Operation] According to the above-mentioned means, the determining means includes the test data written in the memory cell array, which determines the quality of the memory cell array based on read data from the memory cell array and the data held in the holding means. A logic circuit configured to perform an exclusive OR operation on data read from the memory cell array and data held in the holding means can reduce the pass/fail determination information and output it to the outside. allows for omission,
Furthermore, the tester simplified in this manner allows efficient testing of a large number of semiconductor memory devices.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a dynamic RAM which is an embodiment of the present invention. In the figure, 10 is a memory cell array, and this memory cell array 10 includes a plurality of 1-transistor type dynamic memory cells MS in which an N-channel type MOSFET and a storage capacitor are connected in series, which are arranged in a matrix, although the memory cell array 10 is not particularly limited. Become. The memory cells MS are coupled in equal numbers to every other complementary data line DL laid out by the folded data line method via data input/output terminals (MOSFET drain electrodes), and the selection terminals (MOSFET drain electrodes) of each memory cell MS are M
(gate electrodes of the OSFETs) are coupled to word lines WL in respective columns.

Reference numeral 12 denotes a row address buffer for taking in a row address given from the outside, and a row decoder 11 is arranged at the subsequent stage of this row address buffer 12 for decoding the row address taken in by the row address. Ru. Further, 13 is a column address buffer for taking in a column address given from the outside, and a column decoder 17 is arranged at the subsequent stage of this column address buffer 13 for decoding the column address taken in by this column address buffer. . Addressing of the memory cell array 10 involves driving a predetermined word line WL to a selected level based on the output of a row decoder 11 including a word driver, and driving a pair of complementary data lines WL based on the output of a column decoder 17. This is performed based on a column selection circuit 15 that selectively connects the lines to a complementary common data line (also referred to as a common data line), which is not shown. Each complementary data line is coupled to, but not limited to, a signal input terminal of the static sense amplifier 14. This sense amplifier 13
Although not particularly limited, the inverter is configured by mutually cross-coupling the input and output terminals of a CMOS inverter circuit, and is driven through a power switch MOSFET whose gate receives sense amplifier operation signals having mutually opposite phases. There is. The output terminal of the sense amplifier 13 is coupled via the column selection circuit 15 to the main amplifier 18 and the output terminal of a write driver 20 having a function of holding data input via the input buffer 21.

Reference numeral 19 denotes a pattern register. Although not particularly limited, the pattern register 19 is laid out at the periphery of the chip and has a function of holding data for testing the memory cell array 10. A data input terminal of the pattern register 19 is coupled to an input buffer 21, through which test data can be written from outside. Although the test data is not particularly limited, it has an 8-bit configuration such as "00110010".

Reference numeral 25 denotes a discrimination circuit (CMP), and this discrimination circuit 25 distinguishes between read data RD from the memory cell array 10 of the test data written in the memory cell array 10 and data PR held in the pattern register 19. It is possible to determine the quality of the memory cell array 10 based on the above, and the determination output is sent to the selector 24.
and the control circuit 23. This discrimination circuit 25 will be described in detail later with reference to FIG. 2, but in order to simplify the configuration of the tester used for testing the dynamic RAM of this embodiment,
The memory cell array 10 is configured to include a logic circuit for reducing the pass/fail determination information of the memory cell array 10 to 2 bits and outputting it to the outside by performing an exclusive OR operation of read data from the pattern register 19 and data held in the pattern register 19. .

The selector 24 can selectively transmit the output of the main amplifier 18 and the output of the discrimination circuit 25 to the output driver 22 at the subsequent stage. In the normal operation mode of the dynamic RAM of this embodiment, , selects the output of the main amplifier 18, and in the test mode,
It acts to select the output of the discrimination circuit 25. Such selection control is performed by the control circuit 23. The output driver 22 and the input buffer 21 share a data external terminal, and if the number of data external terminals is n, although this is not particularly limited, the output driver 22 and the input buffer 21 also have an n-bit configuration. In that case, the external output of the quality determination information of the determination circuit 25 includes n
The upper or lower two bits of the bit-configured output buffer 24 and data external terminal are used. That is, in this embodiment, in order to prevent an increase in the number of external terminals, a dedicated external terminal is not provided for the external output of the pass/fail judgment information of the discriminating circuit 25, and the selection operation of the selector 24 allows The existing data external terminal is also used.

23 is a control circuit, and this control circuit 23
includes a row address strobe signal RAS* (* indicates row active or signal inversion) indicating the validity of the row address, a column address strobe signal CAS* indicating the validity of the column address, and the memory cell array 10.
Write enable signal WE instructs to write data to
*, various control signals such as an output enable signal OE* that instructs external output of data are inputted from the outside, and based on such various control signals, this control circuit 23 performs the operations according to the present embodiment. Controls the operation of each part of the dynamic RAM. Such a control function realizes a write/read control means for controlling writing and reading of test data into the memory cell array 10 and an external output control means for controlling external output of quality determination information of the memory cell array 10. be done. Further, the test mode of the dynamic RAM of this embodiment is also realized by this control circuit 23. For example, when the column address strobe signal CAS* is asserted to a low level, the row address strobe signal RAS* is asserted to a low level, and further, in this state, the write enable signal WE* is asserted to a low level. It is considered to be in test mode. In this test mode, a half potential application mode is set in which the plate potential is set to HVcc (half potential) by setting one predetermined bit of the row address, for example, A0, to a high level, and the row address A1
is set to a high level, so that the memory cell array 1
This is the reduction mode for the quality determination information of 0. In this reduction mode, the pattern register 19 and the discrimination circuit 25
etc. are enabled, test data can be written to the pattern register 19 from the outside, and
Writing the test data to the memory cell array 10, reading the data from the memory cell array 10, and further writing the test data RD and the test data P.
It is possible to determine whether the memory cell array 10 is good or bad based on R.

FIG. 2 shows an example of the configuration of the discrimination circuit 22.

The determination circuit 22 has a first logic circuit 27 for checking quality and a second logic circuit 26 for checking the state of data. The first logic circuit 27 converts the logic state of the read data RD from the memory cell array 10 into data P held in the pattern register 19.
It is configured to include a selective logic inversion circuit 42 for selectively inverting bits in accordance with the logic state of R, and an exclusive OR circuit 32 for obtaining an exclusive OR of the output of this inversion circuit 42. Ru. At this time, the selective logic inversion circuit 42 includes a plurality of inverters 3 for inverting the logic of read data RD from the memory cell array 10 bit by bit.
0-1 to 30-n and the logic state of the data RD held in the pattern register 19.
a selector (SEL) 31- that can selectively select logically inverted data and data before logically inverted according to 1 to 30-n;
1 to 31-n. In addition, the second
The logic circuit 26 includes a plurality of exclusive OR circuits 28-1 to 28-n for obtaining the exclusive OR of the read data RD from the memory cell array 10 and the data held in the pattern register 19 in bit units. and an OR circuit 29 that obtains the OR of the plurality of exclusive OR circuits 28-1 to 28-n. Although not particularly limited, the inverters 30-1 to 30-n, selectors (SEL) 31-1 to 31-n, and exclusive OR circuits 28-1 to 28-n may be connected to the pattern register 19 or the main amplifier. They are arranged corresponding to the number of output bits, such as 18.

Next, the operation in the reduction mode of the quality determination information of the memory cell array 10 will be described in detail.

FIG. 3 shows an example of output data of the main part in this embodiment.

In the above reduction mode, predetermined test data is transmitted from the tester of the dynamic RAM of this embodiment.
It is written into the pattern register 19 via the input buffer 21. This test data is "00110010"
Then, the data written to the memory cell array 10 via the write driver 20 is "00110010".
Or "11001101".

Data “0” is output from the memory cell array 10.
0110010'' (this is called D reading), the first logic circuit 27 in the discrimination circuit 25 selects the pattern register 19 out of the read data RD by the selection action of the selectors 31-1 to 31-n. Retained data (
The bits inverted by the inverters 30-1 to 30-n are assigned as bits corresponding to the bits in which the test data) is set to "1", and as a result, the selector (S
The outputs of EL) 31-1 to 31-n, that is, the input data of the exclusive OR circuit 32, are "00000000". Therefore, in that case, the output of the exclusive OR circuit 32 is set to "0" since all bits are the same. On the other hand, when data "11001101" is read out from the memory cell array 10 (this is referred to as D* reading), the determination circuit 25
Now, as in the case above, the selectors 31-1 to 31-
Due to the selection action of n, among the read data RD, the data held in the pattern register 19 (test data) is “1”.
'' are assigned bits inverted by inverters 30-1 to 30-n, and as a result, selectors (SEL) 31-1 to 31
The output of -n, that is, the input data of the exclusive OR circuit 32 is "11111111". Therefore, the output of the exclusive OR circuit 32 in that case is also "0" because all bits are the same.
”. In this way, when the output of the exclusive OR circuit 32 is "0", it means that the write data to the memory cell array 10 has been correctly read, and the pass/fail (F
AIL/PASS) check output is determined to be good (PASS). On the other hand, as shown in FIG. 3, if an error occurs in the fourth bit of the read data from the memory cell array 10 and the read data becomes "11011101", selectors (SEL) 31-1 to 31
The output of -n, that is, the input data of the exclusive OR circuit 32 is "11101111", and as a result, the output of the exclusive OR circuit 32 is "1", unlike the above case. In this way, the output of the exclusive OR circuit 32 is “1”.
”, it means that the write data to the memory cell array 10 was not read correctly, and the pass/fail (FAIL/PASS) check output indicates the failure (FAI/PASS).
L).

As mentioned above, one of the exclusive OR circuits 32
The state of the bit output reflects the result of determining whether or not there is an error bit in the read data from the memory cell array 10, and the information thus reduced is transmitted via the selector 24 and output driver 22. It is output externally,
By inputting the data to a tester (not shown), it is possible to judge whether the memory cell array 10 is good or bad.

[0023] Here, the above-mentioned pass/fail (FAIL/PASS)
) Check only, for example, in the case of D read, the output of the selectors (SEL) 31-1 to 31-n is "1111".
1111" or in the case of D* reading,
The outputs of selectors (SEL) 31-1 to 31-n are “0”.
0000000'', the output of the exclusive OR circuit 32 is set to ``0'', and it is determined to be good (PASS), even though such a state is originally defective. Therefore, in this embodiment, in the second logic circuit 26, D/D*
By performing checks, such inconveniences are eliminated.

That is, in the second logic circuit 26, the exclusive OR operation of the read data RD from the memory cell array 10 and the data PR held in the pattern register 19 is performed by exclusive OR circuits 28-1 to 28-16. The logical sum of these outputs is performed bit by bit by the logical sum circuit 2.
9, and the logical sum output thereof is used as the D/D* check output. The output of the OR circuit 29 is set to "0" when the read data RD from the memory cell array 10 and the data PR held in the pattern register 19 completely match, and is set to "0" when they do not match. is set to "1". That is, in the case of D read, both the read data RD from the memory cell array 10 and the data PR held in the pattern register 19 are "00110010".
”, and they match perfectly, so the output of the OR circuit 29 is set to “0”, whereas in the case of D* reading,
The read data RD from the memory cell array 10 is “
11001101", and the data PR held in the pattern register 19 is "00110010", and both data are mismatched, so the output of the OR circuit 29 is "1".
It is said that In D read, such 1 bit D/
When the D* check output is set to “1”, even if FA
Even if the IL/PASS check output is "0", it is determined to be defective, and similarly, if the D/D* check output is "0" in D* reading, even if it is FAIL/
Even if the PASS check output is "0", it is determined to be defective. Therefore, D/D* by the second logic circuit 26
By taking the check output into account, D
In the case of reading, selectors (SEL) 31-1 to 31-
When the output of n is "11111111" or in the case of D* reading, the selectors (SEL) 31-1 to 3
Even when the output of 1-n is "00000000", it is possible to accurately determine whether the memory cell array 10 is good or bad.

According to the above embodiment, the following effects can be obtained.

(1) A determination circuit 25 for determining the quality of the memory cell array based on read data RD from the memory cell array 10 of the test data written in the memory cell array 10 and data PR held in the pattern register 19; In the included logic circuit, the pass/fail determination information is compressed by an exclusive OR operation of the read data RD from the memory cell array 10 and the data PR held in the pattern register 19, and can be output to the outside. In a dynamic RAM tester, the read data R from the memory cell array 10 is
A comparator for comparing D and its expected value is not required, and testing of a large number of semiconductor memory devices can be efficiently performed using such a simplified tester.

(2) First logic circuit 27 for checking pass/fail (FAIL/PASS) and data status (D/D
*) A second logic circuit 26 for checking is formed to form the logic circuit in (1) above, and in this case, the logic state of the read data RD from the memory cell array 10 is determined by the logic state of the pattern register 19. Retained data P
A selective logic inversion circuit 42 for selectively inverting bits in accordance with the logic state of R, and an exclusive OR circuit 3 for obtaining an exclusive OR of the output of this selective logic inversion circuit 42.
2, the first logic circuit 27 can be easily formed, and the exclusive OR of the read data RD from the memory cell array 10 and the data PR held in the pattern register 19 can be obtained in bit units. The above-mentioned second logic circuit can be easily formed by a plurality of exclusive OR circuits 28-1 to 28-16 and an OR circuit 29 for obtaining the logical sum of the plurality of exclusive OR circuits. .

(3) The selective logic inversion circuit 42 includes inverters 30 - 1 to 30 - n for inverting the logic of the read data RD from the memory cell array 10 bit by bit, and the pattern register 19 . Data P
This inverter 30-1 to 30 depending on the logic state of R
By providing selectors 31-1 to 31-n that can select logically inverted data by -n and data before logically inverted, the selective logical inverting circuit 42 can be easily formed.

(4) Furthermore, the dynamic RA of the above embodiment
M assumes the use of a tester in its testing, and does not include all of the tasting functions within the chip, so the chip size is smaller than when all of the tasting functions are included within the chip. It is said to be advantageous in that it can suppress the increase.

FIG. 4 shows a dynamic RAM according to another embodiment of the present invention.

In the dynamic RAM shown in FIG.
In order to set the read data used for determining the quality of the memory cell array 10 as the data before selection by the column selection circuit,
A discrimination circuit (CMP) 25 is arranged between the sense amplifier 14 and the column selection circuit 15. Also,
A selector 24 is provided to enable selection of an external terminal used for external output of quality determination information of the memory cell array 10, and a first select register 34 is further provided to enable programmable setting of such external terminal selection.
, a second select register 35 are provided.

The block configuration other than the above is the same as that of the above embodiment.

In the test mode, the row decoder 11
The word line WL is selected based on the output of the word line WL, and at that time, the stored data (previously written test data) of all the memory cells MS coupled to the word line WL driven to the selection level is read. will be held. The read data is amplified by the corresponding sense amplifier 14,
The signal is input to a discrimination circuit (CMP) 25. This discrimination circuit 2
Reference numeral 5 indicates whether or not the memory cell array is good or bad based on read data from the memory cell array 10 of the test data written in the memory cell array 10 and data held by the holding means, and this judgment circuit 25 includes: The same configuration as that in the above embodiment can be applied (see FIG. 2). In the case of this embodiment, since the discrimination circuit 25 is arranged before the column selection circuit 15,
The number of memory cells MS that can be simultaneously tested increases compared to the case where the discrimination circuit 25 is arranged after the main amplifier 18 as in the above embodiment. For example 1
If 16.times.256 memory cells are coupled to one word line, all of them can be tested simultaneously, thereby reducing the testing time. Here, since the operation of each of the plurality of discrimination circuits 25 is the same as in the above embodiment, the explanation thereof will be omitted.

Discrimination information (FAI) from the discriminator circuit 25
L/PASS check output, D/D*check output (total 2 bits) are sent to the output driver 2 via the selector 24.
2, and can be further output to the outside via this output driver 22. Which of the plurality of data external terminals is used for this external output depends on the contents held in the first select register 34 and the second select register 35. That is, depending on the contents held in the first select register 34, the output of the first logic circuit 27 is FAIL/PAS.
The data external terminal used for the S check output is determined, and the data external terminal used for the D/D* check output, which is the output of the second logic circuit 26, is determined depending on the contents held in the second select register 35. Ru. Information can be written to the first select register 34 and the second select register 35 from a tester or the like in the test mode.

In this embodiment, the test data written in the memory cell array 10 is read out from the memory cell array 10 based on the data RD held in the pattern register 19 and the data PR held in the pattern register 19. Discrimination circuit 25 that determines the quality of the cell array
In the logic circuit included in the memory cell array 1,
Read data RD from 0 and the pattern register 1
The above-mentioned pass/fail judgment information is reduced by the exclusive OR operation of the held data PR of 9 and can be outputted externally, so in such a dynamic RAM tester, the read data RD from the memory cell array It has the same effects as the above embodiments, such as eliminating the need for a comparator for comparing expected values and allowing efficient testing of a large number of semiconductor memory devices using such a simplified tester. can be obtained.

Furthermore, in the case of this embodiment, the column selection circuit 1
Since the discrimination circuit 25 is arranged before the main amplifier 18, the number of memory cells MS that can be tested simultaneously is lower than when the discrimination circuit 25 is arranged after the main amplifier 18 as in the above embodiment. By writing information to the first select register 34 and the second select register 35, data external terminals used for externally outputting quality determination information of the memory cell array 10 are increased. can be set arbitrarily,
There are special effects such as

FIG. 5 shows a dynamic RAM according to yet another embodiment of the present invention.

In the dynamic RAM shown in FIG.
a row address counter 37 that generates a row address;
Column address counter 39 that generates column addresses
and address multiplexers 38 and 4 that supply the output of the row address counter 37 and the output of the column address counter 39 to subsequent stage circuits in place of external input address signals only when testing the memory cell array 10.
Including 0. When entering the test mode, the row address counter 37 and column address counter 39 are set to preset initial values. In the test mode, the output of the row address counter 37 is selected by the address multiplexer 38 and transmitted to the row decoder 11. Similarly, the output of the column address counter 39 is selected by the address multiplexer 40 and transmitted to the column decoder 17. In synchronization with the falling timing of the row address strobe signal RAS*, the row address counter 37 and the column address counter 3
9 is counted up and the address is updated. This makes it possible to test all bits of the memory cell array 10.

Even with the above configuration, the same effects as in the above embodiment can be obtained, and since the row address counter 37 and the column address counter 39 are built in, it is possible to generate an address signal internally. , there is no need to supply address signals externally in test mode,
Therefore, there is a unique advantage that in the test mode, there is no need to input address signals from the outside or input control signals associated therewith.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, by incorporating a plurality of pattern registers 19 and switching between them, it is possible to change the test data. In addition, ROM (read-only memory) in which test data is written in advance
may be built-in. Furthermore, if a register or the like is provided in the write driver 20, test data can be held in the register, so that, for example, when the write enable signal WE* and the row address strobe signal RAS* are at low level, The test data can be written to a register in the write driver 20 or the pattern register 19. and,
It may be configured such that when only the row address strobe signal RAS* is set to low level, the read data from the memory cell array 10 and the data held in the pattern register 19 are compared in the discrimination circuit 25 to obtain discrimination information. .

[0042] In the above explanation, the invention made by the present inventor was mainly applied to dynamic RAM, which is the background field of application, but the present invention is not limited thereto, and is applicable to static RAM.
It can be widely applied to data processing devices such as M and other semiconductor memories, and microcomputers including the same.

The present invention can be applied to conditions including at least a memory cell array capable of storing data.

[0044]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in the logic circuit included in the determining means for determining the quality of the memory cell array based on read data from the memory cell array of test data written in the memory cell array and data held in the pattern register, the above-mentioned Since the above-mentioned pass/fail determination information can be compressed and outputted externally by an exclusive OR operation of the data read from the memory cell array and the data held in the pattern register, such dynamic RA
The M tester does not require a comparator to compare the read data from the memory cell array with its expected value, and the tester simplified in this way can test a large number of semiconductor memory devices. It can be done efficiently.

[Brief explanation of drawings]

[Fig. 1] Fig. 1 shows a dynamic R which is an embodiment of the present invention.
It is a block diagram of AM.

FIG. 2 is a circuit diagram showing a detailed configuration of main parts in FIG. 1;

FIG. 3 is an explanatory diagram of output data of main parts in this embodiment.

FIG. 4 is a block diagram of a dynamic RAM that is another embodiment of the present invention.

FIG. 5 is a block diagram of a dynamic RAM that is still another embodiment of the present invention.

[Explanation of symbols]

10 Memory cell array 11 Row decoder 12 Row address buffer 13 Column address buffer 14 Sense amplifier 15 Column selection circuit 18 Main amplifier 19 Pattern register 20 Write driver 21 Input buffer 22 Output driver 23 Control circuit 24 Selector 25 Discrimination circuit 26 Second logic circuit 27 First logic circuits 28-1 to 28-n Exclusive OR circuit 29 Exclusive OR circuit 30-1 to 30-n Inverters 31-1 to 31-n Selector 32 Exclusive OR circuit 34 First select register 35 Second select register 37 Row address counter 38 Address multiplexer 39 Column address counter 40 Address multiplexer 42 Selective logic inversion circuit

Claims (6)

[Claims] 1. A memory cell array capable of storing data, a holding means for holding test data of the memory cell array, and a write/read control means for controlling writing and reading of the test data to and from the memory cell array. a determining means for determining the quality of the memory cell array based on the read data from the memory cell array of the data written in the memory cell array by the write/read control means and the data held by the holding means; and this quality determination information. and an external output control means for controlling the external output of the memory cell array, and the determination means reduces the pass/fail determination information by an exclusive OR operation of the data read from the memory cell array and the data held by the holding means, and outputs the resultant information to the outside. A semiconductor memory device characterized by comprising a logic circuit for enabling output. 2. The logic circuit includes a first logic circuit for checking quality and a second logic circuit for checking the state of data.
and a logic circuit, wherein the first logic circuit selectively inverts the logic state of data read from the memory cell array on a bit-by-bit basis depending on the logic state of data held by the holding means. The second logic circuit includes a logic inversion circuit and an exclusive OR circuit that obtains an exclusive OR of the outputs of the selective logic inversion circuit, and the second logic circuit receives the read data from the memory cell array and the holding means. Claim 1, further comprising: a plurality of exclusive OR circuits for obtaining exclusive ORs with data held in bits; and an OR circuit for obtaining a logical sum of the plurality of exclusive OR circuits. semiconductor storage device. 3. The selective logic inversion circuit includes an inverter for inverting the logic of read data from the memory cell array bit by bit, and a logic inversion by the inverter depending on the logic state of the data held by the holding means. 3. The semiconductor memory device according to claim 2, further comprising a selector capable of selecting data and data before logic inversion. 4. The semiconductor memory device according to claim 1, wherein the read data used for the quality determination by the determining means is data before selection by a column selection circuit operated in response to a column address. . 5. The semiconductor memory device according to claim 1, wherein said external output control means includes a selector for selecting an external terminal used for externally outputting said quality determination information. 6. A row address counter that generates a row address, a column address counter that generates a column address, and only when testing the memory cell array,
6. The semiconductor memory device according to claim 1, further comprising an address multiplexer which supplies the output of the row address counter and the output of the column address counter to a subsequent stage circuit in place of externally input address signals.