JPH06282413A - Comparing circuit - Google Patents

Abstract

PURPOSE:To save an address space and register a reference comparison value by a simple procedure by connecting the data lines of a central processor to the address lines of a memory, connecting some of the address lines of the processor to the data lines of the memory, and storing a comparison result in an address that the reference comparison value in the memory indicates. CONSTITUTION:This circuit consists of the multiport memory 8 which has plural independerit address lines and data lines, the CPU 9 which have its data lines connected to the address lines 1 of the memory 8 and its address lines connected to the data lines 1 of the memory 8 and a decoding circuit, and a circuit 10 which outputs a memory select signal from an address that the CPU 9 outputs to the memory 8. Then the data lines of the CPU 9 are connected to the address lines 1 of the memory 8, and some of the address lines of the CPU 9 are connected to the data lines 1 of the memory 8; and the comparison result is stored in the address indicating the reference comparison value in the memory 8 and a signal to be compared is inputted to the address lines 2 of the memory 8, so that the signal to be compared can be compared with the reference comparison value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit for comparing bit patterns by a memory.

[0002]

2. Description of the Related Art Conventionally, a comparison circuit has been constructed by using a plurality of comparators and registers. However, as the number of comparison value bits to be compared increases and the number of comparison values increases,
There is a problem that the circuit scale becomes large. In order to deal with this problem, a memory-based comparator circuit described below has been used.

FIG. 4 is a block diagram showing a conventional comparison circuit. In the figure, 1 is a multiport memory having a plurality of independent address lines and data lines, and 2 is a CPU (central processing unit) connected to the memory 1. (Device) 3 is a decode circuit for outputting a memory selection signal to the memory 1 from the address output by the CPU 2. FIG. 5 is a block diagram showing another conventional comparison circuit. In the figure, 4 is a multi-port memory having a plurality of independent address lines and data lines, and 5 is a CPU (central CPU) connected to the memory 4. A processing unit), 6 outputs a memory selection signal to the memory 4 by inputting an address output from the CPU 5, and a decoding circuit 7 which outputs a comparison value latch enable signal to a comparison value latch circuit described later. A comparison value latch circuit for inputting a CPU output comparison value output from the CPU 5.

Next, the operation will be described. First, the conventional comparison circuit shown in FIG. 4 will be described. Here, for the sake of explanation, the reference comparison value which is a reference for comparison is set to 12h (h
Represents a hexadecimal number) and 56h, and if the comparison results are in agreement, 1 is obtained, and if they are not in agreement, 0 is obtained. Also, the address line of the memory 1 is 8 bits, CP
The U2 address line is assumed to be 16 bits wide.

First, the registration of the reference comparison values (12h, 56h) in the memory 1 will be described. The address line 1 of the memory 1 is connected to the address line of the CPU 2, and the data line 1 of the memory 1 is connected to the data line of the CPU 2. CPU
2 outputs a comparison circuit selection address (for example, 40h) to the decoding circuit 3 in the upper 8 bits of the address line to select the memory 1, and a reference comparison value (12h, 56h) in the lower 8 bits to the memory 1 Output to. Further, the CPU 2 outputs the registration data (1 which means coincidence) to the data line to the memory 1 and outputs the write control signal to the memory 1 to register data (1) at the addresses 4012h and 4056h. Is written. Here, the decoding circuit 3 decodes the input comparison circuit selection address (40h) and outputs a memory selection signal to the memory 1. Next, the CPU 2 selects addresses 4000h to 40ffh (memory 1 except the above two addresses).
The registration data (0 indicating non-coincidence) is written to all the addresses in.

Next, comparison of compared signals to be compared will be described. When the signal to be compared (for example, 12h) is input to the address line 2 of the memory 1, the data line 2 outputs 1 as a comparison result. If the compared signal is 78h, the data line 2 outputs 0 as a comparison result indicating a mismatch. Here, it is assumed that each signal (read signal or the like) necessary for reading the memory 1 is appropriately input.

The CPU 2 outputs the comparison circuit selection address to the address line and the number of bits of the reference comparison value may be arbitrary, but at least one bit is required for the comparison circuit selection address. Therefore, the maximum bit width of the reference comparison value is C
The bit width of the address line of PU2 is -1.

Next, another conventional comparison circuit shown in FIG. 5 will be described. Unlike the comparison circuit of FIG. 4 which outputs the reference comparison value from the address line of the CPU 2, this comparison circuit outputs the reference comparison value registered in the memory 4 to the CPU.
After being output from the data line 5 and stored in the comparison value latch circuit 7, the stored reference comparison value is input to the address line 1 of the memory 4. In this case, regardless of the number of bits of the comparison value, the address space can be realized with a fixed size.

Conventional examples of comparison circuits using a memory include, for example, Japanese Patent Laid-Open Nos. 59-121537 and 63-85930.

[0010]

Since the conventional comparison circuit is configured as described above, as the number of bits of the reference comparison value increases when registering the reference comparison value in the memory, the central processing unit of the central processing unit is increased. There is a problem that a wide address space is required. Further, in the comparison circuit improved from this, although the address space of the central processing unit can be saved, it is necessary to store the reference comparison value once in the latch circuit,
There is a problem that the procedure for registering the reference comparison value becomes complicated.

The present invention has been made to solve the above problems, and an object thereof is to obtain a comparison circuit which saves an address space of a central processing unit and can register a reference comparison value by a simple procedure. And

[0012]

According to another aspect of the present invention, there is provided a comparator circuit in which a data line of a central processing unit is first connected to an address line of a memory, and a part of the address line of the central processing unit is connected to a data line of the memory. By connecting to, the comparison result is stored in the address indicated by the reference comparison value in the memory, and then the compared signal is input to the address line of the memory to obtain the comparison result.

The comparison circuit according to the invention of claim 2 is
First, the data line of the central processing unit is connected to the address line of the memory, and a part of the data line of the central processing unit is connected to the data line of the memory, so that the comparison result is stored at the address indicated by the reference comparison value in the memory. Then, the compared signal is input to the address line of the memory to obtain the comparison result.

[0014]

According to the first aspect of the present invention, in the comparator circuit, the data line of the central processing unit is first connected to the address line of the memory, and a part of the address line of the central processing unit is connected to the data line of the memory. The reference comparison value and the compared signal can be compared by storing the comparison result in the address indicated by the reference comparison value and then inputting the compared signal to the address line of the memory.

In the comparison circuit according to the second aspect of the present invention, first, the data line of the central processing unit is connected to the address line of the memory, and a part of the data line of the central processing unit is connected to the data line of the memory. By storing the comparison result in the address indicated by the reference comparison value in the memory and then inputting the compared signal to the address line of the memory, the reference comparison value and the compared signal can be compared.

[0016]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of a comparison circuit according to the invention of claim 1, FIG. 2 is a diagram showing an operation at the time of registration of an embodiment of the comparison circuit according to the invention of claim 1, and FIG. FIG. 6 is a diagram showing an operation at the time of comparison of an embodiment of the comparison circuit according to the invention of FIG. In the figure, the same reference numerals as those of the conventional one indicate the same or corresponding portions, and the explanation thereof will be omitted. 8 is a multi-port memory having a plurality of independent address lines and data lines, 9 is a data line connected to the address line 1 of the memory 8, and an address line is connected to the data line 1 of the memory 8 and a decoding circuit 10 described later. A CPU (Central Processing Unit) 10 is a decoding circuit for outputting a memory selection signal to the memory 8 from an address output by the CPU 9.

Next, the operation will be described. Here, for the sake of explanation, the reference comparison value serving as a reference for comparison is AAh (h represents a hexadecimal number, “10101010” in binary), 1 if the comparison result is a match, and 0 if there is no match. Shall be obtained. Further, it is assumed that the address line of the memory 8 has an 8-bit width and the address line and the data line of the CPU 9 have an 8-bit width.

First, the reference comparison value (AAh) memory 8
The registration to is explained. In order to select the memory 8, the CPU 9 outputs a comparison circuit selection address (for example, "0011000") to the decoding circuit 10 in the upper 7 bits of the 8 bits of the address line, and the registration data (indicating a match) in the lower 1 bit. “1”) is output to the data line 1 of the memory 8. That is, "00110001" (31h) is output to the address line of the CPU 9.

Further, the CPU 9 judges that there is a match when the reference comparison value (that is, a value matching this value is input to the memory 8 on the data line. Here, "1010101".
The registration data (1) is written in the address AAh of the memory 8 by outputting 0 ″ (AAh)) to the address line 1 of the memory 8 and activating the write control signal to output to the memory 8. Here, the decode circuit 10 decodes the upper 7 bits of the input comparison circuit selection address (31h), activates the memory selection signal, and outputs it to the memory 8.

Next, the CPU 9 removes the above address AAh 00
In order to write the registration data (0 indicating non-coincidence) from the address h to the address ffh (all addresses in the memory 8), 30h (the upper 7 bits are “0011000”,
Registered data "0") is output to the lower 1 bit, and data from 00h to ffh excluding the address AAh is output to the data line.

Next, comparison of compared signals to be compared will be described. This is similar to the conventional comparison circuit, and when a signal to be compared (for example, AAh) is input to the address line 2 of the memory 8, the data line 2 outputs 1 as a comparison result. Also, the compared signal is 78h
Then, 0 is output from the data line 2 as a comparison result indicating a mismatch. Here, it is assumed that each signal (read signal or the like) necessary for reading the memory 8 is appropriately input. As mentioned above, the required address is 3
Two of 0h and 31h is sufficient. The maximum bit width of the reference comparison value is the bit width of the data line of the CPU 9.

Example 2. An embodiment of the invention of claim 2 will be described below. Although the registration data is output from the address line of the CPU 9 in the first embodiment, the same comparison circuit can be obtained by using 1 bit of the data line of the CPU 9.
In this case, one address (for example, 30h) for selecting the memory 8 is sufficient as the necessary address. Also, the maximum bit width of the reference comparison value is the bit width of the data line of the CPU 9 minus 1.

Example 3. Hereinafter, claim 1 or claim 2
Another embodiment of the invention will be described. In the first or the second embodiment, the registered data is 1 indicating a match and 2 of 0 indicating a mismatch.
Although the value is used, by increasing the number of bits, for example, in the case of 2 bits, it is possible to perform four kinds of comparisons such as mismatch, match in group 1, match in group 2 and match in group 3.

Example 4. Hereinafter, claim 1 and claim 2
Another embodiment of the invention will be described. In Examples 1 to 3, a multiport memory having a plurality of independent address lines and data lines was used, but the address line and the data line are provided to the CPU side and the compared signal side at the time of registration and comparison of the reference comparison value. By providing a signal switching circuit for switching, a memory having only one port for each address line and data line can be used.

[0025]

As described above, according to the first aspect of the present invention, in the comparison circuit, the data line of the central processing unit is first connected to the address line of the memory, and a part of the address line of the central processing unit is connected to the memory. By connecting to the data line, the comparison result is stored in the address indicated by the reference comparison value in the memory, and then the compared signal is input to the address line of the memory to compare the reference comparison value and the compared signal. Since it was configured as
The address space of the central processing unit can be saved, and a comparison circuit capable of registering the reference comparison value can be obtained by a simple procedure.

According to the second aspect of the invention, in the comparison circuit, the data line of the central processing unit is first connected to the address line of the memory, and a part of the data line of the central processing unit is connected to the data line of the memory. As a result, the comparison result is stored at the address indicated by the reference comparison value in the memory, and then the reference comparison value and the comparison signal are compared by inputting the comparison signal to the address line of the memory. There is an effect that a comparison circuit capable of registering a reference comparison value can be obtained by a simple procedure. Further, since only one address is required, the address space of the central processing unit can be saved more effectively.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a comparison circuit according to the invention of claim 1;

FIG. 2 is a diagram showing an operation at the time of registration of an embodiment of the comparison circuit according to the invention of claim 1;

FIG. 3 is a diagram showing an operation at the time of comparison of an embodiment of the comparison circuit according to the invention of claim 1;

FIG. 4 is a configuration diagram showing a conventional comparison circuit.

FIG. 5 is a configuration diagram showing another conventional comparison circuit.

[Explanation of symbols]

 8 memory 9 CPU (central processing unit)

Claims (2)

[Claims] 1. A central processing unit which outputs a reference comparison value serving as a reference for comparison from a data line at the time of data registration and outputs registered data from an address line, and the reference comparison value at the time of data registration. A comparison circuit comprising a memory in which the registration data is written in an address, and when the data is compared, the registration data is read out as a comparison result from the address indicated by the compared signal to be compared with the reference comparison value. 2. A central processing unit that outputs a reference comparison value and registration data as a reference for comparison from a data line when registering data, and the registration data is written to an address indicated by the reference comparison value when registering data. And a memory for reading the registered data as a comparison result from the address indicated by the compared signal to be compared with the reference comparison value during data comparison.