JP3308575B2 - Extension memory bank address automatic setting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management system for an information processing apparatus, and more particularly, to a system for setting a bank address of a memory board in a computer system connecting a plurality of additional memory boards.

[0002]

2. Description of the Related Art An information processing apparatus such as a personal computer is designed so that a plurality of input / output expansion boards and additional memory boards can be connected in order to increase the versatility of a computer system. When connecting an additional memory board among these connected function expansion boards, it is necessary to set an address (a predetermined fixed area on a memory map of a computer system) of the additional memory board to the system.

Conventionally, this type of setting employs a method in which a switch that can be set arbitrarily is provided on a memory board to be added, and an address used by each board is determined by setting this switch artificially. ing.

[0004]

As described above, in the conventional bank address setting method, it is necessary to manually set a switch on the memory board when performing expansion, and a system user sets the switch. Manuals and the like, and there is a possibility that an erroneous setting may be performed due to a human error at the time of setting, which may cause a malfunction, damage to a memory or a board, and the like.

An object of the present invention is to provide an additional memory bank address automatic setting method which facilitates setting of a bank address of a memory board to be added to a computer system.

[0006]

In order to achieve the above object, an automatic expansion memory bank address setting method according to the present invention is provided for an additional memory bank address used in a computer system.
Any memory can be added on the board.
Initialization at system initialization on a functional memory board
Memory capacity on the memory board
Set the memory bank address range of the
Means for outputting a setting permission signal to Moribodo, before
Of the memory bank address range output from the setting means
Compare the data with the address data supplied by the CPU
The memory on the memory board is selected when accessing the memory
Means for outputting a memory access signal indicating that the operation has been performed
And the following to cascade multiple memory boards
Setting when the first memory board is accessed
Bank add to the next memory board based on the enable signal
Means for generating an address setting permission signal.
You .

[0007]

[0008]

[0009]

The data indicating the capacity is received from the memory on the board, and a signal indicating the memory access is generated by a combination of the register, the adder, and the comparator. Further, the register, adder, and comparator generate a setting permission signal for the next bank address memory. The setting permission signals are connected in series, and the expanded memory is sequentially accessed to sequentially set the bank address.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram for explaining an additional memory bank address automatic setting method according to an embodiment of the present invention.
FIG. 3 is a diagram showing an example of a memory map according to the embodiment;
FIG. 4 is a diagram showing an example of a method of adding a memory board according to the present embodiment, FIG. 4 is a diagram showing an example of cascade connection of the memory boards of the present embodiment, and FIG. 5 is an operation timing chart of the present embodiment. .

Referring to FIG. 1 register 1 and No. 1 No. 1 adder 2 and No. 1 2 adders 3 and N
o. No. 3 adder 4 and No. 3 1 comparator 5 and No. 1
2 comparator 6 and No. 2 3 Comparator 7 and N
o. 4 comparator 8, NAND gate 9, inverter 10, AND gate 11, OR gate 12,
No. And two registers 13.

No. No. 1 register 1 contains No. 1 comparator 5 and No. 1 A bank address start value S1 for one adder 2 is generated from an address S2 supplied from the CPU and an input signal I supplied from another board. A latch type is used as this type of register.

No. No. 1 adder 2 is No. 1 register 1
The memory capacity data D1 given from an arbitrary memory mounted on the board is added to the bank address start value S1 supplied from the The memory bank address / end value S2 is given to the comparator 5 and the start value of the next bank address is set to No.
2 to the comparator 6.

No. 2 adder 3, no. 3 adder 4
No. Memory capacity data D2 or D3 given from any memory mounted on the board in the same manner as 1 adder 2.
Is supplied to the comparators 6, 7, or 8 in addition to the value input from the adder 2 or 3 in the preceding stage.

No. The upper 5 bits indicating the memory bank address in the address S2 supplied from the CPU are No. 1 in the comparator 5. 1 register 1 and No. 1 A comparison is made as to whether or not the condition created by the values S1 and S3 supplied from the 1 adder 2 is satisfied. As a result, when the condition is satisfied, a memory access signal M1 indicating that the memory on the board has been selected is generated.

No. 2 comparator 6 and No. 2 No. 3 comparator 7 Similarly to the comparator 5, the value S3 or S4 supplied from the adder 2 or 3 is compared with the address S2 supplied by the CPU, and a memory access signal M2 or M3 is generated.

No. No. 4 comparator 8 is No. 4 The value S5 supplied from the third adder 4 is compared with the address S2 supplied by the CPU, and the generation data S6 of the signal II serving as a setting permission signal for the next memory board is generated.

The NAND gate 9 NANDs the MRCO signal S7 indicating the memory access and the MWCO signal S8.
Then, the signal is supplied to the AND gate 11.

The inverter 10 logically inverts the signal S 9 generated by the NAND gate 9, and 2 registers 13
The clock operation signal is generated.

The AND gate 11 has a No. 4 and the signal S9 generated by the NAND gate 9 and the signal S6 given from the comparator 8 2 The signal S output from the register 13
And 10 to generate a signal II for another memory board.

No. 2 register 13 is AND gate 1
1 and the output of its own and the OR gate 12
And input as data. Then, a signal S10 is generated by the timing generated by the NAND gate 9 and the inverter 10.

As shown in the cascade connection example of the memory boards in FIG. 4, an output signal II of another board (the preceding board in the order of memory setting) is connected to the input signal I. On boards other than the memory board, these signals are connected through.

In FIG. When the output signal II of the memory board No. 1 is connected to the other board through the board other than the memory board, 2 is the input signal I of the memory board.

Next, the following operation will be described with reference to FIG. 2, FIG. 3, FIG. 4, and FIG.

In the system of the memory map as shown in FIG.
It is assumed that one memory board on which two MB memories and one 2 MB memory are mounted is added, and bank addresses are set.

Here, H represents a hexadecimal number. The order of the memory added on the board is 1 MB of memory, 2 MB of memory next, and 1 MB of memory last, counting from the lowest address of the memory area.

As shown in FIG. 2, these memory areas store values from addresses 23 to 20,
The first is represented by 0010 and 0011, and the third is represented by 0100. In the case of the first board, the input signal I
Is given from the main system. This signal I for the first sheet
Is set to be active ("1") when the first memory of the additional memory is first accessed.

When the first board is accessed for the first time, the No. 1 board shown in FIG. No. 1 register 1 passes through the address given from the CPU. 1 adder 2 and N
o. 1 and output to the comparator 5. No. 1 adder 2
Receives the data D1 of the memory capacity from the first of the memories mounted on this board, adds the data D1 to this address, and adds the data D1. 1 is supplied to the comparator 5.

At this time, the memory capacity data is stored in the connector C connected to the memory M mounted on the board B as shown in FIG.
From the signal assigned in advance.
When the memory capacity is 1 MB, it is allocated at the time of board design, such as 0001 for 2 MB, 0010 for 3 MB, and 0011 for 3 MB.

No. In the first comparator 5, the address signal S2 from the CPU is set to the No. 1 signal. 1 from the register 1 and the signal S1. When the following condition is satisfied with the signal S3 from the 1 adder 2, the memory access signal M1 is activated.

When S1 ≦ S3 and S1> S3 At this time, the first memory on the board can be accessed.

No. When the first memory access is completed, the 1-register 1 latches and holds the bank address that has been accessed up to that time.

No. 2 adder 3, no. 3 adder 4
The memory capacity data D2 or D3 from each memory is added to the output of the adder 2 or 3 at the preceding stage, and the condition input values of the comparators 6 and 7 are output and held.

The adders 2, 3, 4 and the comparator 5,
By using a combination of 6 and 7, it becomes possible to mount memories M of an arbitrary memory capacity on the board B in an arbitrary order as shown in FIG.

No. 4 comparator 8 receives the address signal S2 supplied from the CPU and the No. 4 signal. Compare with the signal S5 (start value of the bank address of the next memory board) supplied from the third adder 4, and if they are equal, output signal S6
Outputs 1. At this time, as shown in the operation timing chart of FIG. 5, the MRCO signal S7 / NWCO signal S
8 becomes active in the case of memory access, the output signal S9 of the NAND gate 9 outputs 1.

In addition, No. 2 register 13 sets the Q output to 0 and the Q (bar, logical inversion) to 1 at system initialization.
Is output, and the output obtained by ORing the output of the AND gate 11 with its own output is used as the data input. Therefore, the output does not change as it is. These three signals are ANDed by an AND gate to output 1 as signal II.

According to the operation timing chart of FIG.
When the RCO signal S7 / MWCO signal S8 rises,
No. 2 register 13 receives 1 from OR gate 12. For this reason, No. The two registers 13 invert and output and hold the output signals so far. This allows
The AND gate 11 changes to 0, and the No. 2 registers 13
Will not be output until is initialized.

By the above operation, the signal II becomes active only when the next memory board is first accessed, and does not become active thereafter.

The signal II thus produced is used as an input signal I from the preceding board and an output signal II to the next board, as in the cascade connection of memory boards in FIG. 4 (series connection). Then, by sequentially performing memory access in the added memory area in ascending order of addresses, bank addresses can be set without duplication.

[0040]

As described above, the present invention has a memory bank address setting circuit using a register which can be set by memory access and a capacity discriminating circuit for an additional memory, and cascade-connects a plurality of the same memory boards. By doing so, it is possible to automatically set the bank addresses of multiple memory boards by memory access without human labor, eliminating the need for manual setting and reducing human error. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an additional memory bank address automatic setting method according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a memory map according to the embodiment;

FIG. 3 is a diagram illustrating an example of a method of adding a memory board according to the embodiment;

FIG. 4 is a diagram illustrating a cascade connection of the memory boards according to the embodiment.

FIG. 5 is a timing chart illustrating the operation of the present embodiment.

[Explanation of symbols]

 1 No. 1 register 2 No. 1 adder 3 No. 2 adder 4 No. 3 adder 5 No. 1 comparator 6 No. 2 Comparator 7 No. 3 Comparator 8 No. 4 Comparator 9 NAND gate 10 Inverter 11 AND gate 12 OR gate 13 No. 2 registers

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-184559 (JP, A) JP-A-57-97155 (JP, A) JP-A-59-217282 (JP, A) JP-A-5-97 165710 (JP, A) Introduction of EMS memory board, Electronics Life, Japan, Japan Broadcasting Publishing Association, December 1, 1989, 1988, pp. 37-51 (58) Fields surveyed (Int. . ^7, DB name) G06F 12/06

Claims (1)

(57) [Claims] 1. An extension method used in a computer system.
Memory on the memory board.
Memory boards that can be added to the memory are initialized at system initialization, and
Judgment of memory capacity and memory bank address of memory board
Set the range and allow settings for other memory boards
Means for outputting a signal, and a memory bank address range output from the setting means
Data and the address data supplied by the CPU.
The memory on the memory board is selected when accessing the memory
Means for outputting a memory access signal indicating that the operation has been performed
When, a plurality of identical memory boards for cascading
When the next memory board is accessed for the first time,
Bank address for the next memory board based on the
Means for generating a dress setting permission signal .