JPS5975498A - Memory redundant system - Google Patents

Abstract

PURPOSE:To prevent the congestion of data at readout by setting separately a readout address and write address to a memory unit so as to switch continuously the data of a main memory and a standby memory at write. CONSTITUTION:A comparator 5 is selected by a signal on a signal line 102 at the data write to a memory 1, and when the address from a line 100 is coincident with a set write address in a set device 3, the comparator 5 transmits a coincidence sigal S2, which becomes a memory selecting permission signal S4 via an OR gate 6, and the memory 1 is accessed with an address signal on the line 100. At this readout from the memory 1, only when the readout designating address on the line 100 is coincident with the set readout address in the setting device 2, the memory 1 is selected and a data is outputted on a line 103. In connecting the memory unit like this to a CPU7 via a bus as the main memory 8 and the waiting memory 9, the continuous switching of the write data to boath the memories is attained and no data congestion at readout takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a backup memory (
The present invention relates to a memory redundancy system having a standby memory (standby memory), and particularly to a memory unit suitable for use in such a system.

Generally, in this type of memory redundancy system, when the main memory goes down and is switched to standby memory, the data in the standby memory is always the same as the data in the main memory so that the switch can maintain data continuity. It is desirable that they match.

Conventionally, in such cases, a method has been known in which different addresses are assigned to the main memory and the standby memory, and the data in the standby memory is updated by software after the data in the main memory is updated, but in this case, the same operation as Fi is performed twice. This increases the load on the software, which has the disadvantage of reducing the performance of the central processing unit, such as slowing down the calculation speed of the central processing unit.

On the other hand, it is also possible to allocate the same address to the main memory and standby memory and update data in these two memories at the same time. There is a drawback that data is read out and so-called data tampering occurs.

The present invention was made under these circumstances, and provides a memory redundancy system that does not reduce the performance of a central processing unit and does not cause data tampering, and that is suitable for use in such a system. The entire purpose is to provide a memory unit.

Its feature is that the write address and read address of the memory unit can be set individually, and when a redundant system is configured using this memory unit, the write addresses of both units must match each other. By setting the read addresses to be different from each other, it is possible to prevent data from collapsing during reading and to ensure data continuity when switching from one unit to the other unit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a redundant memory unit according to an embodiment of the present invention. In the figure, 1 is a memory bank, 2 is a memory bank top address setting device, and 3 is a memory bank.
#i Memory bank write start address setter, 4 and 5 are comparators, 6 is an OR gate, 100 is an address line, 1
01 is the hospital output signal line, 102 is the write signal line, 103t
A data line, Sl is a read address match signal, S2 is a write address match signal, 83) is an address signal within a puncture, and S4 is a memory selection permission signal.

That is, the setters 2 and 3 are each connected to a comparator 4.5, and the address line 100 is likewise connected to a comparator 4.5. Roughly speaking, a read signal line 101 t "t=8 included signal line 102 is connected to each of the comparators 4 and 5. Here, when writing data to the memory bank 1, a signal is input to the signal line 102. When the address given via the address l/M100 matches the setting write address set in the setting device 3, the ratio!2 device 5 outputs a 74 write address match signal S2.
This signal S2 passes through the OR gate 6 and becomes the memory selection permission signal S4. This allows the use of the memory bank 1 and makes it accessible by the address signal from the address line 100. In other words, memory bank 1
For example, the first address of “1000” is address I
If the address designation signal applied via the X/J1100 is '1500', the setter 3 is preset to '1000'. Comparator 5 compares the most significant digits (or bits) of the specified address and the set address, and in this case, since both are t1n, address match signal S2 and memory selection permission signal S4 are output, and memory 1 is selected. is allowed.

As a result, only "500'" of the address designation signal "1500" is applied as the in-bank address signal S3 of memory bank 1, a desired address is selected, and predetermined data is written via the data line 103. Comparator 5 only compares the most significant digit or bit, so only one #'i is shown in the figure, but if the next digit or bit needs to be compared, it will be compared accordingly. Of course, as many comparators as the number of comparators are provided (1).Also, when reading out a booter from this memory unit 1, the read designation address given via the address line 10 (1) is set to Memory bank 1 is selected only when the address matches the read setting address set in advance in Lfj
I love being pushed.

FIG. 2 is a system configuration diagram showing a case where a memory redundancy system is configured using such an external memory unit; , 1° That is, the memory units as described above serve as the main memory unit 8 and the standby memory unit 9, and the bus signal line 1
0 in parallel to the central processing unit 7. At the bottom of such a groove, if the write addresses of the main memory unit 8 and the standby memory unit 9 are set to the same address, and the read addresses are set to different addresses, then the Data 1, main memory 8 and standby memory 9 are treated as if they were one memory (address selection is performed and the same data is stored at the same address. On the other hand, central processing unit 7 stores data from memory 8 or 9). When reading, since the read addresses are different from each other, only data from one of the memories is outputted to the bus signal line 10, so the above-mentioned data collision does not occur. The processing unit 7 normally updates the data in the standby memory 9 automatically by simply accessing the main memory 8, and when the main memory 8 dies due to a failure etc., the central processing unit 7 updates the data for reading data. By simply changing the base address of the main memory B from the standby memory 9, memory units can be easily switched while maintaining data continuity.

As described above, according to the present invention, the read address and write address can be set separately for the memory unit, so even when configuring a memory redundancy system using such a memory unit. Since the data in the main memory and the standby memory can be easily matched during writing, the switching can be performed completely continuously, while also preventing data from collapsing during reading. .

It should be noted that the present invention can be applied not only to the above-described memory redundancy but also to the case of making general input/output devices that generally require writing and reading of data redundant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a redundant memory unit according to an embodiment of the present invention, and FIG. 2 is a system block diagram showing a memory redundancy system using the memory unit of the present invention. Code explanation

Claims (1)

[Scope of Claims] 1) A memory redundancy system comprising at least two sets of memory units in which write addresses and read addresses can be individually set, wherein at least the write addresses of both units are made to match each other, A memory redundancy system characterized in that reading addresses are made different from each other to prevent data from being mixed up during reading and to maintain data continuity when switching from one unit to the other unit being used. . 2. In the memory redundancy system according to claim 1, each of the memory units has a write address setting means, a read address setting means, and a writing designated address or read designated address, respectively. A memory redundancy system comprising an address check means for comparing the address with a set address and permitting access to the memory when the address matches.