JPH09161488A - Address converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the comparison processing time of input data by providing an address converter with a memory part and a comparison part and reading addresses of the memory part sequentially to compare an input data with a memory block internal data by the comparison part. SOLUTION: A data latch section 10 latches and holds four input data being sent at a fixed cycle. Comparison data read out of a memory block 1A are inputted into corresponding comparison parts 20. The comparison parts 20 compare the input data with memory block internal data. The results of the comparison of the comparison parts 20 enter an address generation part 30 and an enable generation part 40. When the memory data matching with the input data exist, the generation part 30 outputs an address of the memory data of the memory block. On the other hand, when the matched memory data exists, the generation part 40 outputs a match-enable signal. Outputs of the generation part 30 and the generation part 40 are sent to a higher-order device and a processing is performed corresponding to the results of the outputs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device, and more particularly to input data and a CAM memory (Con).
The present invention relates to an address conversion device that compares internal data of a tent Addressable Memory) and outputs the output address of the CAM memory in which the corresponding data is stored when they match.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a configuration example of a conventional device. In the figure, 1 is a CAM memory. The CAM memory 1 is a memory in which, for example, 8-bit data is provided in the data direction by the number of words (addresses) in the vertical direction. Reference numeral 2 is a comparison unit which is provided for each word and compares the word with the input data. These comparators 2 compare the words in bit units. For example, assuming that the data has an 8-bit configuration of D0 to D7, a bit comparator is provided for each of D0 to D7. That is, the comparison units 2 shown in the figure each include eight bit comparators. Then, when all the bits match, a match signal is output. When the operation of the device shown in the figure is normal, there is only one matching word, so a matching signal is output from the specific comparing section 2 of the comparing sections 2. The outputs of these comparison units 2 are sent to the host device,
The output address of the CAM memory corresponding to the matched word is obtained.

[0003]

As described above, the conventional address translator has a pair of comparators for each CAM word and compares all CAM words in parallel. Then, the output data is only the CAM address. Further, the comparison effective bit of the input data is fixed. Therefore, in the conventional circuit configuration, M words, N
M × N comparators are required for a bit CAM memory, and when a large-scale memory is included, the circuit scale becomes too large. Also, the matched CAM
Since only the address is output, there is a problem that the reliability of the output address cannot be guaranteed when a duplicate match (a match signal of a plurality of words is output) occurs due to a failure or the like. Furthermore, there is a problem in that it is not possible to compare data of bit widths arbitrarily, and there is no versatility.

The present invention has been made in view of the above problems, and can suppress the circuit scale, maintain the reliability of output addresses, and compare data of arbitrary bit widths. It is an object of the present invention to provide an address translation device that can perform.

[0005]

FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 13 are denoted by the same reference numerals. In the figure, reference numeral 1 denotes a CAM memory (memory unit), which is divided into memory blocks 1A for each predetermined number of words. Reference numeral 3 is a memory control unit that controls writing of data to the CAM memory 1 and control of reading data, 10 is a data latch unit that latches input data by the number of memory blocks 1A, and 20 is a block corresponding to each memory block 1A. A comparing unit 30 is provided which compares the input data with the data in the memory block. The receiving unit 30 receives the output of the comparing unit 20 and, according to the comparison result of these comparing units 20, the CA that matches the input data.
An address generation unit 40 for outputting an output address of the CAM memory corresponding to the word data of the M memory 1, 40 receives the output of the comparison unit 20, and receives the input data and the memory block internal data according to the comparison result of the comparison unit 20. Is an enable generation unit that determines a match, an unmatch, and a duplicate match with and outputs a match enable and a duplicate match enable signal according to the output address.

According to the configuration of the present invention, the memory unit 1
The addresses can be sequentially read, and the comparison unit 20 can compare the input data with the memory block internal data. Further, since the data latch section 10 latches the comparison target data in the input data and holds it until the end of the comparison, parallel processing control of the input data can be performed. Also,
Each memory block 1A operates in parallel and memory block 1
Addresses in A are read sequentially and one memory block 1
Since the comparison processing can be performed on A by one comparison unit 20, the circuit scale can be reduced. Further, it is possible to shorten the comparison processing time of the input data by dividing the memory block and processing a plurality of input data in parallel.

Further, a data latch unit for latching input data by a number corresponding to the memory block is provided,
The comparison operation of the input data latched by the corresponding comparison unit 20 and the memory block internal data is performed in parallel.

According to the structure of the present invention, the data latch unit 10 holds the data corresponding to the number of the memory blocks 1A until the end of the comparison operation, whereby the comparison operation can be performed in parallel and the comparison processing time can be reduced. It can be shortened.

Further, the data in the CAM memory unit is provided with a mask bit, and the comparison bit can be designated by the mask bit so that the comparison bit width of the input data can be changed.

According to the structure of the present invention, by providing the mask bit, the data width of the input data to be compared can be varied by setting the mask bit to "0" by the number of bits of the input data.

In this case, the output of the comparison unit 20 is received, and according to the comparison result of these comparison units 20,
It is characterized in that an address generation unit 30 is provided which outputs a CAM address corresponding to word data of the CAM memory that matches input data.

According to the structure of the present invention, it is possible to obtain the output address corresponding to the word data of the CAM that matches the input data. Further, receiving the output of the comparison section 20, it is determined whether the input data and the internal data of the memory block are matched, unmatched or duplicated according to the comparison result of the comparison section 20, and the match enable signal is output according to the output address. It is characterized in that an enable generation unit for outputting an overlap match enable signal is provided.

According to the structure of the present invention, by providing the enable generation section, it is possible to output the match enable signal and the duplicate match enable signal in accordance with the output address, and the matched output output from the address generation section 30. By processing it together with the address data OADD, the reliability of the matching data can be improved.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. The same thing as FIG.
The same reference numerals are given. The device shown in the figure is provided with four memory blocks 1A. In response to this, the data latch unit 10 latches and holds four input data,
Four pieces of data HW-A to HW-D are output. The respective data HW-A to HW-D are stored in four comparison units 20 (hereinafter abbreviated as comparison units 0 to 3).

The CAM memory (memory section) 1 is divided into four memory blocks 1A. The first block (memory block 0) is 1 from CH0 to CH127.
28 word data are stored, and the second block (memory block 1) has 12 channels from CH128 to CH255.
Eight word data are stored, the third block (memory block 2) stores 128 word data from CH256 to CH383, and the fourth block (memory block 3) contains 128 word data from CH384 to 511. The word data of is stored. That is, this CAM memory 1 stores a total of 512 word data.
The memory control unit 3 includes a CAM memory 1 and an address generation unit 3
0 and the address data ADDR is output to the enable generation unit.

From the comparison unit 0, comparison results MT-A0-MT
-D0 is the comparison result MT-A1 to MT- from the comparison unit 1.
D1 indicates comparison results MT-A2 to MT-D from the comparison unit 2.
2 is output from the comparison unit 3 as MT-A3 to MT-D3, and is input to the address generation unit 30 and the enable generation unit 40. The address generator 30 outputs a match output address OADD, and the enable generator 40 outputs a match enable signal MTENB and a duplicate match enable signal FMTENB. The operation of the device configured as described above will be described below.

The data latch unit 10 latches and holds four pieces of input data IDATA sent at a constant cycle. These four data HW-A to HW-D are simultaneously input in parallel to the comparators 0 to 3, respectively. On the other hand, address data 0 to 127 are sequentially input to the memory blocks 0 to 3 from the memory control unit 3. That is, the address data 0 to 127 output from the memory control unit 3 are commonly entered in each of the memory blocks 0 to 3. Memory block 0
The memory blocks 3 are commonly accessed by the memory control unit 3, but the data stored in each memory block is different.

The comparison data CMP-0 to CMP-3 read from these memory blocks 1A are input to the corresponding comparison units 20. The comparison unit 0 compares the four data HW-A to HW-D with the memory data CMP-0, and the comparison unit 1 compares the four data A to D and the memory data C.
The comparison unit 2 compares the MP1 with the four data HW-A-
The HW-D and the memory data CMP2 are compared, and the comparison unit 3
Is four data HW-A to HW-D and memory data CM
Compare with P-3.

The comparison result MT-Ai of these comparing sections 20.
MT-Di (i = 0 to 3) enters the address generation unit 30 and the enable generation unit 40. The address generator 30
If there is memory data that matches the input data, the address of the memory data in that memory block is output as the output address OADD. On the other hand, the enable generation unit 40 outputs the match enable signal MTENB when the matching memory data exists. If duplicated memory data exists, the duplicate match enable signal FMTENB is output. The outputs of the address generation unit 30 and the enable generation unit 40 are
For example, it is sent to a higher-level device and processing is performed according to these output results.

According to the present invention, the addresses of the memory unit 1 can be sequentially read, and the comparison unit 20 can compare the input data with the memory block internal data. Further, since the data latch section 10 latches the comparison target data in the input data and holds it until the end of the comparison, parallel processing control of the input data can be performed. In addition, each memory block 1A operates in parallel, addresses in the memory block 1A are sequentially read, and one comparison unit 20 can perform comparison processing for one memory block 1A, so that the circuit scale can be reduced. You can Further, it is possible to shorten the comparison processing time of the input data by dividing the memory block and processing a plurality of input data in parallel.

As described above, in the present invention, the CAM memory 1
Is divided into four memory blocks, and the number of comparison units 20 corresponding to these memory blocks is provided to compare the input data with the memory data, so that the circuit scale can be suppressed. In addition to the output address, the match enable signal MTENB and the duplicate match enable signal FMT
Since ENB is output, the reliability of the output address can be maintained. Further memory block 1
Since each word data in A has a mask bit, it is possible to create comparison data of only the data width.
Data of arbitrary bit width can be compared.

FIG. 3 is a block diagram showing a configuration example of the data latch unit 10. In the figure, 11 is an input data ID
Data latch circuit for latching ATA, data latch circuit A for latching data A, data latch circuit B for latching data B, data latch circuit C for latching data C, latch data D The circuit is a data latch circuit D. Input data IDATA
Are input to the respective data latch circuits 11. A latch control enable signal CNTL-ENB is input to the data latch circuit 11 from the memory control unit 3. The data latch circuit A has a CNTL-EN
B-A has CNTL-ENB- in the data latch circuit B.
B, CNTL-ENC are input to the data latch circuit C, and CNTL-ENB-D are input to the data latch circuit D, respectively, and they function as data latch signals.

In this embodiment, the comparison target bit width of the input data is 32 bits, the data latch circuit A outputs the data HW-A (31: 0), and the data latch circuit B outputs the data HW-. B (31: 0) is output, and the data HW-C (31:
0) is output, and data H is output from the data latch circuit B.
WD (31: 0) is output. Here, (31:
0) indicates that there are 32 bits from 0 to 31 (same below). Explaining the operation of the circuit configured in this way,
It is as follows.

FIG. 4 is a time chart showing the input / output operation of the data latch unit 10. 32-bit comparison target data (a) is input in time series as shown in the figure. First,
Data A is input, then data B is input, then data C is input, then data D is input. When data A is input, latch control enable signal CNTL
-ENB-A is input to the data latch circuit A, (b)
As shown in, the 32-bit data A from HW-A (0) to HW-A (31) is latched. The data latch circuit A holds the latched data A until the comparison operation by the comparison unit 20 is completed. The shaded area in the figure indicates the data retention period (the same applies hereinafter).

Similarly, when data B is input next, the latch control enable signal CNTL-ENB-B is input.
Is input to the data latch circuit B, and 32-bit data B from HW-B (0) to HW-B (31) is latched as shown in (c). The data latch circuit B holds the latched data A until the comparison operation by the comparison unit 20 is completed. Hereinafter, the data C and the data D are similarly latched.

According to this embodiment, the data latch unit 10 holds the data of the number of the memory blocks 1A until the end of the comparison operation, so that the comparison operation can be performed in parallel and the comparison processing time can be increased. Can be shortened.

FIG. 5 is a diagram showing a configuration example of the CAM memory (memory section) 1. As mentioned above, in this example,
512 word data of 0 to 511 are divided into 4 blocks, and 128 blocks are set in each memory block 1A.
Individual word data are stored. Since one word data is 64 (comparison data + mask data) bits,
The memory capacity of one memory block 1A is 128 words × 64 bits. For example, the memory block 0 stores word data of ADD0 to ADD127. As for the output address, ADD0 is "0", AD
D127 is associated such as "127". Word data from ADD0 to ADD127 is stored in the memory block 1. The output address is
ADD0 is associated with "128" and ADD127 is associated with "255". The configuration of the remaining memory blocks 2 and 3 is also the same.

FIG. 6 is a diagram showing a configuration example of data in the memory. In this embodiment, in addition to 32 bits for storing original data, mask bits having the same capacity, that is, 32 bits are provided. Bit 0 to bit 31 in the figure are areas for storing data, and bit 32 to bit 63
Are the mask bits. For example, if the data length of the data part is 18 bits, "0" is set in the mask bits from bit 32 to bit 50, and "1" is set in the remaining mask bits. That is, the mask bit is set to "0" only for the required data length, and the remaining unnecessary bits are masked by setting the mask bit to "1".

By configuring the memory in this way,
The data width of the input data to be compared can be changed by setting the mask bit to "1" by the number of bits of the input data by the mask bit.

FIG. 7 is a block diagram showing a configuration example of the comparison section 20. In the figure, 21a is the data HW-A (31: 0) from the data latch unit 10 and 32 bits (31: 0) of the data portion of the word data CMP (63: 0) output from the CAM memory 1. Comparing circuit receiving 2
1b is the data HW-B (3
1: 0) and 32 bits (3) of the data portion of the word data CMP (63: 0) output from the CAM memory 1.
1: 0), a comparison circuit 21c receives the data latch unit 1
Comparing circuit for receiving data HW-C (31: 0) from 0 and 32 bits (31: 0) of the data portion of the word data CMP (63: 0) output from the CAM memory 1, 21d is data Data HW-D from the latch unit 10
The comparison circuit receives (31: 0) and 32 bits (31: 0) of the data portion of the word data CMP (63: 0) output from the CAM memory 1. As the comparison circuits 21a to 21d, for example, exclusive OR gates are used. Although the figure shows only one line,
In reality, the comparison circuit 21 compares 32-bit word data with 32-bit input data (HW-A to HW-D) for each corresponding bit. Therefore, these comparison circuits 21a to 21d are composed of 32 bit comparators.

22a is an output of the comparison circuit 21a (31:
0) and the word data C output from the CAM memory 1
A mask circuit for masking the mask bits (63:32) of MP (63: 0) in a bit-corresponding manner, and 22 b is a comparison circuit 2.
A mask circuit for masking the output (31: 0) of 1b and the mask bits (63:32) of the word data CMP (63: 0) output from the CAM memory 1 in bit correspondence, and 22c is the output of the comparison circuit 21c. (31: 0) and C
Word data CMP (6 output from the AM memory 1
A mask circuit for masking the mask bits (63:32) of 3: 0 in bit correspondence, 22d is the output (31: 0) of the comparison circuit 21d, and the word data CMP (63: 0) output from the CAM memory 1. ) Mask bits (63: 3)
2) is a mask circuit for masking and in correspondence with bits. As the mask circuits 22a to 22d, for example, OR gates are used. Although only one line is shown in the figure, the mask circuit 22 actually compares the output of the comparison circuit 21 of 32 bits with the mask bit of 32 bits for each corresponding bit. Therefore, these mask circuits 22a to 22d are composed of 32 OR gates.

23a is an AND gate for receiving 32 data from the mask circuit 22a, and 23b is a mask circuit 22.
AND gate for receiving 32 data from b, 23c
Is an AND gate for receiving 32 pieces of data from the mask circuit 22c, and 23d is an AND gate for receiving 32 pieces of data from the mask circuit 22d. The AND gates 23a to 23d output "1" only when the 32 pieces of input data are all "1", that is, only when the word data stored in the CAM memory 1 and the input data match. . The output of the AND gate 23a is MT-A, the output of the AND gate 23b is MT-B, and the AND gate 23c.
Output is MT-C, and output from AND gate 23 is MT
-D. The operation of the circuit thus configured will be described as follows.

The data latched from the data latch unit 10 is 4
The individual pieces of data HW-A to HW-D are input, HW-A to the comparison circuit 21a, HW-B to the comparison circuit 21b, and HW-H.
-C enters the comparison circuit 21c, and HW-D enters the comparison circuit 21d. On the other hand, from the memory block 1A of the CAM memory 1, the word data CMP (63: 0) of the address accessed by the memory control unit 3 is output,
The lower 32 bits are commonly input to the comparison circuits 21a to 21d. The upper 32 bits of the word data CMP are mask bits, and these mask bits are mask circuits 22a to 22.
Common to d.

The comparison circuit 21a simultaneously compares the input data HW-A and each bit of the word data, and the comparison result (31: 0) enters the mask circuit 22a. Mask circuit 2
The above-mentioned mask bit is input to the other input of 2a. If the bit width of the input data is 32 bits,
Since all 32 bits of the mask bit are "0", in this case, the output of the comparison circuit 21a directly passes. The output of the mask circuit 22a is the AND gate 23.
Enter a. When the word data and the input data match, the output 32 bits of the mask circuit 22a all become "1", so the AND gate 23a outputs a value "1" indicating that the word data and the input data match. Output as MT-A. The case of the comparison circuit 21a has been described above, but the same applies to the other comparison circuits 21b to 21d. The case of the comparison unit 0 has been described above, but since this comparison operation is the same for the remaining comparison units 1 to 3, the detailed operation is omitted.

FIG. 8 is a block diagram showing a configuration example of the address generator 30. In the figure, reference numeral 31 is an encoder for receiving and encoding the output MT (3: 0) of each comparison unit 20. As is clear from FIG. 7, the comparison unit 20 is MT-
Four comparison data A to MT-D are output. The comparison unit 0 has MT-A0, MT-B0, MT-C0, MT-D.
0, the comparison unit 1 is MT-A1, MT-B1, MT-C.
1, MT-D1, and the comparison unit 2 MT-A2, MT-B.
2, MT-C2, MT-D2, the comparison unit 3 MT-A
3, MT-B3, MT-C3, MT-D3 are output respectively. The first encoder 31 has MT-A0, MT
The four comparison result bits MT-A (3: 0) of -A1, MT-A2, and MT-A3 are input, and the second encoder 3
1 is MT-B0, MT-B1, MT-B2, MT-B.
The four comparison result bits MT-B (3: 0) of 3 are input, and the third encoder 31 inputs MT-C0 and MT-C.
1, MT-C2, MT-C3 four comparison result bits M
TC (3: 0) is input, and four comparison result bits MT-D (3: 0) of MT-D0, MT-D1, MT-D2, MT-D3 are input to the fourth encoder 31. Is entered.

Reference numeral 32a is a latch circuit which latches the address data ADDR (6: 0) output from the memory control unit 3 by a latch enable signal. The latch circuit 3
Four 2a are provided corresponding to latch enable A to latch enable D. Address data ADDR
Are commonly input to these latch circuits 32a.
Reference numeral 32b is a latch circuit that latches the data output from each encoder 31 by a latch enable signal. Four latch circuits 32b are provided corresponding to latch enable A to latch enable D. 33
Is a multiplexer which receives the output (6: 0) of each latch circuit 32a and the output (1: 0) of the latch circuit 32b and outputs a 9-bit output address signal OADD (8: 0). The output of the multiplexer 33 is 9 bits because the number of word data stored in the CAM memory 1 is 512 (512 = 2 ⁹ ). The operation of the circuit thus configured will be described as follows.

First, the comparison result of the input data HW-A is M
It is output as T-A (MT-A output from 3: 0 comparison unit 0 to comparison unit 3) and enters the first encoder 31 and 2
Encoded into bit data. FIG. 9 is a diagram showing a truth table of the encoder 31 at this time. This encoder outputs "00" when MT (3: 0) is input as "0001", and "001X" (X is 1 or 0
However, if the input is
When "1" is output, when "01XX" is input, "10" is output, when "1XXX" is input, "11" is output, and when "0000" is input, It outputs "00".

The output of the first encoder 31 is latched in the latch circuit 32b by the latch enable A signal. On the other hand, the address signals ADDR (6: 0) of 0 to 127 output from the memory control unit 3 are latched in the latch circuit 32a by the same latch enable A signal. The output (6: 0) of the latch circuit 32a and the output (1: 0) of the latch circuit 32b are multiplexed by the multiplexer 33, and the 9-bit output address signal OADD is output.
It is output as (8: 0). This output address becomes the output address of the word data in the CAM memory 1 that matches the input data.

At the next timing, the input data HW-B is latched by the latch enable B signal in the latch circuit 32a, while the second encoder 31 is latched in the latch circuit 32b.
Output is latched and these data are
The output address of the CAM multiplexed in 3 is output.
Thereafter, similarly, the output addresses of the input data HW-C and the input data HW-D are output in time series.

According to this embodiment, it is possible to obtain the output address corresponding to the CAM word data that matches the input data. FIG. 10 is a block diagram showing a configuration example of the enable generation unit 40. In the figure, reference numeral 41 is an enable generation circuit provided corresponding to each comparison result signal MT-A to MT-D. These enable generation circuits 41 receive the 4-bit comparison result signals MT-A to MT-D and output the MTE signal and the FMTE signal. Reference numeral 42 is a first multiplexer that multiplexes the MTE signals output from each enable generation circuit 41, and 43 is a second multiplexer that multiplexes the FMTE signals output from each enable generation circuit 41. First multiplexer 4
2 outputs a match enable signal MTENB signal, and the second multiplexer 43 outputs a duplicate match enable signal FMTENB.

In each latch enable generation circuit 41, 50 is a 4-bit comparison result signal MT- * (* is A to
It is an OR gate that receives D). The latch enable signal is output from the OR gate 50. That is, the latch enable A from the first enable generation circuit 41.
The second enable generation circuit 41 outputs a latch enable B signal, the third enable generation circuit 41 outputs a latch enable C signal, and the fourth enable generation circuit 41 outputs a latch enable D signal. , Is input to the address generator 30 shown in FIG.

51 latches the output of the OR gate 50,
A first latch circuit 52 for holding until the end of the comparison, and 52 is an AND gate for receiving the output of the OR gate 50 and the output of the latch circuit 51. 54 is a 4-bit comparison result signal MT
Priority encoder for receiving-*, 55 is a comparison circuit for comparing the comparison result signal MT- * with the output of the priority encoder 54, 53 is an OR gate for receiving the output of the AND gate 52 and the output of the comparison circuit 55, and 56 is the OR gate. It is a second latch circuit for latching the output of 53. Then, the first latch circuit 51 outputs the MTE signal, and the second latch circuit 56 outputs the FMTE signal. The operation of the circuit thus configured will be described as follows.

If "1" is set in any bit of MT-* (3: 0), the output of the OR gate 50 is "1".
become. This “1” is latched by the first latch circuit 51. The output of the first latch circuit 51 is input to the first multiplexer 42. The multiplexer 42 outputs a match enable signal MTENB indicating that there is matching data. On the other hand, when there is no matching data, MT- * is "0" in all 4 bits, and the output of the OR gate 50 is "0". This "0" is the first
Is latched by the latch circuit 51, is output as the MTE signal, and enters the first multiplexer 42. When all the four enable generation circuits 41 output data mismatches, the match enable signal MTENB output from the first multiplexer 42 becomes "0", indicating that there is no data match.

On the other hand, if data coincidence occurs at a plurality of addresses at different times during the comparison time, the output of the first latch circuit 51 and the output of the OR gate 50 both become "1", and the AND gate 52 becomes "1". Is output.
The output of the AND gate 52 enters the OR gate 53,
The OR gate 53 outputs "1" indicating that duplicate data coincidence has occurred, is latched by the second latch circuit 56, is output as the FMTE signal from the second latch circuit 56, and is output by the second multiplexer 43. to go into.

If data coincidence occurs at the same time during the comparison time, MT-* (3: 0) means that "1" is set in a plurality of bits. The priority encoder 54 is provided to identify that "1" is set in a plurality of bits at the same time. FIG.
1 is a diagram showing a truth table of the priority encoder 54. The priority encoder 54 generates "0001" when the input data IN is "0001", and "00" when the input data IN is "001X".
10 "is generated, and when the input data IN is" 01XX "," 0100 "is generated and the input data IN is" 1XX ".
In the case of X "," 1000 "is generated, and in the case of the input data being" 0000 "," 0000 "is generated.

That is, this priority encoder 54
Outputs data in which even if "1" is set in a plurality of bits of 4 bits, "1" is set in only one arbitrary bit. Therefore, when the output of the priority encoder 54 and the original data are compared by the comparison circuit 55, data mismatch always occurs when "1" is set in a plurality of bits. Here, when "1" is set to a plurality of bits, the comparison circuit 55 outputs "1". The output of the comparison circuit 55 enters the OR gate 53 and outputs "1". This "1" is latched by the second latch circuit 56 and enters the second multiplexer 43 as an FMTE signal. As a result, the second multiplexer 43 outputs "1" when a match occurs between adjacent data, or when a plurality of data matches during the simultaneous comparison time, and a duplicate match occurs. To notify.

According to this embodiment, the match enable signal and the duplicate match enable signal can be output according to the output address. Therefore, the matched output address data AO output from the address generation unit 30
By processing together with DD, the reliability of the matching data can be improved.

FIG. 12 is a time chart showing the overall operation of the present invention. In the figure, (a) is the input data ID
ATA, (b) the first input data HW-A latched by the data latch unit 10, (c) the second input data HW-B latched by the data latch unit 10,
(D) shows the third input data HW-C latched by the data latch unit 10, and (e) shows the fourth data HW-D latched by the data latch unit 10.

(F) shows the address data ADDR sequentially output from the memory control unit 3, and (g) shows the word data CMP-0 output from the memory block 0.
(H) is the word data CMP1 output from the memory block 1, (i) is the word data CMP2 output from the memory block 2, and (j) is the word data CMP-3 output from the memory block 3. Indicates.

(K) is a comparison result MT-A0 to MT-A of the first data HW-A output from the four comparison units 20.
3, (l) is the comparison result MT-B0 to MT-B3 of the second data HW-B output from the four comparing units 20,
(N) shows the comparison results MT-D0 to MT-D3 of the fourth data HW-D output from the four comparison units 20.
(O) is the output address OADD output from the address generation unit 30, (p) is the match enable signal MTENB output from the enable generation unit 40, and (q) is the duplicate match output from the enable generation unit 40. The enable signal FMTENB is shown.

Bits to be compared of the input data (32
4 bits (HW-A ~) in the data latch unit 10.
HW-D). At the same time as the data input, the memory control unit 3 outputs the read address ADDR to each of the memory blocks 0 to 3 and
~ Read comparison data and mask bits CMP-0 to CMP-3 to the address of the memory block 3.

In the comparison unit 0, HW-A to HW-D and C
The comparison with MP-0 and the mask are performed in the comparison unit 1 by HW-
A to HW-D and CMP-1 are compared, and the mask is compared, and in the comparison unit 2, HW-A to HW D and CMP-2 are compared,
And a mask, and HW-A to HW-D and CM in the comparison unit 3.
Comparison with P-3 and masking are performed. HW-A starts at address 0 and ends at address 127. HW-
B starts at address 32 and goes to address 127, then returns to address 0 and ends at address 31. HW-
The C and HW-D are similarly accessed.

Here, DATA-An and C of the input data
It is assumed that the data at address 3 of MP-0 matches. The comparator 0 outputs "1" to MT-A0 as shown in (k). In the address generation unit 30, the read address ADDR that matches is latched by the first latch circuit 32a, and the lower 7 bits are output as "0000011". The upper 2 bits encode the comparison result MT-A (3: 0) by the first encoder 31. MT-A is "0
001 ”is encoded by the encoder 31 to“ 00 ”
(See FIG. 9).

Therefore, the output address OADD of the data DATA-An becomes "000000011". This output address is output as shown in (o) after the completion of comparison with all the words. Similarly, input data DATA-B
If n and the word data of the address 95 of the CMP-1 match, the output address OADD output from the address generation unit 30 is “011011111”.

When a data mismatch occurs, the enable generator 40 generates a match enable signal, and "0"("1" when matched) is output to MTENB in synchronization with the output address. Similarly, when a duplicate match of data occurs, "1" is output to FTENB in synchronization with the output address.

The device of the present invention is normally used for data mismatch (CA
If it does not match any word data in M memory 1), the output address is "0000000" which is all 0s.
00 "is output. In that case, if only the address is output,
It is indistinguishable from the one matched at the address "000000000000". Therefore, the match enable MTENB is set to "0" to notify that there is no match.

Further, in the case of overlapping match, the output address is the smallest matched address. As it stands, it cannot be said that the data is reliable. Therefore, the overlap match enable signal FMTENB is set to "1".
By setting to, it notifies that a duplicate match has occurred. This makes it possible to determine that the output address is not reliable data.

According to the present invention, the mask bit in the CAM memory 1 is used in order to make the bit width of the input comparison target data variable. For example, when the input data is 20 bits, "1" is set to the 20 to 31 bits of the mask bits in the memory. In the comparison unit 20 shown in FIG. 7, the comparison result of the bits for which “1” is set in the mask bit is ignored. Then, only the comparison result for 20 bits is output. Since the mask circuit 22a of FIG. 7 is composed of an OR gate, if the mask bit is "1", the output of the mask circuit 22a becomes "1" regardless of the data from the comparison circuit 21a, and the don't care. Will be (ignored).

In the above-described embodiment, the case where the number of word data is 512 and the CAM memory 1 is divided into four memory blocks of 128 words has been described as an example. However, the present invention is not limited to this, and the CAM memory 1 having an arbitrary number of words can be made into a memory block with an arbitrary number of words as one block, and the present invention can be applied to these memory blocks. Needless to say.

[0060]

As described above in detail, according to the present invention, the input data is compared with the internal data of the CAM, and when they match, the CAM address corresponding to the word data of the matched CAM is output. In the address translation device, the memory is divided into a plurality of memory blocks, and a memory is provided for each block corresponding to the memory block, and a comparison unit for comparing input data with data in the memory block, The addresses of the memory units are sequentially read out, and the comparing unit compares the input data with the memory block internal data, whereby the addresses of the memory unit are sequentially read out, and the comparing unit compares the input data with the memory block internal data. You can Further, since the data latch unit latches the comparison target data in the input data and holds the comparison target data until the end of the comparison, parallel processing control of the input data can be performed. In addition, each memory block operates in parallel, addresses in the memory block are sequentially read, and
Since the comparison processing can be performed for one memory block by one comparison unit, the circuit scale can be reduced. Furthermore,
By dividing the memory block and processing a plurality of input data in parallel, it is possible to shorten the processing time for comparing the input data.

Further, a data latch unit for latching input data by a number corresponding to the memory block is provided,
By performing the parallel operation of the comparison between the input data latched by the corresponding comparison unit and the internal data of the memory block, the data latch unit holds the data of the number of memory blocks until the end of the comparison operation. The operations can be performed in parallel processing, and the comparison processing time can be shortened.

Further, the data in the CAM memory unit is provided with a mask bit, and the comparison target bit is designated by the mask bit, and the comparison target bit width of the input data is made variable, so that the mask bit is provided. Thus, the data width of the input data to be compared can be changed by setting the mask bit to "0" by the number of bits of the input data.

In this case, when the outputs of the comparison units are received, the C corresponding to the word data of the CAM memory that matches the input data according to the comparison results of the comparison units.
By providing the address generation unit that outputs the AM address, the output address corresponding to the CAM word data that matches the input data can be obtained.

Further, receiving the outputs of the comparison units, it is determined whether the input data and the internal data of the memory block are matched, unmatched or duplicated according to the comparison results of the comparison units, and the match enable signal is output according to the output address. By providing the enable generation unit that outputs the duplicate match enable signal, it is possible to output the match enable signal and the duplicate match enable signal according to the output address, and to output the matched output address data OADD output from the address generation unit. By performing the processing together, the reliability of the matching data can be improved.

As described above, according to the present invention, it is possible to provide an address conversion device capable of suppressing the circuit scale, maintaining the reliability of output addresses, and comparing data of arbitrary bit widths. It is possible and has a great practical effect.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a data latch unit.

FIG. 4 is a time chart showing an input / output operation example of a data latch unit.

FIG. 5 is a diagram showing a configuration example of a memory unit.

FIG. 6 is a diagram showing a data configuration example in a memory.

FIG. 7 is a block diagram illustrating a configuration example of a comparison unit.

FIG. 8 is a block diagram illustrating a configuration example of an address generation unit.

FIG. 9 is a diagram showing a truth table of an encoder.

FIG. 10 is a block diagram illustrating a configuration example of an enable generation unit.

FIG. 11 is a diagram showing a truth table of a priority encoder.

FIG. 12 is a time chart showing the overall operation of the present invention.

FIG. 13 is a block diagram showing a configuration example of a conventional device.

[Explanation of symbols]

 1 CAM memory (memory unit) 1A memory block 3 memory control unit 10 data latch unit 20 comparison unit 30 address generation unit 40 enable generation unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masaki Kira 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Makoto Yamada 2-3-9 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Digital・ Technology Stock Company in-house (72) Inventor Sai Kasugai 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu Digital Technology Stock Company In-house (72) Inventor Hiroshi Ishiwata 2-3, Shin-Yokohama, Yokohama-shi, Kanagawa No. 9 Fujitsu Digital Technology Stock Association In-house

Claims (5)

[Claims] 1. An address conversion device that compares input data with internal data of a CAM memory and outputs a CAM address corresponding to the matched word data of the CAM memory when the memory data is divided into a plurality of memory blocks. Memory unit and a comparing unit that is provided for each block corresponding to the memory block and that compares the input data with the data inside the memory block. The addresses of the memory unit are sequentially read and the comparing unit inputs the input data. And an address translation device that compares internal data of the memory block. 2. A data latch unit for latching input data by a number corresponding to the memory block is provided, and the comparison operation between the input data latched by the corresponding comparison unit and the memory block internal data is performed in parallel processing. The address translation device according to claim 1, which is characterized in that. 3. The data in the memory unit is provided with a mask bit, and the comparison bit can be designated by the mask bit so that the comparison bit width of the input data can be changed. Address translation device described. 4. An address generation unit is provided which receives the outputs of the comparison units and outputs the CAM address corresponding to the word data of the CAM memory that matches the input data according to the comparison results of the comparison units. The address translation device according to claim 1, which is characterized in that. 5. A match enable signal is received according to an output address of the comparison unit, which receives the outputs of the comparison units and determines a match, an unmatch, and a duplicate match between the input data and the internal data of the memory block according to the comparison results of the comparison units. 2. The address translation device according to claim 1, further comprising an enable generation unit that outputs a duplicate match enable signal.