JPH01185712A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate the initialization of all main memory devices by performing the address setting of each of the main memory devices by comparing address data fetched from a data bus in advance with the address data from an address bus by an initialization control signal from a central processing unit, and setting the data as the address data when coincidence is obtained. CONSTITUTION:An address data holding means fetches and holds prescribed address data from the data bus 32 selectively by the initialization control signal 33 from the central processing unit 20. And a comparator 13 compares the address data inputted from the address bus 31 with the address data held at the address data holding means 11 and 12, and when they coincide, the data is outputted to an address setting circuit as the address data. At the time of initializing all main memory devices 10, for example, by holding (all 0s) at the address data holding circuits of all main memory devices 10, and setting the address data of the address bus 31 at (all 0s), all main memory devices 10 can be initialized simultaneously. In such a way, the initialization of all main memory devices 10 can be performed rapidly.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICABILITY The present invention is utilized in the information communication field.

The present invention relates to an information processing device, and particularly to initialization of its main storage device.

〔overview〕

The present invention provides an information processing device that includes a central processing unit and a plurality of main storage devices connected to the central processing unit via an address bus and a data bus. In response to an initialization control signal from the processing device, the address data read in advance from the data bus is compared with the address data input from the address bus, and if they match, the entire main memory is set as address data. This allows the device to be initialized quickly.

[Conventional technology]

Conventionally, the address of the main storage device of this type of information processing device has been fixedly set within the system in order to select one of a plurality of main storage devices.

Therefore, when initializing all the main storage devices, the initialization is performed while increasing the addresses of all the main storage devices.

[Problem that the invention seeks to solve]

In the conventional information processing device described above, when initializing the main memory, the main memory is initialized while sequentially increasing the addresses, so it takes a very long time to complete the initialization. There was a drawback that it took a while.

An object of the present invention is to provide an information processing device that can quickly initialize a main storage device by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides an information processing device comprising a central processing unit and a plurality of main storage devices connected to the central processing unit via an address bus and a data bus, wherein the main storage devices are connected to the central processing unit through an address bus and a data bus. address data holding means that selectively captures and holds the contents of the data bus in response to an initialization control signal; compares the address data input from the address bus with the address data held in the address data holding means, and matches the address data held in the address data holding means; The present invention is characterized in that it includes an address comparison circuit that outputs address data when

[Effect]

The address data holding means selectively takes in and holds predetermined address data from the data bus in response to an initialization control signal from the central processing unit. The address comparison circuit compares the address data inputted from the address bus with the address data held in the address data holding means, and outputs the data as address data to the address setting circuit when they match.

As a result, when initializing all main memory devices, the address data holding circuits of all main memory devices are made to hold, for example, "all 0s", and when the address data of the address bus is set to "all 0s", Main memory is initialized at the same time.

Therefore, it is possible to quickly initialize the primary storage device.

The fixed address settings for each main memory device are as follows:
This is done by setting the address data held in the address data holding circuit to predetermined data.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the connection of address registers.

In FIG. 1, this embodiment includes a central processing unit 20, an address bus 31 and a data bus 3 connected to the central processing unit 20.
2, the main memory 10 selectively captures and holds the contents of the data bus 32 in response to an initialization control signal 33 from the central processing unit 20. Address register 11 and AND gate 12 as address data holding means
and an address comparison circuit 13 that compares the address data input from the address bus 31 with the address data held in the address register 11 and outputs the address data as address data if they match. Note that 14 is a control circuit and 15 is a storage element.

FIG. 2 shows a case where the address bus 31 consists of 4 bits and four main storage devices 10 are connected to it, and one input of each AND gate 12 is connected to each bit of the address bus 31. The other input is commonly connected to the address control signal 33.

The feature of the present invention is that in FIG. 1, the initialization control signal 33
This is because an address data holding means consisting of an AND gate 12 connected to a data bus 32 and an address register 11 connected to a data bus 32, and an address comparison circuit 13 are provided.

Next, the operation of this embodiment will be explained.

When initializing the information processing apparatus of the present embodiment, the central processing unit 20 enables the initialization control signal 33 and sets the bit position of the main memory 10 connected to each bit of the address bus 31. Enable it and set the data bus 32 to "all 0s". Thereafter, the initialization control signal 33 is set to "0". At this time, the cashier storage device 10 in the information processing device
The address register 11 inside holds the contents of the data bus 32 and is set to "all 0s".

When initializing any one of the main storage devices 10, the central processing unit 20 initializes the memory for one device while sequentially increasing the value of the address bus 31. At this time, the address data from the address bus 31 of the other main memory devices 10 is also "all 0", and as mentioned above, the contents of each address register 11 are "all O", so each address comparator 13 At the same time, the outputs of the main storage devices 10 become "all 0", and when the initialization of one device is completed, the initialization of all main storage devices 10 is performed simultaneously.

Thereafter, the initialization control signal 33 is enabled again, the bit position of the address bus 31 corresponding to the main memory 10 is enabled, and the contents of the data bus 32 are written into the address register 11. Subsequently, by sequentially changing the contents of the data bus 32 and writing them into the address register 11, the address of the main memory device 10 can be fixedly set within the information processing device.

〔Effect of the invention〕

As explained above, the present invention sets the address registers to the same address data when initializing the main storage devices, so that a write instruction to any one of the main storage devices can be sent to the address bus. Since this is a write instruction for the main storage device connected to the main storage device, the time required to initialize the main storage device can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a connection example of the address register. 10... Main memory device, 11... Address register,
12...AND gate, 13...Address comparison circuit, 14...Control circuit, 15...Storage element, 20...
・Central processing unit, 31...address bus, 32...
Data bus, 33... initialization control signal.

Claims (1)

[Claims] 1. A central processing unit (20), and a plurality of main storage devices (1) connected to the central processing unit via an address bus (31) and a data bus (32).
0), wherein the main memory device includes address data holding means (11, 12); and an address comparison circuit (13) that compares the address data input from the address bus with the address data held in the address data holding means and outputs the address data as address data if they match. Information processing equipment.