KR100209883B1 - Reproducing apparatus and method for high speed selection - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed sorting and reproducing apparatus and method for shortening the access time of recorded contents and reproducing only the desired contents in a device for reproducing with a CD or IC card or the like as a recording medium. The present invention divides the recording medium into a plurality of virtual tracks of a plurality of segments and records the contents for each segment. In other words, in the case of a recording medium of a language learner in which multiple languages are recorded, it is recorded in English for A segment, Japanese for B segment, German for C segment, and Korean for D segment. When one of the segments of an arbitrary track is selected through the user's key operation, the segment data in the selected track is read and stored in the corresponding segment memory, and the selected segment data is reproduced and output. The segment memory stores corresponding segment data of a plurality of tracks, and can selectively reproduce segment data in a required track at any time.

Description

High speed sorting playback device and method

FIG. 1 (a) is a diagram for explaining the recording format of a digital recording medium used in the present invention, and FIG. 1 (b) is a diagram for explaining the recording format of a table of contents (TOC) area.

2 is a block diagram showing an embodiment of a fast sort playback apparatus according to the present invention.

3 is a block diagram showing another embodiment of the fast sorting and reproducing apparatus according to the present invention.

4 is a detailed view showing a memory unit in the fast sorting / reproducing apparatus of the present invention.

5 is an operation timing diagram for explaining a process of selectively reproducing data of the 100th A track.

6 is an operation timing diagram for explaining a process of selectively reproducing data of track A from the 100th consecutively.

7 (a) is an example of a process of accessing data of the 100th track "A", Figure 7 (b) is an example of a process of accessing data of the 101st "A" track while the main memory is full, 7 (c) is a diagram illustrating an example of a process of accessing data of the 101st " A " track stored in the main memory.

* Explanation of symbols for main parts of the drawings

11, 21: recording medium 14: memory

15: data expansion unit 16: data output unit

17: key control unit 18: system control unit

41: buffer memory 42: read / write controller

43: main memory 44: I / O

45: multiplexer

The present invention relates to an apparatus and method for reproducing recorded contents using a CD (Compact Disc) or an IC card as a recording medium, and more particularly, to selectively reproduce recorded contents and to search for desired contents at high speed. A high-speed sorting and reproducing apparatus and method for reproducing the same are provided.

Most of the commercially available devices as language learners use tape as a medium. However, in the case of using the tape, it is difficult to wait while winding the tape forward and backward when specifying a specific section, and it is difficult to accurately reach the desired part. On the other hand, when a plurality of languages such as English and Korean are mixed and recorded on a track of a tape, it is difficult to select and listen to only one language.

Accordingly, an object of the present invention is to solve the above problems and to search a desired section at high speed, to form a plurality of virtual tracks on a recording medium so that a particular language can be selected and listened to, and a plurality of segments within the virtual tracks. The present invention provides a fast sorting / playback method in which contents are recorded for each segment area by storing regions, and the recorded contents are stored in the memory for each segment area at the time of reproduction and selectively read directly from the memory for playback.

Another object of the present invention is to provide an apparatus for implementing the above-described fast sorting reproduction method.

In order to achieve the above objects, the fast sorting / reproducing method of the present invention comprises a TOC area and a data area, and the data area is composed of a plurality of virtual tracks of a plurality of segments, and records data for each segment in each virtual track. The TOC area includes a first step of selecting a portion to be reproduced from a recording medium defining a start address of each segment in the virtual track and a pointer of the start address, and using the information defined in the TOC area in the first step. A second step of sequentially reading segment data from an arbitrary virtual track including the selected portion and storing the segment data in segments; and reading the segment data in the random virtual track stored in the second stage and selecting the first segment Selecting only segment data corresponding to the third step; and The segment data selected in step 3 to the original and a fourth step of reproducing restored.

The high speed sorting and reproducing apparatus of the present invention for achieving another object of the present invention comprises a TOC area and a data area, and the data area is composed of a plurality of virtual tracks of a plurality of segments and records data for each segment in each virtual track. The TOC area receives a recording medium defining a start address for each segment in the virtual track and a pointer of the start address, a key operation unit, and a key operation signal of the key operation unit, and the information defined in the TOC area of the recording medium. A system control unit for controlling the overall operation of each component by using a control unit, and reading data stored in a data area of the recording medium according to the control of the system control unit and storing the data by segment, and segment data in a desired virtual track among the stored segment data. A memory unit that reads only the data, and data read from the memory unit And means for restoring and reproducing the original.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 (a) is a diagram for explaining the recording format of the digital recording medium used in the present invention, and FIG. 1 (b) is a diagram for explaining the recording format of the TOC area. Here, the recording medium uses a CD or IC card or the like.

In FIG. 1 (a), the recording medium area is largely divided into a TOC area for data management and a data area in which actual data exists. The data area is divided into a number of virtual tracks (1000 in this case) between the data start point (S) and the end point (E), and each virtual track is divided into four segment areas “A, B, C, D”. do. Here, the "A, B, C, D" segment areas are the same size, each address is given, and can be recorded for each area. For example, English in “A” segment areas A1 to A1000 in 1000 virtual tracks, Japanese in “B” segment areas B1 to B1000, and German in “C” segment areas C1 to C1000. Korean and the like can be recorded in the, and “D” segment areas D1 to D1000.

On the other hand, in Fig. 1 (b), the TOC area indicates the beginning of the position where the "A, B, C, D" segment areas exist in the virtual tracks (1 track to 1000 tracks) in the data area on the recording medium. A1 ~ D1000 ”Track Start Address is defined as 4 bytes. In addition, "1 to 1000" track start address point representing the position where the start address of the head segment area in each virtual track is defined among the positions where the "A1 to D1000" track start address is defined in the TOC area is defined as 1 byte. .

2 is a block diagram showing an embodiment of a fast sorting / playback apparatus according to the present invention. As shown, the reproducing apparatus of the present invention uses a CD 11 as a recording medium, a pickup section 12 for reading data from the CD 11, and a digital signal processing section for extracting only pure data from the read data. Signal Processor (DSP) 13 is provided. The DSP 13 stores data, reads the stored data, and a memory unit 14, and a data extension unit 15 which expands the data read from the memory unit 14 and outputs the data through the data output unit 16. Are connected in turn. The reproducing apparatus of the present invention also includes a key control unit 17 and a system control unit 18 for controlling the overall operation of the memory unit 14 in accordance with the key operation signal.

3 is a block diagram showing another embodiment of the fast sorting / reproducing apparatus according to the present invention. As shown in Fig. 2, the IC card 21 is used instead of the recording medium CD 11, which is configured substantially the same as that in Fig. 2, and includes a connector 22 for connecting the IC card 21 to the main body. do. Here, the same reference numerals are used for the same components as those in FIG.

The operation of the fast sorting / reproducing apparatus of the present invention configured as described above will be described in more detail with reference to FIGS. 4 to 7.

First, in the initial play state, the system control unit 18 reads the contents recorded in the TOC area in the recording medium such as the CD 11 or the IC card 21. The user selects a part to be played back through the key manipulation of the key manipulation section 17. For example, when the user selects the 100th of the 1000 virtual track “A, B, C, D” segments through the key control unit 17, the system control unit 18 receiving the key operation signal is read. The TOC area of Fig. 1 (b) is searched. The system controller 18 first finds the 100th virtual track start address point defined by 1 byte in the TOC area, and then finds the start address of the segment "A100" defined by 4 bytes at that point in the TOC area. The system control unit 18 transfers the pickup unit 12 to read data stored in the position indicated by the start address from the CD 11 or directly assigns an address to the IC card 21 to read the data. At this time, the data of the "A100, B100, C100, D100" segments of the position are read continuously. The read data X is input to the memory unit 14, and the memory unit 14 is configured as shown in FIG.

4 is a detailed view of the memory unit 14 in the apparatus of FIGS. 2 and 3. As shown, the memory unit 14 includes a buffer memory 41 comprising four buffers BUFA to BUFD for storing, for each segment, input data X read from an arbitrary virtual track, and the system control unit 18. Read / write controller 42 comprising a plurality of AND products AND1 to AND6, OR1 to OR4, and inverter INV1 for controlling the reading and writing of the buffer memory 41 according to the control of ). In the memory unit 14, the main memory includes four memories 43A to 43D for storing a plurality of segments for each data read from the buffer memory 41 under the read / write control of the read / write controller 42. And an input / output unit 44 comprising a plurality of three-phase buffers and an inverter INV2 for preventing data collision between the buffer memory 41 and the main memory 43, and the input / output unit 44. It is configured to include a multiplexer 45 for selectively outputting the segment-specific data read from the main memory 44 through the control of the system controller 18.

In FIG. 4, the input data X is simultaneously input to the buffers BUFA to BUFD of the buffer memory 41, and the buffers BUFA to BUFD are read / write controller 42 and the system controller 18. According to the control of the corresponding segment data of the input data (X) in order to store. Here, the case where the data X of the 100th "A, B, C, D" track is input as shown in FIG. 5 (a) will be described first.

In the read / write controller 42, the logical multipliers AND1 to AND4 receive the first clock clk1 of FIG. 5 (b) from the system controller 18 in common, and the first multiplier AND1 to AND4 are input from the system controller 18. Each of the clock enable signals ① to ④ of 5 degrees (c) is input and logical-operated. Thus, the logical AND operation signal of the AND multipliers AND1 to AND4 alternates to the buffers BUFA to BUFD in the buffer memory 41 through the logical ORs OR1 to OR4. The same valid write clock (ⓛ ~ ⓞ) is applied. Each valid write clock (buffers BUFA to BUFD to which ⓛ ~ ⓞ in FIG. 5 (d) is applied in turn receives the input data X “A, B, C, D” in FIG. 5 (a). At this time, the system control unit 18 assigns addresses to the buffers BUFA to BUFD through a common address bus, while the four buffers BUFA to BUFD have “A, B,” in the 100th track. When all segment data of C, D ”are stored, the data of the 101st " A, B, C, D " track can be accessed from the recording medium 11 and 21 before being stored in the buffer memory 41. The data of the 100th “A, B, C, D” track stored in 41 is quickly read.For this purpose, the AND product AND6 of the read / write controller 42 is moved from the system controller 18 to the fifth. A second clock clk2 having a half cycle period of the first clock clk1 of FIG. 2B is input, and the clock enable signal 5 of FIG. 5E is inverter from the system controller 18. 5th inverted by (INV1) The logical enable operation of the logical enable element AND6 is performed by receiving the clock enable signal (6) of f), and thus the buffers BUFA through BUFD through the logical oligos OR1 to OR4. Is applied to the valid read clock (⑦) of Fig. 5 (g), and the 100th " A, B, " stored in the buffers BUFA to BUFD according to this valid read clock (7) of Fig. 5 (g). The data of the C, D " tracks are read at the same time (see FIG. 5 (h)) and input to the input / output unit 44. The input / output unit 44 is applied to the fifth diagram (Fig. The input / output control signal ⓐ of i) is applied to four three-phase buffers connected to the output side of the main memory 43, and the signal inverted by the inverter INV2 is connected to the output side of the buffer memory 41. Three phase-buffers and four three-phase buffers connected to the input side of the main memory 43 so that there is no collision between data input and output, at this time, a logical AND element of the read / write controller 42 From The valid read clock 7 in Fig. 5 (g) is applied to the write clock in the main memory 43. Thus, the data of ˜˜ⓢ in Fig. 5 (h) read out from the buffer memory 41 are inputted to the input / output device. Input and store the corresponding memory 43A to 43D of the main memory 43 through 44. Here, the system controller 18 assigns an address to the memories 43A to 43D in the main memory 43 via a common address bus. Thus, the data of the 100th " A, B, C, D " tracks stored in the memories 43A to 43D in the main memory 43 are simultaneously read by the read clock (8) in FIG. The read clock is obtained by performing an AND operation on the first clock clk1 and the clock enable signal ⑤ applied by the logical AND device AND5 of the read / write controller 42 from the system controller 18. The memories 43A to 43D of the main memory 43 input / output 44 the data of the 100th " A, B, C, D " track stored by the valid read clock (8) of FIG. Output through This is input to the multiplexer 45 in the form of ⓗ ~ ⓚ of FIG. 5 (k). The multiplexer 45 selectively outputs data such as ⓗ to ⓚ of FIG. 5 k according to the signal ⓔ of FIG. 5 l applied from the system controller 18. For example, if the signal ⓔ of FIG. 5 (l) is "00", the 100th "A" track data such as ⓗ of FIG. 5 (k) is selected, and if "01", "B", "10" is selected. If it is “”, it selects “C” and if it is “11”, it outputs by selecting “D”. At this time, the signal (6) of FIG. 5 (f) by the inverter INV1 of the read / write controller 42 performs the enable control function of the multiplexer 45 and is connected to the buffer memory 41. Data output through the three-phase buffers of 44) is not output through the multiplexer 45. The data selected by the multiplexer 45 is input to the data extension section 15 of the MPEG decoder 15 'and restored to its original state. The reconstructed data Y is finally output through the data output unit 16.

In this way, if the user selects one of the "A, B, C, D" segment data through the key operation, the data can be read directly through the memory without directly accessing the data from the recording medium. It's fast.

On the other hand, when the data of the "A, B, C, D" tracks are selectively reproduced from the 100th as shown in FIG. 6, the buffers BUFA to BUFD of the buffer memory 41 are as shown in FIG. Alternately valid write clocks (Y ~ Τ in FIG. 6 (d)) are applied to the first clock clk1 in (b). Therefore, the data of tracks "A", "B", "C", and "D" such as the 100th, 101st, and 102th input data (X) shown in FIG. 6 (a) are stored in order in the corresponding buffers. do. At this time, the data of the 100th “A, B, C, D” track already stored before the data of the 101st “A, B, C, D” track is saved is saved as a valid read clock (⑦). Is read from the buffers BUFA to BUFD and a valid read clock ⑦ as shown in FIG. 6G is applied to the write clock of the main memory 43 so that the corresponding memory of the main memory 43 can be read. (43A-43D) are stored. The same is true when the data of the 102nd "A, B, C, D" track is stored. Here, the data of the track corresponding to each of the memories 43A to 43D of the main memory 43 is stored and read by the read clock 8 as shown in FIG. The multiplexer 45 selectively outputs data such as ⓗ ~ ⓚ of FIG. 6 (k) according to the signal ⓔ of FIG. 6 (l). The memories 43A to 43D in the main memory 43 designate a track using the upper 3 bits as shown in Table 1 below, and designate an address where actual data is recorded using the lower 7 bits.

As shown in Table 1, the memories 43A to 43D can store eight segment data, and since the address of the memory where the previous segment data is recorded is known, the data within this range can be reproduced at any time.

7 is an example of a data access process, in which FIG. 7 (a) is an example of accessing data of the 100th track “A”, and FIG. 7 (b) shows the 101st “A” track when the main memory is full. Fig. 7 (c) shows an example of a process of accessing data of the track “A” stored in the main memory.

First, in the case of Fig. 7 (a), the data of the "A" track is stored in the buffer memory 41 by the write clock of the read / write controller 42 among the data of the 100th "A, B, C, D" track. It is input to the buffer BUFA and stored. The data of the stored 100th " A " track is read by the read clock of the read / write controller 42 and stored in the corresponding memory 43A in the main memory 43 which uses this read clock as the write clock. The data of the 100th " A " track stored in the memory 43A is read according to the read clock of the read / write controller 42, input to the multiplexer 45, and selected and output according to the control of the system controller 18. On the other hand, in the case of Fig. 7 (b), when the data of the 101st "A" track is input while the memory 43A for the "A" track in the main memory 43 is full, the first stored in the memory 43A is 93. Delete the data of the first "A" track, move one by one and store the data of the 101st "A" track. In the case of FIG. 7 (c), the data of the 101st "A" track is stored in the corresponding memory 43A in the main memory 43 and selected by the multiplexer 45 through the case of FIG. 7 (b). When the 101st is selected again in the process of being outputted, the output of the corresponding buffer BUFA in the buffer memory 41 is cut off, and the 101st “A” stored in the corresponding memory 43A in the main memory 43 is blocked. The data of the track is read out and output through the multiplexer 45.

As described above, the present invention relates to a high-speed sorting and reproducing apparatus and method thereof, which divides a recording medium into a plurality of virtual tracks of a plurality of segment areas, stores data for each segment area in the virtual track, and stores the stored data in a memory. Access time can be shortened by storing the data on the respective areas so that data can be read directly from the memory without directly accessing the recording medium. In addition, in the case of a language learner, it is possible to record a language for each of a plurality of areas in a track and to select and reproduce only a desired language.

Claims (8)

An apparatus for fast sorting reproduction, comprising a TOC area and a data area, wherein the data area is composed of a plurality of virtual tracks of a plurality of segments, and records data for each segment in each virtual track, and the TOC area is a segment in the virtual track. A recording medium defining a star start address and a pointer of the start address; Key control unit; A system control unit which receives a key operation signal of the key operation unit and controls the overall operation of each component using information defined in the TOC area of the recording medium; A memory unit for reading data stored in a data area of the recording medium and storing the data stored in segments according to the control of the system controller, and reading only segment data of a desired virtual track from among the stored segment data; And means for restoring and reproducing and outputting the data read from the memory unit. The memory unit of claim 1, wherein the memory unit comprises a plurality of buffers for receiving data for each segment in a desired virtual track, storing data for each segment according to a valid write clock, and simultaneously reading data for each segment stored according to a valid read clock. Buffer memory; The first clock signal and the clock enable signal are applied from the system controller to generate valid write clocks alternately in the buffers of the buffer memory, and the second clock signal and the clock in faster than the first clock signal from the system controller. A valid signal is applied to the buffers of the buffer memory upon receiving a block signal, and the read clock is generated as a valid write clock of the main memory, and a first clock signal and a clock enable signal are applied from the system controller. A read / write controller that receives a valid read clock of main memory; A segment-specific data read from the buffers in accordance with a valid write clock applied from the read / write controller and connected to corresponding buffers of the buffer memory, and to a valid read clock applied from the read / write controller. A main memory comprising a plurality of memories for reading data for each segment stored accordingly; And a multiplexer for selectively outputting segment-specific data read out from the main memory under the control of the system controller. The high speed selective playback apparatus according to claim 2, wherein the system controller is further connected with an input / output unit for preventing data collision between the buffers of the buffer memory, the memories of the main memory, and the multiplexer. The apparatus of claim 3, wherein the input / output unit comprises: an inverter configured to reverse a state of a control signal of the system controller; Three-phase buffers connected to the output sides of the buffers in the buffer memory, and receiving and outputting data read from the buffers according to control signals inverted by the inverter; Respectively connected between an output side of the three-phase buffers and an input side of the memories in the main memory, and receiving the outputs of the three-phase buffers according to a control signal reversed by the inverter and outputting the outputs to the memories of the main memory. Other three-phase buffers; And another three-phase buffers connected to an output side of the memories in the main memory and receiving and outputting data read from the memories according to a control signal of the system controller. The method of claim 2 or 3, wherein the read / write controller receives a first clock signal in common from the system controller, and applies a clock enable signal alternately active in every clock from the system controller. A plurality of logical AND elements which take the logical AND operation and generate a valid write clock of the buffers; A logical multiplication device receiving the first clock signal and the clock enable signal and performing logical AND operation to generate a valid read clock of the memories; An inverter inverting the state of the clock enable signal applied to the logical AND device; The system controller receives the second clock signal between the accompaniment mechanisms of the first clock signal, receives the clock enable signal of the inverter, and performs an AND operation to generate a valid write clock of the memories and a valid read clock of the buffers. Logical multiplication device; And a plurality of logical sum elements that deliver valid write and read clocks of the buffers to the buffers. A method for fast sorting reproduction, comprising a TOC area and a data area, the data area comprising a plurality of virtual tracks of a plurality of segments, and recording data for each segment in each virtual track, wherein the TOC area is a segment in the virtual track. A first step of selecting a part to be reproduced from a recording medium defining a star start address and a pointer of the start address; A second step of sequentially reading segment data from an arbitrary virtual track including a portion selected in the first step by using the information defined in the TOC area and storing the data for each segment; A third step of reading data for each segment in an arbitrary virtual track stored in the second step and selecting only segment data corresponding to a part selected in the first step among the second virtual tracks; And a fourth step of restoring and restoring the segment data selected in the third step to the original. The method of claim 6, wherein the second step comprises: a second step of storing corresponding segment data of the input data and outputting the stored segment data before the corresponding segment data of the next virtual track is input; And a second step of storing the segment data output by the step 2a while moving the storage position of the previous virtual track data. 8. The method of claim 7, wherein the third step comprises: a step 3a of reading data for each segment in the current virtual track stored in step 2b; Stopping the operation of the step 2a when the selected part is the previous virtual track and reading the data of each segment in the previous virtual track stored in the step 2b; And a third step (c) of selecting and outputting the corresponding segment data among the segment data read in steps 3a to 3b.