JPH06175947A - Data processor equipped with dma function - Google Patents

Abstract

PURPOSE:To attain the detection of an abnormality with a high probability at the time of a DMA (direct memory access) transfer by comparing and collating data in a register with the data corresponding to transmission or reception data stored in a buffer memory by a CPU. CONSTITUTION:This processor is equipped with a register 204 which holds the data running through a data line 206 at the time of performing a memory access at the time of transmission and reception at the time of the DNA transfer. When the bit of a DMA address is changed due to some factor during the DMA transmission operation, the data are read from the other area of a buffer memory 202, and DMA transferred, and the two data compared by the CPU are different with the high probability, so that the generation of the abnormality can be recognized by the CPU. At the time of the reception operation, the detection of the abnormality can be attained by comparing the contents of the buffer memory 202 and the register 204 for transmission and reception.

Description

Detailed Description of the Invention

 [Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a DMA (Direct Memory Access) function used for transmitting and receiving data communication, for example.

[0002]

2. Description of the Related Art In a data processing apparatus including a communication controller 101 having a built-in DMAC shown in FIG. 1, a CPU (central processing unit) (not shown) for DMA transfer generally stores data to be transmitted and received. Start address of the data in the buffer memory 102 and its send / receive data
Information including byte length is passed to the communication controller to activate it. In the case of transmission, the CPU is the communication controller 10
1 is started to start DMA transfer, and when the communication controller 101 completes the transmission after that, the interrupt signal transmission line 10
The CPU has been notified of the completion of transmission by a CPU interrupt via 9.

In the case of reception, the communication controller 101 is set in the reception ready state in advance, and when the reception is completed, the CPU is notified of the reception completion by an interrupt. And DM
For the data at the time of A transfer, the CPU and the communication controller sometimes check the data transfer by adding a parity check or a checksum code. However, in such a conventional data processing device having a DMA function, if the DMA transfer address is erroneous for some reason, a sufficient transfer check cannot be performed.

[0004]

Since the conventional data processing apparatus having the DMA function is configured as described above, in the buffer memory access of the DMA, the memory address 5 set by the CPU is set by the communication controller, for example. It is not possible to check whether the access is really correct during DMA transfer.
If the MA transfer address is erroneous (for example, 1 bit is inverted), then there is a drawback that the erroneous memory address is accessed and DMA transferred as if it is operating normally. The present invention seeks to overcome this drawback. [Constitution of Invention]

[0005]

A first aspect of the present invention is a data processing apparatus having a DMA function, which performs C control for transmission / reception.
PU and DMA connected to this CPU via a transmission line
A C (direct memory access control) device, a buffer memory connected to the DMAC device via the transmission line and storing transmission / reception data, and a buffer memory connected to the transmission line via the transmission line and the buffer memory A register for latching the transmission / reception data transmitted / received to / from the DMAC device, wherein the CPU can compare and collate the data in the register with the data corresponding to the transmission or reception data stored in the buffer memory. It has characteristics.

A second aspect of the present invention is a data processing device having a DMA function, which comprises a CPU for controlling transmission and reception, and a CP
DMAC (Direct) connected to U via a transmission line
A controller incorporating a memory access control), a buffer memory connected to the controller via the transmission line to store transmission / reception data, and a buffer memory connected to the transmission line via the transmission line and the DMAC. A register for latching the transmission / reception data transmitted / received to / from a controller containing therein, the CPU compares the data in the register with the data corresponding to the transmission or reception data stored in the buffer memory. It has a feature that can be collated.

The third invention is the DM according to the first invention.
In the data processing device having the A function, the register is built in the same chip as the DMAC device.

The fourth invention is the DM according to the second invention.
In the data processing device having the A function, the above-mentioned register is incorporated in the same chip as the controller incorporating the DMAC.

[0009]

The data processor having the DMA function of the present invention has a register for latching the data actually passing on the data bus in the DMA transfer, and the CPU compares the data in the buffer memory at the end of the DMA transfer. Since it is possible to detect if wrong data is transmitted by DMA, it is possible to detect that the received data by DMA transfer is not written correctly in the memory area. It is possible to avoid system malfunction due to data.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a data processing device having a DMA function according to the present invention will be described with reference to FIG. Figure 2
Shows the configuration of the main part of the position embodiment of the data processing device having the DMA function of the present invention, and the reference numerals in the figure indicate the following components.

Reference numeral 201 is a communication controller with a built-in DM
Transmission / reception data is exchanged with the buffer memory 202 by AC. Reference numeral 202 is a buffer memory, and the communication controller 201 stores the transmission / reception data via the serial signal transmission line 211. Reference numeral 203 is a data latch signal generation unit.

Reference numeral 204 is a register for temporarily storing data transmitted and received between the communication controller 201 and the buffer memory 202. It is composed of a transmission register and a reception register. Reference numeral 205 is an address line (ADR). Reference numeral 206 is a data line (DATA). Reference numeral 207 is a control line (CNT). Reference numeral 208 is a data latch signal transmission line. Reference numeral 209 is an interrupt signal transmission line, and notifies the completion of the serial transmission / reception of the communication controller 201 to the CPU via this transmission line (INT). Reference numeral 210 is a register read signal transmission line, and is output when the CPU reads the data held by the register 204 via this transmission line. Reference numeral 211 is a serial signal transmission line, and the communication controller 201 performs serial transmission / reception via this signal line.

One embodiment will be described in detail below with reference to FIG.

That is, in the embodiment shown in FIG. 2, by providing the register 204 for holding the data flowing through the data line 206 when the memory is accessed during the transmission / reception during the DMA transfer, the address bit is inverted during the DMA transfer. Realize the detection of various obstacles with high probability.

The transmission operation of the communication controller 201 will be described. When the communication controller 201 is activated by a CPU (not shown), the data is read from the buffer memory 202 byte by byte and the serial signal transmission line 2 is read.
The transmission of serial data is started at 11. At this time, the data latch signal generation unit 203 generates a clock signal for data latch of the register 204 according to the control signal from the control line 207 and supplies it to the register 204 via the data latch signal transmission line 208. The value of the data input to is latched in the register 204 every time the communication controller 201 reads the DMA.

When the DMA transfer is completed, the communication controller 201 notifies the CPU via the interrupt signal transmission line 209 that the transmission processing is completed. Due to this transmission completion interrupt, the CPU generally recognizes the start address and the transmission data byte length in the buffer memory 202 in which the transmitted data was stored.
From the transmit register in register 204 via register read signal transmission line 210 to read the data at the same location and length as stored in register 204 (eg, the last data byte).
Predetermined data flowing in 06 (eg final data byte)
Is read by the CPU and compared with the data read from the buffer memory 202.

If the bit of the DMA address changes for some reason during the DMA transmission operation, the data is read from another area of the buffer memory 202 and DMA-transferred. Therefore, the CPU compares 2
The CPU recognizes that an abnormality has occurred because the two data are different with high probability. In the case of the receiving operation, the abnormality is detected by comparing the contents of the buffer memory 202 and the contents of the transmitting / receiving register 204 in the register 204 in exactly the same manner.

In the above description, the hardware of the transmission / reception register 204 in the register 204 has been mainly described as an example of comparing and collating the final byte of the data to be DMA-transferred. The optimum value may be selected depending on the capacity of the register 204 that stores the data that actually passes through the data line 206 and the application device that is applied by the control of the CPU.

In the above description, an example in which the DMAC is built in the communication controller has been described, but it goes without saying that the DMAC and the communication controller may select different device configurations.

Further, from the viewpoint of improving reliability, the hardware such as the register 204 to be added needs to be highly reliable, and if the reliability of the added hardware is low, an error of the device may occur. It may be easier.

Therefore, it is desirable that the additional hardware such as the register 204 is included in the same silicone chip as the DMAC or the controller 201 to improve reliability.

[0022]

As described above, the data processing device having the DMA function according to the present invention can detect an abnormality at the time of DMA transfer with a high probability, thereby avoiding a systematic defect, and therefore, a problem at the time of DMA transfer can be avoided. The reliability can be improved, and the effect obtained in practical use is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a conventional data processing device having a DMA function.

FIG. 2 is a configuration diagram of essential parts showing an embodiment of a data processing device having a DMA function according to the present invention.

[Explanation of symbols]

 201 communication controller 202 buffer memory 203 data latch signal generation unit 204 register 205 address line (ADR) 206 data line (DATA) 207 control line (CNT) 208 data latch signal transmission line 209 interrupt signal transmission line 210 register read signal transmission line 211 Serial signal transmission line

Claims (4)

[Claims] 1. DMA (Direct Memory Access)
CPU that controls transmission / reception in devices with built-in functions
And a DMAC connected to this CPU via a transmission line
A (direct memory access control) device, a buffer memory connected to the DMAC device via the transmission line and storing transmission / reception data,
A register connected to the transmission line for latching the transmission / reception data transmitted / received between the buffer memory and the DMAC device via the transmission line;
The PU is a data processing device having a DMA function, which is capable of comparing and collating the data in the register with the data corresponding to the transmission or reception data stored in the buffer memory. 2. DMA (Direct Memory Access)
CPU that controls transmission / reception in devices with built-in functions
And a DMAC connected to this CPU via a transmission line
A controller incorporating (direct memory access control), a buffer memory connected to the controller via the transmission line and storing transmission / reception data, and a buffer memory connected to the transmission line via the transmission line A register for latching the transmission / reception data transmitted / received to / from a controller containing the DMAC, and the CPU stores data in the register and data corresponding to transmission or reception data stored in the buffer memory. A data processing device having a DMA function characterized by being able to compare and collate. 3. A data processing apparatus having a DMA function according to claim 1, wherein the register is built in the same chip as the DMAC device. 4. A data processing apparatus having a DMA function according to claim 2, wherein the register is incorporated in the same chip as a controller incorporating a DMAC.