JPH0248736A - Information processing system - Google Patents

Abstract

PURPOSE:To speedily detect the abnormality of a request signal and a response signal by supervising the fall of the request signal and the response signal. CONSTITUTION:A fall detection circuit 11 transmits the pulse of a prescribed width after the response signal falls (changes from a high level to a low level), and a fall detection circuit 21 transmits the pulse of the prescribed with pulse after the request signal falls. When a signal IRQC is in the low level and a signal IRQALM is in the high level, or when the signal IRQC and the signal IRQALM are both in the high level, the control part of a central processing unit 2 recognizes that a signal IRQ has been cancelled or an abnormal signal has occurred due to noise and the like. On the other hand, the control part of an output device 1 recognizes that the abnormal signal has occurred due to noise and the like when a signal ACKC is in the low level or a signal ACKALM is in the high level. Thus, the abnormality of the request signal and the response signal can be speedily judged.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly to an information processing system comprised of a plurality of information processing devices that send and receive request signals and response signals via an interface.

Conventionally, in this type of information processing system, for example, a three-way system, request signals and response signals are exchanged between an input/output device and a central processing unit. In such a computer system, in response to an interrupt request signal from an input/output device, the central processing unit checks the priority of other interrupt requests and, if possible, responds with a signal. There is.

In addition, the reception desk responds to the input of the response signal, and the input/output device
If an interrupt request was currently being sent, the interrupt request signal would be reset unconditionally. Therefore, the normality of each signal in the input/output device has been confirmed through subsequent processing.

As mentioned above, in conventional interrupt request processing, if the input/output device cancels the request before accepting the interrupt request signal and responding with the signal, the central processing unit does not immediately know that the request has been canceled. , it is necessary to know that some kind of abnormality has occurred by detecting through time monitoring etc. that the next response from the input/output device is not received, and to sense the status of the input/output device from the central processing unit. There was a drawback.

Further, the same problem occurs when the interrupt request signal or response signal is output due to noise or the like, and there is a drawback that the abnormality must be detected by time monitoring or the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing system that can quickly determine abnormalities in request signals and response signals.

95 Example 1 The information processing system of the present invention transmits a predetermined request signal, and provides first information that disables the transmission of the request signal when a response signal is input from another information processing device. a processing device; and a second device configured to send out the response signal after a predetermined time when the request signal is input, and to stop sending out the response signal when the request signal from another information processing device is cut off. an information processing device; a first fraudulent signal sending means for sending a fraudulent signal to the first information processing device when transmission of the request signal is interrupted before the response signal is sent; and the request signal. a second device that sends an unauthorized signal to the second information processing device when the response signal is cut off before the signal sending is cut off;
It is characterized by having a fraudulent signal sending means.

cold cliff father-in-law Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing system according to the present invention. In the figure, an information processing system according to an embodiment of the present invention is comprised of an input/output device 1 and a central processing unit 2.

The input/output device 1 includes a driver DR1 for sending a request signal (IRQ), a receiver RV1 for receiving a response signal (ACK), flip-flops (hereinafter abbreviated as FF) 10 and 13, and a fall detection circuit. 11 and an AND circuit 12.

The central processing unit 2 includes a receiver R for receiving the request signal.
V2, a slanted driver OR2 that sends out a response signal,
It is configured to include FFs 20 and 23, a falling detection circuit 21, an AND circuit 22, and an inverter INV.

The fall detection circuit 11 sends out a pulse of a predetermined width after the response signal falls (that is, when it changes from high level to low level). Further, the fall detection circuit 21 sends out a pulse of a predetermined width after the request signal falls. The FF 23 takes in and holds a request signal from the input/output device 1 via the driver DR1 and receiver RV2, and sends out a signal IRQc. Further, the FF 13 takes in and holds a response signal from the central processing unit 2 via the driver OR2 and the receiver RV1, and sends out a signal ACKC.

The FF20 holds the output of the AND circuit 22 and outputs the signal IRQ.
This transmits ALH. Further, FF10 holds the output of the AND circuit 12 and sends out ^[H to the signal ^C.

The operation of transmitting and receiving request signals and response signals between the input/output device 1 and the central processing unit 2 in the information processing system having such a configuration will be explained with reference to FIGS. 2 to 4. Second
The figure is a time chart showing the normal operation, FIG. 3 is a time chart showing the operation when an abnormality occurs in the request signal, and FIG. 4 is a time chart showing the operation when an abnormality occurs in the response signal.

In FIG. 2, the request signal IRQ, the signal IRQC, the output 210 of the falling detection circuit 21, and the signal IRQA[
In Figure 9, which shows the response signal ACK, the signal CKC, the output 110 of the falling detection circuit 11, and the signal CKALM, in normal times, the request signal IRQ is first sent from the input/output device 1. When sent, driver DR1
and is input to the central processing unit 2 via the receiver RV2. Then, the signal IRQC, which is held in the FF 23 and is its output, is sent to a control section (not shown) (■), and the fall detection circuit 21 monitors the fall of the request signal IRQ.

A control unit (not shown) in the central processing unit 2 checks whether or not an interrupt can be accepted, and if the interrupt is accepted, and if the signal IRQAL is
If H is not sent, a response signal ACK is sent (
(■) This response signal ACK is input to the input/output device 1 via the driver DR2 and receiver Rv1, held in the FF13, and the signal ACKC is sent to the control section (not shown) (■). The circuit 11 monitors the fall of the response signal AC.

If the response signal AC is input and the signal ACKALH is not sent, the input/output device 1 starts the sequence related to the interrupt request and releases the request signal IRQ (■)
. Then, the request signal IRQ falls, and the falling detection circuit 2
1 sends out an output 210, and the signal I which is the output of FF23
RQC falls (■).

In this case, since the response signal ACK is at a high level, the output of the inverter INV is at a low level, and the signal IRQALM is not sent out (■ and ■).

Next, when the central processing unit 2 releases the response signal ACK, the fall detection circuit 11 sends out the output 110 due to the fall of the response signal ACK, and 〇KC falls to the signal that is the output of the FF 13 (■
).

In this case, since the request signal IRQ is at a low level, the signal ACKALH is not sent out (■).

This completes the signal exchange.

That is, when the control section of the central processing unit 2 sends out the response signal AC, the signal IRQC is in the set state (in other words, high level), and the signal IRQ^[H is in the non-set state (in other words, low level). request signal I
It recognizes that the RQ has not been cancelled. At this time, if the signal 1110C is low level and the signal IRQA
LH is high level, or signal IRQC and signal IR
If both QALHs are at high level, it can be recognized that the signal IRQ has been canceled or that an incorrect signal has been generated due to noise or the like.

In this case, the response signal ACK is not issued and abnormality processing is performed.

Furthermore, when canceling the sending of the request signal [Q, the control section of the input/output device 1 sees that ALH is at a low level in the signal ^C and recognizes that the response signal C is normal. At this time, if the signal ACKC is at a low level or the signal KALH is at a high level, it can be recognized that an incorrect signal has been generated due to noise or the like. In this case, the request signal IRQ is not released, but the request signal IRQ is not released, but the request signal IRQ is waited for to be sent as the normal response signal AC.

Further, in FIG. 3, the request signal IRQ and the signal IR
QC, the output 210 of the falling detection circuit 21, and the signal IR
Q8[H and are shown in the response signal AC.

In the figure, first, the request signal IR is sent from the input/output device 1.
When Q is sent out, it is held in FF23 as described above,
Signal 1nQC falls (■), then request signal IR
When Q falls due to noise or the like (that is, incorrectly), the output 210 of the falling detection circuit 21 is sent out.

At this time, since the response signal ^C has not yet been sent, the output of the inverter INV becomes high level, the output of the AND circuit 22 becomes high level and is held in the FF 20, and the signal IRQALH is sent out (■ and ■). This allows the central processing unit i! The control section in 2 recognizes that the request signal IRQ from the input/output device 1 is invalid and does not send CK to the response signal (■).

Furthermore, in FIG. 4, the response signal ○, the signal CKC, the output 110 of the fall detection circuit 11, the signal ^C ALH, and the request signal IRQ are shown.

In the figure, after the request signal IRQ is sent from the input/output device 1, when the response signal ACK is sent from the central processing unit 2, it is held in the FF 13 as described above, and the signal ACKC
rises (■), and then falls due to noise etc. (in other words, incorrect), the fall detection circuit 11
The output 110 of is sent out (■).

At this time, since the request signal IRQ is still being sent out, the output of the AND circuit 12 becomes high level and FFl0
is held, and 8 [H is sent to C to the signal (■ and ■
), the control unit in the input/output device 1 recognizes that the response signal AC from the central processing unit 2 is invalid,
Without releasing the request signal IRQ (■), the normal response signal AC
It waits for K to be sent.

As described above, in the central processing unit 2, the signal IRQ
When ALH is at high level and signal IRQC is at high level, it can be quickly detected that the request signal IRQ is invalid.

Further, when the signal ACKALH and the signal ACKC are at a high level in the input/output device 1, it is possible to quickly detect that the response signal AC is invalid.

As described above, the present invention has the advantage that by monitoring the fall of the request signal and the response signal, it is possible to quickly detect fraud in the request signal and the response signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention, FIG. 2 is a time chart showing the normal operation of the information processing system shown in FIG. 1, and FIG. 3 is a block diagram showing the information processing system shown in FIG. FIG. 4 is a time chart showing the operation of the processing system when an abnormality occurs in the request signal. FIG. 4 is a time chart showing the operation when an abnormality occurs in the response signal of the information processing system of FIG. Explanation of symbols of main parts 10.13, 20.23... Free lag flop 11.21... Fall detection circuit 12.22...
・・・AND circuit

Claims (1)

[Claims] (1) A first information processing device that sends a predetermined request signal and stops sending the request signal when a response signal is input from another information processing device; a second information processing device that transmits the response signal after a predetermined time and stops transmitting the response signal when the request signal from another information processing device is disconnected; A first device that sends an unauthorized signal to the first information processing device when the sending of the request signal is interrupted before the request signal is sent.
and a second fraudulent signal transmitting means for transmitting a fraudulent signal to the second information processing device when the response signal is disconnected before the request signal is disconnected. An information processing system characterized by: