JPS60149251A - Fault detector for terminal control processor of electronic exchange - Google Patents

Abstract

PURPOSE:To improve the fault detecting sensitivity as well as the processing efficiency by dividing a terminal control processor into two blocks and monitoring the presence or absence of an access and the length of this access to a shared memory between both processors by these processors to each other. CONSTITUTION:Control processors 7 divided into two parts via a control bus 8 are connected to an exchange control processor 6 of a system. These processors 7 are connected to terminal control processors 9 via a reset circuit 12 and a memory controller 13 respectively. Then each of divided terminals 11 are connected to the processors 9, and common memory devices 10 are connected to the controllers 13 respectively. When the controllers 13 deliver the requests to processors 7 and 9 for use of the devices 10, the faults of both processors 7 and 9 are detected with each other by the output of controllers 13 in response to the requests of the controllers 13. Then the circuit 12 is reset based on the result of the fault detection. This improves the fault detecting sensitivity and facilitates an easy increase of terminals 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a terminal control processor fault detection device for an electronic exchange having terminal control processors.

This will be explained in conjunction with FIG. In FIG. 1, 1 is a control processor, and a control bus 2 is connected to this control processor. A terminal control processor 3 is connected to the control bus 2 like the control processor 1, and at the same time is connected to the terminal device 5 through a control line 4. 6 is an individual reset signal line from the control processor 1 to the terminal control processor 3.

Next, the operation of the above conventional example will be explained. In FIG. 1, terminal operation, for example off-hook.

Information such as dial information is sent through the terminal control processor 3.
It is sent to the control processor 1. On the other hand, the control processor 1 analyzes and interprets this information and gives instructions (such as sending a ring tone) to the uncontrolled processor 3. Therefore, if the terminal control processor 3 breaks down, the terminals connected to that terminal control processor will not be able to receive exchange services. Therefore, the control processor 1 periodically sends test commands to the terminal control processor 3 through the control bus 2 to check the operation of the terminal control processor 3. When the control processor 1 detects a failure in the terminal control processor 3 using the above test command, it initializes the terminal control processor 3 using the individual reset line 6 .

Conventionally, failure detection and recovery of the terminal control processor 3 have been performed as described above.

However, in the conventional example described above, the control processor 1 detects failures by periodically sending test commands to the terminal control processor 3. Therefore, in order to shorten the time from failure occurrence to failure detection, it is necessary to shorten the interval between the above-mentioned periodic tests. Therefore, if the fault detection sensitivity is improved, the control processor 1
There was a problem that the load on the machine would increase. Furthermore, since the individual reset signal 6 is sent to the terminal control processors 3, there is a problem in that when the number of terminal control processors 3 increases, the number of main lines of the control bus increases.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned conventional problems, and aims to prevent the increase in failure detection sensitivity and terminal control processors from affecting the processing efficiency of the control processors. It is.

Structure of the Invention In order to achieve the above object, the present invention distributes a terminal control processor into two processors, provides a shared memory between these two processors, and determines whether or not this memory is accessed by both processors; The system is configured to detect each other's failures by monitoring each other's access lengths.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 6 is a control processor;
This control processor 6 is connected to a communication control processor 7 via a control bus 8 . 9 is a terminal control processor, and between the terminal control processor 9 and the communication control processor 7, a memory device 10 that can be accessed by both the processors 9 and 7 is connected. 11 is a terminal connected to the terminal control processor, and 12 is a reset circuit that initializes both the processors 7 and 9 by signals from the communication control processor 7 and the terminal control processor 9. 13 is
This is a memory control device that controls memory contention between the two processors 7.9.

Next, the operation of the above embodiment will be explained. In FIG. 2, when the communication control processor 7 issues a memory use request to the memory control device 13 in order to access the memory device 10, the memory control device 13 requires that the terminal control processor 9 is currently using the memory device 10. Permission to use the memory is given to the communication control processor 7 as soon as it is in use, or after completion of the use if it is in use.

The communication control processor 7 measures the time from the memory use request to the memory use permission, and if it exceeds the specified time, it determines that there is a failure in the terminal control processor 9 and drives the reset circuit 12. The communication control processor 7 and the terminal control processor 9 are initialized to perform failure recovery. Conversely, when the terminal control processor 9 accesses the memory device 10, it sends a memory use request to the memory control device 13, receives permission to use the memory, and then accesses the memory device 10.
access. The terminal control processor 9 measures the time from the memory use request to the memory use permission, and if the specified time is exceeded, it determines that there is a failure in the communication control processor 7 and drives the reset circuit 12. The communication control processor 7 and the terminal control processor 9 are initialized to perform failure recovery.

In this way, in the above-mentioned embodiment, since the fault detection of the terminal control device is performed by the terminal control device itself, there is no need for the switching control processor 6 to monitor faults in the terminal control processor. This has the advantage that the load on the processor 6 can be significantly reduced.

Effects of the Invention As is clear from the above embodiments, the present invention comprises a terminal control device including a communication control processor, a terminal control processor, a memory device common to both processors, and a reset circuit. There is no need to control failure recovery at all, and there is an advantage that the wiring between the exchange control processor and the terminal control processor can be significantly reduced. Further, according to the present invention, since the communication control processor and the terminal control processor forming each terminal control device are configured to mutually detect the failure, the load on the exchange control processor is significantly reduced. It has the advantage of being able to Further, according to the present invention, since a shared memory device is used and a fault is detected when the memory device is accessed, there is an advantage that fault detection sensitivity is significantly increased.

[Brief explanation of the drawing]

- FIG. 1 is a schematic configuration diagram of a failure detection device for a terminal control processor of a conventional electronic exchange, and FIG. 2 is a schematic configuration diagram of a failure detection device for a terminal control processor in an embodiment of the present invention. 6... Control processor, 7... Communication control processor, 9
...Terminal control processor, 10...Memory device, 11
. . . terminal, 12 . . . reset circuit, 13 . . . memory control device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] A plurality of terminal control devices connected to the exchange control processor perform conflict control among the communication control processor connected to the exchange control processor, the terminal control processor connected to the terminal, a memory device common to both of the processors, and the memory device. The memory control device and the terminal control device are each equipped with a reset circuit for initializing the device, and the communication control processor,
When each of the terminal control processors issues a request from the processor to the memory control device to use the memory device, the terminal control is performed using the output of the memory control device output in response. An electronic exchange characterized in that the processor and the communication control processor are configured to mutually detect a failure, and based on the detection result, drive the reset circuit and initialize the terminal control device. Terminal control processor failure detection device.