JPS58211268A - Multi-processor system - Google Patents

Multi-processor system

Info

Publication number
JPS58211268A
JPS58211268A JP57094065A JP9406582A JPS58211268A JP S58211268 A JPS58211268 A JP S58211268A JP 57094065 A JP57094065 A JP 57094065A JP 9406582 A JP9406582 A JP 9406582A JP S58211268 A JPS58211268 A JP S58211268A
Authority
JP
Japan
Prior art keywords
processor
fault
faulty state
state
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57094065A
Other languages
Japanese (ja)
Inventor
Kazuhiko Maekawa
和彦 前川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57094065A priority Critical patent/JPS58211268A/en
Publication of JPS58211268A publication Critical patent/JPS58211268A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify the processing of a fault in a multi-processor system, by constituting so that the processor concerned can be set forcibly to a mode of a faulty state, when an abnormal state of other processor is detected. CONSTITUTION:In case when a processor 1 executes an inter-device communication to a processor 2 and 3, the processor 1 sends out a transmitting signal to the processor 2 and 3, and thereafter, waits for its response for a constant interval of time. In case when no response is received from the processor 2, the processor 1 can decide that the processor 2 is not in a normal state. In that case, when the processor 1 sets a faulty state requesting circuit 132, a faulty state displaying circuit 21 is set, and the processor 2 is set to a mode of a faulty state. By an output of this circuit 21, faulty state displaying circuits 122, 322 are set, and the fault processing is started. In this way, the processors 1, 3 can detect the faulty state of the processor 2 in the same way as the faulty state of its own device, therefore, the processing of a fault can be simplified.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、複数個のプロセッサ（ＣＰ　Ｕ）を具備する
多重プロセッサシステムの障害処理方式に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to a failure handling method for a multiprocessor system including a plurality of processors (CPUs).

〔従来技術の説明〕[Description of prior art]

従来、多重プロセッサシステムでは、第一のプロセッサ
が第二のプロセッサの、異常を検出したときには、第一
のプロセッサは第二のプロセッサをシステムから切離す
ために、第三、第四のプロセッサに装置間通信を行った
後に、第二のプロセッサを切離していた。したがってこ
れらの装置間通信中に第二のプロセッサの異常を検出し
たときには、この障害処理のために別の装置間通信網を
使用する必要があり、そこで再び他装置の異常を検出し
たときには、さらに別の装置間通信網を使用して障害処
理を行わなければならない等障害処理が複雑化する問題
点があった。Conventionally, in a multiprocessor system, when a first processor detects an abnormality in a second processor, the first processor sends a device to the third and fourth processors in order to disconnect the second processor from the system. The second processor was disconnected after the communication between the two processors was completed. Therefore, when an abnormality in the second processor is detected during communication between these devices, it is necessary to use another inter-device communication network to handle the fault, and when an abnormality is detected in another device again, further processing is required. There is a problem that trouble handling becomes complicated, such as having to use another inter-device communication network to handle trouble.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記問題点を解決するもので任意のプ
ロセッサに障害が生じた場合に、その障害情報を他のプ
ロセッサに迅速に通知して障害処理を簡単化し得る多重
プロセッサシステムを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a multiprocessor system that can quickly notify other processors of failure information when a failure occurs in any processor, thereby simplifying failure handling. There is a particular thing.

〔発明の要点〕[Key points of the invention]

本発明は、任意の１個のプロセッサを障害状態のモード
に設定することを要求する手段と、この手段の指示によ
り対応するプロセッサを障害状態のモードに設定する手
段と、他のプロセッサに上記プロセッサが障害状態のモ
ードに設定されたことを通知する手段とを有することを
特徴とする。The present invention includes means for requesting that any one processor be set to a failure state mode, means for setting a corresponding processor to a failure state mode in response to an instruction from the means, and a means for requesting other processors to set said processor to a failure state mode. and means for notifying that the mode is set to a failure mode.

〔実施例による説明〕[Explanation based on examples]

次に本発明の実施例について図面を参照して詳細に説明
する。Next, embodiments of the present invention will be described in detail with reference to the drawings.

図は本発明の一実施例多重プロセッサシステムのブロッ
ク構成図であり、３プロセツサシステム構成の例である
。The figure is a block diagram of a multi-processor system according to an embodiment of the present invention, and is an example of a three-processor system configuration.

プロセッサｌには、自己のプロセッサｌの障害状態表示
回路１１、他のプロセッサ２．３の障害状態表示回路１
２２．１２３、および他のプロセッサ２．３の障害状態
要求回路１３２．１３３が設けられる。Processor l includes a fault state display circuit 11 for its own processor l and a fault state display circuit 1 for other processors 2.3.
22.123, and a fault status request circuit 132.133 of the other processor 2.3.

プロセッサ２には、自己のプロセッサ２の障害状態表示
回路２１、他のプロセッサ１．３の障害状態表示回路２
２１．２２３、および他のプロセッサ１．３の障害状態
要求回路２３１．２３３が設けられる。The processor 2 includes a fault state display circuit 21 of its own processor 2 and a fault state display circuit 2 of the other processors 1.3.
21.223, and a fault status request circuit 231.233 of the other processor 1.3 is provided.

プロセッサ３には、自己のプロセッサ３の障害状態表示
回路３１、他のプロセッサ１．２の障害状態表示回路３
２１．３２２、および他のプロセッサ１．２の障害状態
要求回路３３１．３３２が設けられる。The processor 3 includes a fault state display circuit 31 for its own processor 3 and a fault state display circuit 3 for other processors 1.2.
21.322, and a fault status request circuit 331.332 of the other processor 1.2 is provided.

プロセッサ１の障害状態表示回路１１は、プロセッサｌ
内で障害を検出したときにセットされ、プロセソ−ｇ−
１は障害状態のモードになる。他のプロセッサ１．３の
障害状態表示回路１２２．１２３は、それぞれプロセッ
サ２の障害状態表示回路２１、プロセッサ３の障害状態
表示回路３１がセットされることによりセントされ、障
害処理が起動される。また障害状態要求回路１３２．１
３３をセットすることにより障害状態表示回路２１．２
２がセントされ、該当するプロセッサｌまたは２が障害
状態のモードに設定される。つまり障害状態表示回路１
１．２１．３１は、自己のプロセッサ内で障害を検出し
たときと、障害状態要求回路１３２．１３３．２３１．
２３３．３３１．３３２がセットされたときにセットさ
れる。The fault status display circuit 11 of the processor 1
Set when a fault is detected in the processor g-
1 is in failure state mode. The fault state display circuits 122 and 123 of the other processors 1.3 are sent by setting the fault state display circuit 21 of the processor 2 and the fault state display circuit 31 of the processor 3, respectively, and the fault processing is activated. Also, the fault state request circuit 132.1
By setting 33, the fault status display circuit 21.2
2 is sent and the appropriate processor l or 2 is set to failure mode. In other words, the fault status display circuit 1
1.21.31 when a failure is detected within its own processor, and failure state request circuit 132.133.231.
Set when 233.331.332 is set.

このような構成で、プロセッサｌがプロセッサ２と３と
の間で装置間通信を行ったときの動作を説明する。プロ
セッサ１は、ブロモ・ノサ２および３に送信信号を送出
した後、プロセッサ２および３からの応答をある一定時
間待つ。いまブロモ・ノザ２からのみ応答がなかったと
すると、ブロモ・ノサｌはプロセッサ２がストール状態
等の正常でない状態になっていると判断することができ
る。そこでプロセッサ１がプロセッサ２用の障害状態要
求回路１３２をセットすると、ブロモ・ノサ２の障害状
態表示回路２１がセットされ、ブロモ・ンサ２は障害状
態のモードに設定される。この障害状態表示回路２１の
出力によりブロモ・フサ２用の障害状態表示回路１２２
．３２２がセ・７トされ、プロセッサｌおよび３にプロ
セッサ２が障害状態のモードになったことが通信され、
障害処理が起動される。With this configuration, the operation when processor 1 performs inter-device communication between processors 2 and 3 will be described. After the processor 1 sends the transmission signal to the bromo nosas 2 and 3, it waits for a response from the processors 2 and 3 for a certain period of time. If there is no response only from Bromo Noza 2, Bromo Noza 1 can determine that the processor 2 is in an abnormal state such as a stall state. Therefore, when the processor 1 sets the fault state request circuit 132 for the processor 2, the fault state display circuit 21 of the Bromo Nosa 2 is set, and the Bromo Nosa 2 is set to the fault state mode. The output of this fault state display circuit 21 causes a fault state display circuit 122 for Bromo Fusa 2 to
．． 322 is set to communicate to processors 1 and 3 that processor 2 is in a failed mode;
Fault handling is activated.

これにより他のプロセッサ１および３は、プロセッサ２
の障害状態を自装置の障害状態と同様に検出することが
できるため、障害処理を非富に簡単化することができる
。As a result, other processors 1 and 3
Since the fault state of the device can be detected in the same way as the fault state of the own device, fault handling can be greatly simplified.

なお上記例で示したブロモ・ノサの数は、３個に限らず
、増減してもよい。Note that the number of bromo nosas shown in the above example is not limited to three, and may be increased or decreased.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、他のプロセッサ
の異品を検出したときに該当ブロモ・ノサを強制的に障
害状態のモードに設定することができるように構成する
ことにより、多重ブロモ・ソサシステムでの障害処理を
簡単化できる優れた効果がある。As described above, according to the present invention, when a foreign processor is detected, the corresponding Bromo Nosa can be forcibly set to the failure mode, thereby making it possible to・It has the excellent effect of simplifying failure handling in the Sosa system.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例多重ブロモ・ノサシステムのブロ
ック構成図。 １２、計−プロセッサ、１１２１．３１〜自己のプロセ
ッサの障害状態表示回路、１２２．１２３．２２１．２
２３．３２１．３２２−他のプロセッサの障害状態表示
回路、１３２．１３３．２３１．２３３．３３１．３３
２−障害状態要求回路。 特許出願人　日本電気株式会社、−９゜代理人　弁理士
　井出直孝゛″　、゛The figure is a block diagram of a multiple bromo-nosa system according to an embodiment of the present invention. 12, Total processor, 1121.31 ~ own processor fault status display circuit, 122.123.221.2
23.321.322 - Other processor fault status indication circuit, 132.133.231.233.331.33
2 - Fault condition request circuit. Patent applicant: NEC Corporation, -9゜Representative: Patent attorney Naotaka Ide

Claims (1)

【特許請求の範囲】 （１１自己のプロセッサに、 他のプロセッサを障害状態のモードに設定することを要
求する要求手段と、 この要求手段の指示により上記他のプロセッサを障害状
態のモードに設定する手段と、上記他のプロセッサ以外
のプロセッサに上記他のプロセッサが障害状態のモード
に設定されたことを通知する手段と を備えた多重プロセッサシステム。[Scope of Claims] (11) requesting means for requesting its own processor to set other processors to failure state mode, and setting the other processors to failure state mode according to instructions from the requesting means; and means for notifying a processor other than the other processor that the other processor is set to a failure mode.
JP57094065A 1982-06-03 1982-06-03 Multi-processor system Pending JPS58211268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57094065A JPS58211268A (en) 1982-06-03 1982-06-03 Multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57094065A JPS58211268A (en) 1982-06-03 1982-06-03 Multi-processor system

Publications (1)

Publication Number Publication Date
JPS58211268A true JPS58211268A (en) 1983-12-08

Family

ID=14100113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57094065A Pending JPS58211268A (en) 1982-06-03 1982-06-03 Multi-processor system

Country Status (1)

Country Link
JP (1) JPS58211268A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08263329A (en) * 1995-03-17 1996-10-11 Nec Corp Fault log information acquisition system for computer system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166752A (en) * 1979-06-13 1980-12-26 Meidensha Electric Mfg Co Ltd Function inspection system of multimicrocomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166752A (en) * 1979-06-13 1980-12-26 Meidensha Electric Mfg Co Ltd Function inspection system of multimicrocomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08263329A (en) * 1995-03-17 1996-10-11 Nec Corp Fault log information acquisition system for computer system

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