JPS6239776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an information processing device having multiple types of interrupt processing functions.

Information processing apparatuses that control peripheral devices such as printers and key input devices or perform multiprocessor processing are required to have the ability to execute multiple interrupt processes. For this reason, conventional devices are configured to be able to select and execute a desired program from among a plurality of interrupt processing programs, and the selection of the program is performed using an interrupt request signal. An interrupt request signal is generated from another device that wants this device to perform interrupt processing, and this device is designed to select and execute the interrupt processing program specified by the request signal when it receives the request signal. There is. Recently, there are some devices whose circuits are designed to give priority to a plurality of interrupt request signals and to process the higher priority interrupt request signal preferentially. In the case of this device, a mask register is generally provided in the interrupt request signal receiving section so that an interrupt request signal with a lower priority is masked (input prohibited) by an interrupt request signal with a higher priority.

Furthermore, in information processing systems that are accompanied by peripheral devices or include a plurality of the above information processing devices, the processing contents of the information processing devices themselves tend to become more complex and sophisticated. For this reason, timing (time) control of processing also becomes extremely complicated. Moreover, if a plurality of interrupt processes have to be executed, it is difficult to perform simple software control alone.

Therefore, it is desirable to reduce the burden on software and perform efficient timing control so that processing can be performed as efficiently as possible. However, conventionally known information processing devices with an interrupt processing function do not fully satisfy this requirement, especially those with complex interrupt levels, which have many processing timing lags and require urgent interrupt processing. However, there was a high risk that the processing efficiency would be poor and that incorrect processing would sometimes be executed, due to long waiting times or unrelated interrupt processing being suddenly executed.

An object of the present invention is to provide an information processing device that can easily control the timing of processing, reduce the burden on software, and execute efficient interrupt processing in program processing, especially when multiple interrupt processing is involved. It's about doing. Another object of the present invention is to provide a highly reliable information processing device that saves power consumption and does not execute interrupt processing by mistake.

The present invention provides an information processing device having a function of executing a plurality of interrupt processes, comprising: a receiving unit that accepts a request signal instructing the interrupt process; a selecting unit that selects a desired signal from among the accepted request signals; a processing unit that executes interrupt processing; a stop unit that temporarily stops the operation of the processing unit; and a stop unit that controls the stop unit and releases the stopped state based on the request signal selected by the selection unit. a control unit that puts the processing unit into an operating state, and an interrupt that determines whether or not to perform an interrupt process specified by the interrupt request signal used to cancel the stop state for the processing unit whose stop state has been released. 1. An information processing apparatus, comprising: an interrupt processing determining section, and determining whether or not to perform interrupt processing based on a selected interrupt request signal after releasing the stopped state of the processing section.

According to the present invention, since the stop control section is provided that can stop the operation of the processing section, unnecessary processing time or waiting time until the next processing command is given after the completion of one processing is eliminated. Alternatively, the operation of the processing section can be temporarily stopped during a timing period before urgent interrupt processing occurs. Therefore, execution of unnecessary processing and power consumption during non-processing time can be significantly reduced.
Furthermore, if it is predicted that an emergency interrupt will occur, the currently executing process can be saved and temporarily suspended, and placed on standby for interrupt processing. If so, you can start working on it immediately. Therefore, interrupt processing with a high degree of urgency is not made to wait unnecessarily, and high-speed processing can be performed. In addition, since the stop control unit's stop release control is performed by the interrupt request signal selected by the selection unit, that is, the signal that specifies the requested interrupt processing, it is possible to There is no inconvenience that the processing section is occupied by the interrupt request signal.

Further, in the present invention, after the processing unit is released from the stopped state by the selected interrupt request signal, it is determined whether or not to perform actual interrupt processing based on the interrupt request signal used to release the processing unit from the stopped state. have the means. Therefore, after the processing section is released from the stopped state by a desired interrupt request signal, it is possible to freely control whether or not to execute the interrupt. In other words, it is possible to perform an operation in which the stopped state of the processing unit can be canceled only when a desired interrupt request is received, thereby achieving the effect of expanding the control range of interrupt processing as described later. can.

As is clear from the above description, the present invention includes:
The present invention provides a controller that has a plurality of interrupt processing functions and executes desired interrupt processing at high speed in each predetermined cycle, and is extremely useful as a control system for terminal devices such as printers and key input devices.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which an information processing apparatus (hereinafter referred to as a processor) of the present invention is used as a printer controller for a system including a printer as a terminal device will be described below with reference to the drawings.

FIG. 1 shows a block diagram of essential parts of a processor showing one embodiment of the present invention. Reference numeral 1 denotes a memory unit that collectively represents a program memory (for example, ROM) and a data memory (for example, RAM).
2 is a processing section including various registers and an arithmetic control circuit. 3 is a timer circuit, and 4 is a serial interface circuit for inputting/outputting serial data from, for example, another processor, which is a useful function in a multiprocessor system. 5 is an interrupt control circuit, which receives an interrupt request signal INTT from the timer circuit 3, an interrupt request signal INTS from the serial interface circuit 4, and an interrupt request signal 6 from an external peripheral terminal device (for example, printer 100, CRT 200). (INT1, INT2) are input, and various processes as described later are performed in response to these interrupt request signals. Reference numeral 7 denotes a halt control circuit that controls the temporary suspension (hereinafter referred to as halt) and release of the operation of the processing unit 2 (or memory unit 1 in some cases), and is the output terminal of the interrupt control circuit 5. are partially connected.

Next, details of the interrupt control circuit 5 are shown in FIG. In FIG. 2, the interrupt request signal mentioned above is
INT1, INT2, INTT, and INTS are input to one input terminal of AND circuits 8, 9, 10, and 11, respectively. Reference numeral 12 denotes a selection unit having a function of selecting a desired interrupt request signal, and includes mask registers 12-1, 12-2, 12-3, and 12-1, each having 1 bit.
It is composed of 2-4. As an output, an inverted output of the contents of the register is taken out and inputted to the other input terminal of the corresponding AND circuit 8, 9, 10, 11, respectively. Therefore, interrupt mask register bits 12-1, 12-2, 12-
By resetting 3, 12-4, the inverted output of each bit becomes high level, so the interrupt request signals INT1, LNT2, INTT, INTS,
This signal is valid and is used as a signal to release the halt state and as a signal to instruct interrupt processing, as described below. Furthermore, interrupt mask register bits 12-1, 12-2, 12-3,
When 12-4 is set (made high level), the inverted output of each bit becomes low level, so the outputs of the corresponding AND circuits 8, 9, 10, and 11 all become low level, and the interrupt request signal
Even if INT1, INT2, INTT, and INTS are input, they are invalid, and as described below, the halt state cannot be released or an interrupt instruction can be given. The outputs of AND circuits 8, 9, 10, and 11 are input to an OR circuit 13, and AND circuits 16, 17, 18, and 1 are input for interrupt instructions.
9, is also input to one side. The output of the OR circuit 13 is connected to the reset input terminal of a set/reset flip-flop (hereinafter referred to as "SRT/F") 15. This SRF/F15 has a halt command control signal 20 at its set end so that it is set by a command for setting the halt state of the processing section (hereinafter referred to as "halt command").
is input. The SRF/F15 controls the halt control circuit with its output, and when the SRF/F15 is set, a halt state is set and the operation of the processing section is temporarily stopped. On the other hand, when it is reset, the halt state is released and the processing section becomes operational.
14 is also an SRF/F, which is set by a control signal 21 caused by an interrupt enable instruction (hereinafter referred to as "EI instruction"), and reset by a control signal 22 caused by an interrupt disable instruction (hereinafter referred to as "DI instruction"). . The output of this SRF/F 14 is commonly supplied to the other input terminals of AND circuits 16, 17, 18, and 19. SRF/F14
When set, its output becomes high level,
The output states of AND circuits 16, 17, 18, and 19 are determined by the output states of AND circuits 8-11. On the other hand, if the SRF/F 14 is reset, even the interrupt request signal selected by the mask register will be inhibited there.
When the SRF/F14 is set and an interrupt request signal is input, only the selected interrupt request signal is output from the corresponding AND circuits 16 to 19, and this is processed by the interrupt processing subroutine (e.g.
It is used as a signal to specify the start address for reading an interrupt processing program (predetermined in memory such as ROM). To give the simplest example, each interrupt processing subroutine is stored in memory as a table, the start address of each table is set in a register for the number of tables, and the read signal for that register is used as a read signal.
It is only necessary to set the outputs of the AND circuits 16 to 19 to be used.

Here, the types of interrupt request signals input to the circuit of FIG. 2 and their input conditions will be clearly explained.

INT1: A request signal generated by the printer 100 to accept printout data, and a signal requesting interrupt processing to cause the processor to execute data transfer in order to transfer the data to be printed from the processor shown in FIG. .

INT2...A request signal generated from the CRT200 and sent to the processor to accept display data.
A signal that requests interrupt processing to execute CRT data transfer.

INTT... Interrupts the processor every predetermined cycle with an interrupt request signal from the timer circuit, and gives the start timing of a process to be repeatedly executed every predetermined cycle. In this example, this corresponds to key input scanning processing for a key input device.

INTS: An interrupt request signal transferred from or to other processors that make up a multiprocessor system. When multiple processors cooperate to execute a series of programs, this is an interrupt request signal that is used to transmit data between processors. Or, it occurs when giving and receiving commands. In this example, the requests include a request to execute a partial program, a transfer request to receive the result, and a request to transfer information stored in a memory attached to the processor.

Next, the setting conditions of the mask register will be explained.
Data transferred from the processing section 2 of FIG. 1 is written into the individual mask registers 12-1 to 12-4, and selection is made to the corresponding interrupt request signal. In this case, only the interrupt request signal determined by the processor is permitted. As for hardware, each register is configured with 1-bit RSF/F. Therefore, there is no need for a circuit configuration for determining the priority order of interrupt request signals, and the circuit configuration is significantly simplified. The processor determines which interrupt request signal to select depending on time or by a program. In addition, in order to accept other urgent interrupt processing while one interrupt processing is being executed, some of the interrupt request signals input to the AND circuits 8 to 11 are branched and sent to the urgent priority determination circuit (dotted line block 23). You may also input it. However, even in this case, after saving the address indicating the order of interrupt processing currently being executed, the contents of the mask register 12 can be changed, that is, the mask register can be controlled so that the emergency interrupt request signal can be selected. Or, as will be described later, the SRF/F 14 may be reset and the interrupt request signal 24 permitted by the emergency priority determination circuit 23 may be used to execute emergency interrupt processing. In this way, even when a plurality of interrupt requests occur simultaneously, the one selected by the mask register 12 can be permitted, and emergency interrupts can also be accepted.

Next, the halt instruction execution conditions will be explained. This command is used when it is known that a predetermined interrupt request signal will be input periodically, or when the processor is not accepting or does not have a program to process (in other words, when it is in an empty state). It is an instruction to be executed. When this command is executed, the supply of the basic clock signal to the processing section or memory section (in the case of static memory) of the processor is stopped and it is placed in a non-operating state (waiting state). As a result, interrupt processing can be executed without waiting time, and power consumption in the idle state can be saved. Note that when it is known that a predetermined interrupt request signal is input every cycle as described above, for example, in the printout data transfer interrupt processing (INT1), a program that can be executed within that cycle (for example, print Only the out data creation process) is executed, and after that process is executed, the system is placed in a halt state. As a result, the interrupt processing by INT1 can immediately proceed to the interrupt processing without any waiting time. Furthermore, there is no power consumption until interrupt processing.

Next, the EI and DI instruction execution conditions will be explained. The SRF/F 14 that executes this instruction is provided primarily as a safety circuit to prevent malfunctions due to interrupts. This is an important additional mechanism in terms of increasing the reliability of the processor.
That is, it is a circuit for controlling the timing of the interrupt request signal once selected by the mask register 12.
It works to prohibit acceptance of interrupts when the processor is executing other program processing or when the current processing based on the interrupt has not been saved. Therefore, after the SRF/F 14, which is set in the reset state, has finished saving the current processing or after the contents have been written to the mask register 12, the reset state is released and the AND
Allow circuits 16-19 to become active.
Also, this circuit temporarily suspends the current interrupt when you do not want to accept any interrupts or when you want to execute a high-priority interrupt controlled by the priority determination circuit 23 instead of the interrupt processing that is currently being processed. It is useful when storing. It is usually desirable for this circuit to be set after the mask register is set.

In order to show the interrupt operation of this processor, the interrupt processing for printout data transfer based on the interrupt request signal INT1 will be described below.

First, mask register 12-1 is reset and other mask registers are set. After this,
The EI instruction is executed and SRF/F14 is set. When the INT1 signal is input in this state,
The SRF/F 15 is reset by the output of the AND circuit 8, and the halt control circuit starts supplying the basic clock signal. At the same time, since the output of SRF/F14 is high level, AND circuits 16 and 1
7, 18, and 19 are in an active state. Therefore, AND circuit 1 to which the output of AND circuit 8 is input
The output of step 6 calls a printout data transfer execution subroutine. Here, the outputs of the AND circuits 9, 10, 11 are always fixed at low level by the interrupt mask register bits 12-2, 12-3, 12-4, so even if the interrupt request signals INT2, INTT, INTS, Note that even if a signal occurs, the halt state cannot be released by that signal. The halt state can only be canceled by the interrupt request signal INT1, and printout data transfer is forcibly executed. Similar operations occur for other interrupt request signals depending on the contents of the corresponding mask registers.

On the other hand, if the DI instruction is executed before the halt instruction is executed, the SRF/F is reset, so the outputs of the AND circuits 16, 17, 18, and 19 are always at a low level. Therefore, interrupt mask register bits 12-1, 12-2, 12-
3 and 12-4 can be used to select and release the interrupt request signal that releases the halt state, but all interrupt processing can be executed by the outputs of AND circuits 16, 17, 18, and 19. Since the interrupt is prohibited, the processor executes the instruction programmed after the halt instruction without accepting the interrupt. Therefore, depending on the state of the SRF/F 14, the operation of the processor after the halt state is released can also be selectively controlled. This allows the halt control circuit to be used for purposes other than quick response to interrupt signals.
A great advantage is obtained in that it enables intermittent operation in which the operation of the processor is temporarily stopped and an unrelated program continues to be executed based on the input of an interrupt request signal.

When the processor finishes the printout data transfer subroutine, it executes processing to create the next printout data, and after that, it maintains the halt state and quickly responds to the periodically generated INT1 signal. Make sure you have a system in place.

In this way, according to this embodiment, only desired interrupts are selected and accepted among multiple interrupt levels, and
As a result, the halt state can be released and interrupt processing can be executed immediately, so that interrupt processing can be performed at high speed without malfunctioning, and is particularly effective as a processor that controls a plurality of terminal devices. Further, as described above, this is particularly effective in a system in which the input timing of an interrupt signal is known in advance on the processor side.

It should be noted that it is clear that similar effects can be obtained for other interrupt processing as well. Furthermore, the priority determination circuit 2
It is also clear that by adding 3, more advanced interrupt processing can be executed while maintaining the above effects. Further, in this priority processing, the mask register 12 may be controlled instead of the circuit 23, but even in that case, it is desirable to perform halt control using a masked interrupt request signal.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing one embodiment of the present invention. 1... Memory section, 2... Processing section, 3... Timer circuit, 4... Serial interface circuit, 5
... Interrupt control circuit, 6 ... External interrupt request signal, 7 ... Halt control circuit, 100 ... Printer, 200 ... CRT. FIG. 2 is a circuit block diagram showing details of an interrupt control circuit according to an embodiment of the present invention. 8, 9, 10, 11, 16, 17, 18, 19
... AND circuit, 12 ... Interrupt mask register, 13 ... OR circuit, 14, 15 ... SR flip-flop, 20 ... Halt command control signal,
21...EI command control signal, 22...DI command control signal, 23...priority determination circuit.

Claims (1)

[Claims] 1. In an information processing device having a function of executing a plurality of interrupt processes, an accepting unit that accepts a request signal instructing the interrupt process, a selecting unit that selects a desired signal from among the accepted request signals, and an interrupt process. a processing unit that executes a processing unit; a stop unit that temporarily stops the operation of the processing unit; and a stop unit that controls the stop unit according to the request signal selected by the selection unit to release the stopped state and operate the processing unit. an interrupt process for determining whether or not to perform an interrupt process specified by an interrupt request signal used to cancel the stop state for the processing unit whose stop state is released; 1. An information processing apparatus, comprising: a determining unit, and determining whether or not to perform interrupt processing based on a selected interrupt request signal after releasing the stopped state of the processing unit.