TW202404286A - Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver - Google Patents

Abstract

An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit selects M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couples one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit generates the data select signal according to a first lane identifier corresponding to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the first lane identifier.

Description

Integrated circuitry in a clock forward interface receiver with channels for both clock and data channels

This disclosure relates to a clock forwarding interface, and more particularly to an integrated circuit in a clock forwarding interface receiver having channels for both clock and data channels, and clock forwarding The physical layer of the interface receiver.

Some communication systems utilize clock forwarding schemes to provide high-speed data transfer between transmitters and receivers. In this pulse forwarding scheme, a clock signal along with one or more data signals are transmitted from a transmitter to a receiver. For example, the receiver may include a clock forwarding interface having a clock lane and multiple data lanes. A clock signal on the clock channel together with a plurality of data signals on the data channels are forwarded from the transmitter to the receiver. Therefore, the receiver can utilize the clock signal forwarded by the transmitter to retrieve the data signals. Depending on the physical layer (PHY) specification used, each channel (ie, clock channel or data channel) in the clock forwarding interface can be a point-to-point (point) for clock or data transmission. -to-point), two-wire (two-wire) or three-wire (three-wire) interface.

Embodiments of the present disclosure provide an integrated circuit in a clock forward interface receiver with channels for both clock and data channels, and its associated physical layers.

Certain embodiments of the present disclosure include an integrated circuit in a transmitter. The integrated circuit includes a multi-channel interface, N signal generation circuits, a channel selection circuit and a control circuit. The multi-channel interface has N channels. N is an integer greater than 1. The N signal generating circuits are coupled to the multi-channel interface. The M signal generating circuits among the N signal generating circuits are respectively used to generate M clock signals, and the (N-M) signal generating circuits among the N signal generating circuits are used to generate (N-M) data signals respectively, M is a positive integer less than N. The channel selection circuit is coupled between the multi-channel interface and the N signal generating circuits, and is used to couple the M clock signals to M channels among the N channels respectively. The channels are selected as M clock channels, and one of the (N-M) data signals is coupled to one of the remaining (N-M) channels according to a data selection signal. The (N-M) channels serve as (N-M) data channels. The control circuit is used to generate the data selection signal according to a first channel identification code. The first channel identification code corresponds to the channel identification code of the channel among the (N-M) channels. The data selection signal has a signal value matching the first channel identification code.

Certain embodiments of the present disclosure include an integrated circuit in a transmitter. The integrated circuit includes a multi-channel interface, N signal generation circuits, a channel selection circuit and a control circuit. The multi-channel interface has N channels. N is an integer greater than 1. The N signal generating circuits are coupled to the multi-channel interface. The M signal generating circuits among the N signal generating circuits are respectively used to generate M clock signals, and the (N-M) signal generating circuits among the N signal generating circuits are used to generate (N-M) data signals respectively, M is a positive integer less than N. The channel selection circuit is coupled between the multi-channel interface and the N signal generation circuits, and is used to select M channels among the N channels as M clock channels, and the remaining (N-M) channels as ( N-M) data channels. In one mode, one of the N channels is selected as a clock channel for outputting one of the M clock signals based on a clock selection signal. In another mode, the channel of the N channels is used to output a data signal of the (N-M) data signals based on a data selection signal. The control circuit is used to generate the clock selection signal and the data selection signal. In the other mode, the control circuit is used to generate the data selection signal according to a first channel identification code. The first channel identification code corresponds to the channel identification code of the channel among the N channels, and the data selection signal has a signal value matching the channel identification code of the channel among the N channels.

Certain embodiments of the present disclosure include a physical layer of a receiver. The physical layer includes a physical medium attachment layer (PMA) and a physical coding sublayer (PCS). The physical media connection layer is used to output M first clock signals respectively related to M different clock domains. M is an integer greater than 1. The physical coding sub-layer has N first channels and is coupled to the physical media connection layer. N is an integer greater than M. The physical coding sublayer is used to select M channels among the N first channels as M first clock channels, and receive the M first clock signals via the M first clock channels. One or more channels among the remaining (N-M) channels among the N first channels serve as one or more first data channels.

By using at least one channel that is common to both the clock channel and the data channel, the physical layer on the receiving side can support different channel configurations on the transmitting side. For example, the physical layer can be divided into multiple physical interfaces to support multiple transmitters. In addition, a clock/data channel can be selected based on its channel identification code to facilitate clock/data channel selection.

The following disclosure provides various implementations, or examples, by which various features of the present disclosure can be implemented. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It should be understood that these descriptions are only examples and are not intended to limit the disclosure. In addition, this disclosure may reuse reference symbols and/or reference numerals in multiple embodiments. Such repeated use is for the purposes of brevity and clarity and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

Furthermore, it will be understood that if one component is described as being "connected to" or "coupled to" another component, it may be that the two components are directly connected or coupled, or that interactions between the two components may be present. Other intervening components.

The physical layer of a receiver using a clock forwarding interface can use a dedicated clock lane to receive the clock signal transmitted via the clock lane on the transmitter side. However, in applications where the clock channel and multiple data channels of the transmitter are interchangeable to meet certain communication requirements, this receiver will no longer be suitable. For example, the number of transmission devices located on the transmission side may change. For another example, a transmission device located on the transmission side may use clock channels and data channels interchangeably in certain operating scenarios.

The present disclosure provides an exemplary integrated circuit in a clock forwarding interface receiver with channels interchangeable between clock and data channels. In some embodiments, the exemplary integrated circuit may be implemented in a sublayer of the physical layer of the clock forward interface receiver, such as a physical medium attachment layer (PMA) or physical Coding sublayer (physical coding sublayer, PCS). Through the exemplary integrated circuit, the clock forwarding interface receiver can be adapted to be used interchangeably between a clock channel and a data channel, thereby supporting different lane arrangements on the transmit side.

FIG. 1 is a functional block diagram of an exemplary multi-lane communication system according to certain embodiments of the present disclosure. The multi-channel communication system 100 includes K transmitters TX[0]˜TX[K-1] located on a transmission side TS and a receiver 104 located on a receiving side RS, where K is a positive integer. Each of the K transmitters TX[0]~TX[K-1] may include a multi-channel interface (ie, one of the K multi-channel interfaces TF[0]~TF[K-1] ) to transmit clock information and data information. Each of the K multi-channel interfaces TF[0]˜TF[K-1] may include at least one clock channel and at least one data channel (not shown in Figure 1).

The receiver 104 is used to communicate with each of the K transmitters TX[0]˜TX[K-1] via a communication link 106 . A physical layer 108 of the receiver 104 may use a clock forwarding scheme to receive clock information and data information transmitted over the communication link 106 . Therefore, at least one clock signal can be forwarded from the transmitting side TS to the receiving side RS together with at least one data signal. The physical layer 108 includes an integrated circuit 110, which can be disposed in the physical media connection layer or the physical encoding sub-layer of the physical layer 108. The integrated circuit 110 can be adapted to various lane arrangements/configurations of the transmission side TS. For example, the integrated circuit 110 may operate in a mode to communicate with the transmission side TS, where the transmission side TS uses a single channel as a clock channel to transmit a clock signal. The integrated circuit 110 can operate in another mode to communicate with the transmission side TS, where the transmission side TS uses multiple channels as multiple clock channels to transmit multiple clock signals.

In this embodiment, the integrated circuit 110 includes (but is not limited to) a multi-channel interface 114, a channel selection circuit 120 and N sampling circuits RX[0]˜RX[N-1], where N is greater than 1. integer. The multi-channel interface 114 is connected to each of the K multi-channel interfaces TF[0]˜TF[K-1] via the communication link 106. The multi-channel interface 114 includes N channels LA[0]˜LA[N-1]. At least one channel among the N channels LA[0]˜LA[N-1] can be commonly used for the clock channel and the data channel, that is, the at least one channel can be used interchangeably between the clock channel and the data channel.

The channel selection circuit 120 is coupled to the multi-channel interface 114 and is used to select M channels among the N channels LA[0]˜LA[N-1] as M clock channels, where M is a positive integer less than N. . In addition, the channel selection circuit 120 can be used to output M signals CK ₀ ˜CK _(M-1) respectively on the M clock channels, that is, M clock signals. The remaining (NM) channels can be used as (NM) data channels respectively. At least one of the (NM) data channels can carry a data signal transmitted from the transmission side TS. In this embodiment, the M clock signals may be transmitted forward together with (NM) data signals (ie, (NM) signals DA ₀ ~ DA _(NM-1) on the (NM) channels) , so that each data channel can carry a data signal. It is worth noting that the channel selection circuit 120 can select any one of the N channels LA[0]˜LA[N-1] as the clock channel. Each channel among the N channels LA[0]~LA[N-1] can be used commonly for clock channels and data channels.

In this embodiment, the channel selection circuit 120 includes (but is not limited to) a plurality of selection stages 122 and 124 . The selection stage 122 has an input side S1 and an output side S2. The input side S1 is coupled to the multi-channel interface 114 . The selection stage 122 is used to couple M signals CK ₀ ˜CK _(M-1) on the M clock channels from the input side S1 to the output side S2 . The selection stage 124 is disposed between the output side S2 and the N sampling circuits RX[0]～RX[N-1] to couple each of the M signals CK ₀ to CK _(M-1) to N One or more sampling circuits among the sampling circuits RX[0]~RX[N-1]. For example, the selection stage 122 may be implemented as an N-to-M multiplexer, which may couple M channels among the N channels LA[0]˜LA[N-1] to Output side S2. The selection stage 124 may be implemented as M clock trees CT, each of which may assign a clock signal (ie, one of the M signals CK ₀ to CK _(M-1) ). Give more than one sampling circuit.

N sampling circuits RX[0]˜RX[N-1] are coupled to the multi-channel interface 114 and the channel selection circuit 120, and are used for sampling data according to the clock information and data information transmitted from the transmission side TS. In this embodiment, each of the N sampling circuits RX[0]˜RX[N-1] is used to receive M signals CK ₀ ˜CK _(M-1) on the M clock channels. one of them. In addition, (NM) sampling circuits among the N sampling circuits RX[0] ~ RX[N-1] are respectively coupled to the (NM) data channels for receiving (NM) on the (NM) data channels. NM) signals DA ₀ ~ DA _(NM-1) . Each of the (NM) sampling circuits is used to analyze one of the (NM) signals DA ₀ ~DA _(NM-1) according to one of the M signals CK ₀ ~CK ₍ M-1). Once sampled.

For example (but this disclosure is not limited thereto), each of the N sampling circuits RX[0]˜RX[N-1] may include a clock input terminal C _IN and a data input terminal D _IN . Each sampling circuit uses the signal input to the corresponding clock input terminal C _IN to sample the signal input to the corresponding data input terminal D _IN . By coupling M channels among the N channels LA[0]~LA[N-1] to the N clock input terminals C _IN of the N sampling circuits RX[0]~RX[N-1], The channel selection circuit 120 may select the M channels among the N channels LA[0]˜LA[N-1] as the M clock channels. Each of the remaining (NM) channels can be coupled to a data input terminal D _IN rather than coupled to the N clock input terminals C _IN , thereby serving as a data channel. Therefore, when each sampling circuit is coupled to a data channel via its included data input terminal D _IN and coupled to a clock channel via its included clock input terminal C _IN , the sampling circuit can utilize the clock channel to sample the signal on the data channel. In some embodiments, a clock channel can be coupled to one or more clock input terminals among the N clock input terminals C _IN , so that multiple sampling circuits can sample data according to the same clock signal.

The sampling results SR output by the N sampling circuits RX[0]~RX[N-1] include clock information and data information, which can be transmitted to the integrated circuit 110 including other functional blocks (not shown in Figure 1). output circuit 140 for further processing. For example, a sampling circuit coupled to one of the M signals CK ₀ ~CK _(M-1) and one of the (NM) signals DA ₀ ~DA _(NM-1) simultaneously can output a data signal , this data signal can be used as part of the sampling result SR. A sampling circuit coupled to one of the M signals CK ₀ ~CK _(M-1) but not coupled to the (NM) signals DA ₀ ~DA _(NM-1) can output a clock signal. The signal can be used as another part of the sampling result SR. The output circuit 140 can output M clock signals and (NM) data signals according to the sampling result SR. In some embodiments, the output circuit 140 may include a deserializer block. Each of the M clock signals and the (NM) data signals output from the output circuit 140 may be a multi-bit parallel output signal.

In some embodiments, the transmitter may provide information indicating which channel should be used as a clock channel. According to the information provided by the transmitter, the receiver 104 can configure the channel selection circuit 120 to select the appropriate channel as the clock channel. The receiver 104 can correctly use the signal on the clock channel to process the signals on one or more data channels.

In some embodiments, the transmitter can generate a clock signal by repeating a specific bit pattern to indicate which channel on the transmitting side RS should be used as a clock channel. For example, the transmitter may repeatedly send a one-bit pattern "01", such as "01010101", as a clock signal. The receiver 104 can identify which channel can be used as the clock channel by checking whether the bit stream received by a channel has a repeated bit pattern. In other words, the receiver 104 can configure/set the channel selection circuit 120 according to the detection result of a predetermined repeated bit pattern.

In some embodiments, a system application (not shown in FIG. 1 ) associated with the receiver 104 may determine which channel of the multi-channel interface 104 should be used as a clock channel. According to the instructions sent by the system application, the receiver 104 can configure/set the channel selection circuit 120 to select the appropriate channel as the clock channel.

Please note that the above is for illustrative purposes only and is not intended to limit the scope of this disclosure. In some embodiments, the channel selection circuit 120 shown in FIG. 1 may be implemented with a single selection stage or more than two selection stages without departing from the scope of the present disclosure. In some embodiments, at least one of the N sampling circuits RX[0]˜RX[N-1] shown in FIG. 1 can be implemented using a sampling circuit with more than one data output terminal.

The physical layer 108 of the receiving side RS can support different channel configurations of the transmitting side TS by using at least one channel that is common to both the clock channel and the data channel. In order to further explain the lane interchange scheme of the receiving side RS, some embodiments of the lane configuration of the transmitting side TS are provided below. A person of ordinary skill in the art should understand that the channel swapping scheme of the receiving side RS can support other channel configurations of the transmitting side TS without departing from the scope of this disclosure.

2A to 2C illustrate schematic diagrams of different modes of the receiver 104 shown in FIG. 1 according to certain embodiments of the present disclosure. The receiver 104 can operate in different modes OP1 to OP3 respectively according to different channel configurations of the transmission side TS. In the mode OP1 shown in FIG. 2A , the receiver 104 can be used to receive clock information and data information provided by a single transmitter. For convenience of explanation, the single transmitter can be represented by the transmitter TX[0] shown in FIG. 1 . The multi-channel interface TF[0] of the transmitter TX[0] includes multiple channels L0[0]~L0[P], where P is a positive integer. The transmitter TX[0] is used to transmit the clock signal C0 on the channel L0[P] together with the P data signals D0 ₀ ~D0 _{(P-1) on the P channels L0[0]~L0[P-1]} output together.

The receiver 104 is used to select one of the N channels LA[0]˜LA[N-1] as a clock channel (ie, M=1) to receive the clock signal C0 via the communication link 106 . P channels among the remaining (N-1) channels can be used as P data channels to receive P data signals D0 ₀ ~D0 _(P-1) . In this embodiment, the sum of the number of data signals and the number of clock signals transmitted from the transmitter TX[0] may be equal to the number of channels of the multi-channel interface 114 (ie, P+1= N). Therefore, each of the N channels LA[0]~LA[N-1] can be used to receive the signal information provided by the transmission side TX[0]. The receiver 104 may select channel LA[N-1] (ie, the channel to which the clock signal C0 on channel L0[P] is input) as the clock channel. The remaining (N-1) channels LA[0]~LA[N-2] can be used as (N-1) data channels to receive P data signals D0 ₀ ~D0 _(P-1) .

In the mode OP2 shown in FIG. 2B , the receiver 104 can be used to receive clock information and data information provided by multiple transmitters, in which multiple channels of the transmitting side TS can be used as multiple clock channels to carry multiple clocks. Pulse signal. For example, when operating in bifurcation mode, the physical layer 108 can be divided into multiple physical layers that are different from each other to support the K transmitters TX[0]˜TX[K-1] shown in FIG. 1 Multiple transmitters. For convenience of explanation, in this embodiment, the multiple transmitters may be represented by two transmitters TX[1] and TX[2]. The multi-channel interface TF[1] of the transmitter TX[1] includes multiple channels L1[0]~L1[Q], where Q is a positive integer. The transmitter TX[1] is used to transmit the clock signal C1 on the channel L1[Q] together with the Q data signals D1 ₀ ~ D1 _{(Q-1) on the Q channels L1[0] ~ L1 [Q-1]} output together. The multi-channel interface TF[2] of the transmitter TX[2] includes multiple channels L2[0]~L2[R], where R is a positive integer. The transmitter TX[2] is used to transmit the clock signal C2 on the channel L2[R] together with the R data signals D2 ₀ ~ D2 _{(R-1) on the R channels L2[0] ~ L2 [R-1]} output together. Since both channels of the transmission side TS are used as clock channels in mode OP2, the channel configuration of the transmission side TS in mode OP2 is different from the channel configuration of the transmission side TS in mode OP1, which uses a single channel as the clock aisle.

The receiver 104 can select two channels among the N channels LA[0]~LA[N-1] as two clock channels (that is, M=2) in response to the mode OP2 to receive the data transmitted by the transmission side TS. A plurality of clock signals C1 and C2. The (Q+R) channels among the remaining (N-2) channels can be used as (Q+R) data channels to receive a plurality of data signals D1 ₀ ~ D1 _(Q-1) and D2 ₀ ~ D2 _{( R-1)} . In this embodiment, the sum of the number of data signals and the number of clock signals transmitted from the plurality of transmitters TX[1] and TX[2] may be equal to the number of channels of the multi-channel interface 114 (That is, Q+R+2=N). Therefore, each of the N channels LA[0]~LA[N-1] can be used to receive signal information provided by a plurality of transmitters TX[1] and TX[2]. The receiver 104 can select the two channels LA[J] and LA[N-1] (that is, the channels to which the plurality of clock signals C1 and C2 are input) as two clock channels. J is an integer between 0 and N-2. The remaining (N-2) channels can be used as (N-2) data channels to receive a plurality of data signals D1 ₀ ~D1 _(Q-1) and D2 ₀ ~D2 _(R-1) . Since channel LA[J] can be used as a data channel in mode OP1 and as a clock channel in mode OP2, the integrated circuit 110 can support not only a single transmitter but also multiple transmitters.

In some embodiments, one or more transmitters have channels that can be used interchangeably between data channels and clock channels to provide different channel configurations on the transmit side TS. For example, in the mode OP3 shown in FIG. 2C , the receiver 104 can be used to receive the clock information and data information provided by the transmitter TX[0], where the transmitter TX[0] can receive the signal from the channel L0[0] Transmit clock signal C0, and transmit P data signals D0 ₀ ~ D0 _(P-1) from P channels L0[1] ~ L0[P]. Compared with mode OP1, the transmitter TX[0] can cause the signals transmitted on the clock channel and the data channel to be interchanged with each other. Therefore, channel L0[0], which is a data channel in mode OP1, can be used as a clock channel in mode OP3, and channel L0[P], which is a clock channel in mode OP1, can be used as a data channel in mode OP3. The receiver 140 may select channel LA[0] as the clock channel to receive the clock signal C0. P channels among the remaining (N-1) channels LA[1]~LA[N-1] can be used as P data channels to receive P data signals D0 ₀ ~D0 _(P-1) . By using channel LA[0] and channel LA[N-1] interchangeably between data channels and clock channels respectively, the integrated circuit 110 can support a transmitter TX that can use clock channels and data channels interchangeably. 0].

To facilitate understanding of the present disclosure, certain embodiments are provided below to further illustrate the clock forwarding interface receiver using the channel swapping scheme. Those of ordinary skill in the art should understand that other embodiments of the channel interchange scheme described based on the integrated circuit 110 or the receiver 104 shown in FIG. 1 follow the spirit of the present disclosure and fall within the scope of the present disclosure.

FIG. 3 is a schematic diagram of a specific implementation of the integrated circuit 110 shown in FIG. 1 according to certain embodiments of the present disclosure. The integrated circuit 310 is disposed in a physical layer of the receiver 300, such as a physical media connection layer, to receive clock information and data information transmitted by one or more transmitters on the transmission side. The integrated circuit 310 can be an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be used commonly for clock channels and data channels, N=6). In this embodiment, the integrated circuit 310 may include a plurality of sampling circuits RX[0]˜RX[5] as shown in FIG. 1 , a multi-channel interface 314 and a channel selection circuit 320 . The multi-channel interface 314 and the channel selection circuit 320 can be respectively used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 .

In this embodiment, each of the plurality of channels LA[0]˜LA[5] of the multi-channel interface 314 can be implemented using a two-wire lane. A two-wire channel is a differential lane that includes a pair of signal pins and an amplifier. In some embodiments, each of the plurality of channels LA[0]-LA[5] may be implemented using other types of channels, such as single-wire channels or channels with more than two wires, without departing from the teachings of the present disclosure. Scope.

The channel selection circuit 320 is used to select one or more channels among the plurality of channels LA[0]˜LA[5] as one or more clock channels. The channel selection circuit 320 may include a plurality of selection stages 322 and 324, which may serve as embodiments of the plurality of selection stages 122 and 124 shown in FIG. 1, respectively. In this embodiment, the selection stage 322 may couple one or two channels to the selection stage 324 according to the mode of the integrated circuit 310 . The selection stage 322 includes (but is not limited to) a plurality of channel selection units 322.0 and 322.1. The channel selection unit 322.0 is used to couple a plurality of channels LA[0]˜LA[2] from the input side S01 to the output side S02 according to a clock selection signal SEL ₀₀ . The channel selection unit 322.1 is used to couple a plurality of channels LA[3]˜LA[5] from the input side S11 to the output side S12 according to a clock selection signal SEL ₀₁ .

The selection stage 324 may distribute the signals on each channel selected by the selection stage 322 to more than one sampling circuit. The selection stage 324 includes (but is not limited to) a plurality of channel selection units 324.0˜324.5. The plurality of channel selection units 324.0-324.5 can select a signal according to the corresponding clock (that is, one of the plurality of clock selection signals SEL ₁₀ -SEL ₁₅ ). The plurality of output sides S02 and S12 are coupled to the corresponding Sampling circuit. The description of the plurality of clock selection signals SEL ₀₀ , SEL ₀₁ and SEL ₁₀ ~ SEL ₁₅ will be discussed later.

The clock input terminals C _IN of the plurality of sampling circuits RX[0]˜RX[5] are respectively coupled to the respective output terminals of the plurality of channel selection units 324.0˜324.5. The data input terminals D _IN of the plurality of sampling circuits RX[0]˜RX[5] are respectively coupled to the plurality of channels LA[0]˜LA[5]. In this embodiment, each of the plurality of sampling circuits RX[0]˜RX[5] can use a flip-flop (such as a D-type flip-flop). ) to implement for data sampling. Those with ordinary skill in the art should understand that each of the plurality of sampling circuits RX[0]˜RX[5] can be implemented using other types of sampling circuits without departing from the scope of the present disclosure.

4A to 4C illustrate operation diagrams of the integrated circuit 310 shown in FIG. 3 according to certain embodiments of the present disclosure. In the embodiment shown in FIGS. 4A and 4B , the integrated circuit 310 operates in a mode similar to the modes OP1 / OP3 shown in FIGS. 2A / 2C to receive a single clock signal from the multi-channel interface 314 . The channel selection circuit 320 can select one of the plurality of channels LA[0]˜LA[5] as a clock channel to receive the clock signal. The channel selection circuit 320 is used to couple the signal on the clock channel (that is, the clock signal) to each of the plurality of sampling circuits RX[0]˜RX[5]. In the embodiment shown in FIG. 4C , the integrated circuit 310 operates in a mode similar to the mode OP2 shown in FIG. 2B to receive multiple clock signals from the multi-channel interface 314 . The channel selection circuit 320 can select two channels among the plurality of channels LA[0]˜LA[5] as two clock channels to receive the plurality of clock signals. The channel selection circuit 320 is used to couple the signal on each clock channel to one or more sampling circuits among the plurality of sampling circuits RX[0]˜RX[5].

First, please refer to FIG. 4A. The integrated circuit 310 can support the "5D1C" channel configuration, in which a clock signal 5D_CLK is input to one of the plurality of channels LA[0]~LA[2] (in this embodiment, Take input to channel LA[0] as an example to illustrate). Five data signals 5D ₀ ~ 5D ₄ are input to the remaining five channels. The channel selection unit 322.0 couples the channel LA[0] to the output side S02 according to the clock selection signal SEL ₀₀ , so as to select the channel LA[0] as the clock channel. The plurality of channels LA[1] and LA[2] are not coupled to the output side S02. In addition, each of the plurality of channel selection units 324.0˜324.5 can couple the output side S02 of the channel selection unit 322.0 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the clock signal 5D_CLK can be sent to the respective clock input terminals C _IN of a plurality of sampling circuits RX[0]˜RX[5]. A plurality of sampling circuits RX[1]˜RX[5] respectively coupled to a plurality of channels LA[1]˜LA[5] can sample the plurality of data signals 5D ₀ ˜5D ₄ according to the clock signal 5D_CLK.

Referring to FIG. 4B, the integrated circuit 310 can support the "5D1C" channel configuration, in which the clock signal 5D_CLK is input to one of the plurality of channels LA[3]~LA[5] (in this embodiment, input Take channel LA[3] as an example to illustrate). A plurality of data signals 5D ₀ ~ 5D ₄ are input to the remaining five channels. The channel selection unit 322.1 couples the channel LA[3] to the output side S12 according to the clock selection signal SEL ₀₁ , so as to select the channel LA[3] as the clock channel. Each channel selection unit among the plurality of channel selection units 324.0˜324.5 can couple the output side S12 of the channel selection unit 322.1 to the corresponding sampling circuit. Therefore, a plurality of sampling circuits RX[0]～RX[2], RX[4] and RX[ are respectively coupled to a plurality of channels LA[0]～LA[2], LA[4] and LA[5]. 5] A plurality of data signals 5D ₀ ~ 5D ₄ can be sampled according to the clock signal 5D_CLK.

Referring to Figure 4C, the integrated circuit 310 can be used as two circuit interfaces, both of which can support "2D1C" channel configuration (two channels as data channels and one channel as a clock channel). In this embodiment, a clock signal 2D_CLK0 is input to one of the plurality of channels LA[0]˜LA[2], such as channel LA[0]. The relevant data signals 2D ₀₀ and 2D ₀₁ can be input to the remaining two channels. In addition, a clock signal 2D_CLK1 is input to one of the plurality of channels LA[3]˜LA[5], such as channel LA[3]. Relevant data signals 2D ₁₀ and 2D ₁₁ can be input to the remaining two channels.

The channel selection unit 322.0 is used to couple the channel LA[0] to the output side S02 according to the clock selection signal SEL ₀₀ . Each channel selection unit among the plurality of channel selection units 324.0˜324.2 is used to couple the output side S02 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the plurality of sampling circuits RX[1] and RX[2] respectively coupled to the plurality of channels LA[1] and LA[2] can sample the plurality of data signals 2D ₀₀ and 2D ₀₁ according to the clock signal 2D_CLK0 . Similarly, the channel selection unit 322.1 is used to couple the channel LA[3] to the output side S12 according to the clock selection signal SEL ₀₁ . Each channel selection unit among the plurality of channel selection units 324.3˜324.5 is used to couple the output side S12 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the plurality of sampling circuits RX[4] and RX[5] respectively coupled to the plurality of channels LA[4] and LA[5] can sample the plurality of data signals 2D ₁₀ and 2D ₁₁ according to the clock signal 2D_CLK1 . Because the signal level/signal value of each of the plurality of clock selection signals SEL ₁₀ ~ SEL ₁₂ may be different from the signal level/signal value of each of the plurality of clock selection signals SEL ₁₃ ~ SEL ₁₅ signal level/signal value, therefore, the plurality of channel selection units 324.0～324.5 can allocate different clock signals 2D_CLK0 and 2D_CLK1 to the plurality of sampling circuits RX[0]～RX[5].

By referring to the selection operations described in FIGS. 4A and 4B , the selection stage 322 and the selection stage 324 shown in FIG. 3 can be respectively used as a 6-to-1 multiplexer (6-to-1 multiplexer) and a clock tree, so as to Supports "5D1C" channel configuration. In addition, by selecting operations described with reference to FIG. 4C , the selection stage 322 shown in FIG. 3 can function as two 3-to-1 multiplexers (3-to-1 multiplexers), and the selection stage 324 shown in FIG. 3 can As two clock trees, it further supports "2D1C" channel configuration in bifurcated mode. Therefore, the channel selection circuit 320 shown in FIG. 3 can support one or more transmitters by operating as a 6-to-M multiplexer and M clock trees, where M can be equal to 1 or 2 (depending on the mode of IC 310).

Please note that the circuit structures of the plurality of selection stages 322 and 324 shown in FIG. 3 are only for convenience of illustration and are not intended to limit the scope of the present disclosure. In some embodiments, selection stage 322 may be implemented with other circuit structures to provide multiplexer operation. In some embodiments, selection stage 324 may be implemented with other circuit structures to construct one or more clock trees. In some embodiments, the signal on each selected clock channel (such as a clock signal) may not be coupled to the data input terminal D _IN of each sampling circuit. For example, when the channel LA[0] shown in FIG. 3 is selected as the clock channel, the channel LA[0] may not be coupled to the data input terminal D _IN of each sampling circuit.

In some embodiments, a plurality of clock selection signals SEL ₁₀ -SEL ₁₂ may be implemented using the same clock selection signal, or may have the same signal value. In some embodiments, a plurality of clock selection signals SEL ₁₃ - SEL ₁₅ may be implemented using the same clock selection signal, or may have the same signal value. These design modifications and changes all follow the spirit of this disclosure and fall within the scope of this disclosure.

5A to 5C are schematic diagrams of other specific implementations of the integrated circuit 110 shown in FIG. 1 according to certain embodiments of the present disclosure. Each of the plurality of integrated circuits 510A to 510C shown in FIGS. 5A to 5C can be used as the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels). , N=6) embodiment. In these embodiments, the channel selection circuit 120 shown in FIG. 1 can be implemented using different clock tree groups to support different channel configurations on the transmission side. Each clock tree group includes at least one clock tree circuit, and one clock tree circuit includes a multiplexer and a clock tree.

See Figure 5A first. Except for the channel selection circuit 520A, the structure of the integrated circuit 510A is similar/identical to the structure of the integrated circuit 310 shown in FIG. 3 . The circuit operation provided by the channel selection circuit 520A may be similar/identical to the circuit operation of the channel selection circuit 320 described with reference to FIGS. 4A/4B. In this embodiment, the channel selection circuit 520A can be implemented using a clock tree group G1. The clock tree group G1 has a clock tree circuit, which includes a multiplexer 522A (ie, a 6-to-1 multiplexer) and a clock tree 524A. The multiplexer 522A can select one of the plurality of channels LA[0]~LA[5] as a clock channel according to a clock selection signal SEL _A , and then output the signal on the selected channel from an output terminal T _5D . The clock tree 524A can distribute the signal on the output terminal T _5D to each of the plurality of sampling circuits RX[0]˜RX[5]. Please note that the circuit structure of the selection stage 322 shown in FIGS. 4A/4B can be used as an implementation of the multiplexer 522A. In addition, or alternatively, the circuit structure of the selection stage 324 shown in FIGS. 4A/4B can be used as an implementation of the clock tree 524A. Since a person with ordinary knowledge in the art should be able to understand the operation details of the channel selection circuit 520A shown in Figure 5A in the "5D1C" channel configuration after reading the paragraphs related to Figure 3, Figure 4A and Figure 4B, therefore, regarding Further explanation of channel selection will not be repeated here.

See Figure 5B. Except for the channel selection circuit 520B, the structure of the integrated circuit 510B is similar/identical to the structure of the integrated circuit 310 shown in FIG. 3 . The circuit operation provided by the channel selection circuit 520B may be similar/identical to the circuit operation of the channel selection circuit 320 described with reference to FIG. 4C . In this embodiment, the channel selection circuit 520B can be implemented using a clock tree group G2. The clock tree group G2 has two clock tree circuits, one of which includes a multiplexer 522B.0 and a clock tree 524B.0, and the other clock tree circuit includes a multiplexer 522B.1 and a clock tree. Vein Tree 524B.1. The multiplexer 522B.0 (that is, a 3-to-1 multiplexer) can select one of the plurality of channels LA[0]~LA[2] as the clock channel according to a clock selection signal SEL _B0 . The clock tree 524B.0 can distribute the signal on the output terminal T _2D0 to each of the plurality of sampling circuits RX[0]˜RX[2]. Multiplexer 522B.1 (that is, a 3-to-1 multiplexer) can select one of the plurality of channels LA[3]~LA[5] as a clock channel according to a clock selection signal SEL _B1 . The clock tree 524B.1 can distribute the signal on the output terminal T _2D1 to each of the plurality of sampling circuits RX[3]˜RX[5]. Please note that the circuit structure of the selection stage 322 shown in FIG. 4C can be used as an implementation of a plurality of multiplexers 522B.0 and 522B.1. In addition, or alternatively, the circuit structure of the selection stage 324 shown in FIG. 4C can be used as an implementation of a plurality of clock trees 524B.0 and 524B.1. Since a person with ordinary knowledge in the art should be able to understand the operation details of the channel selection circuit 520B shown in Figure 5B in the "2D1C" channel configuration after reading the paragraphs related to Figure 3 and Figure 4C, therefore, regarding channel selection Further explanation will not be given here.

See Figure 5C. Except for the channel selection circuit 520C, the structure of the integrated circuit 510C is similar/identical to the structure of the integrated circuit 310 shown in FIG. 3 . The channel selection circuit 520C may be implemented using a clock tree group G3. Clock tree group G3 has three clock tree circuits, thereby supporting the transmission side where three clock channels and their associated three data channels are configured. In this embodiment, the channel selection circuit 520C includes a plurality of multiplexers 522C.0˜522C.2 (ie, a plurality of 2-to-1 multiplexers) and a plurality of clock trees 524C.0˜524C.2. The multiplexer 522C.0 can select one of the plurality of channels LA[0] and LA[1] as the clock channel according to a clock selection signal SEL _C0 . The multiplexer 522C.1 can select one of the plurality of channels LA[2] and LA[3] as the clock channel according to a clock selection signal SEL _C1 . The multiplexer 522C.2 can select one of the plurality of channels LA[4] and LA[5] as the clock channel according to a clock selection signal SEL _C2 . The clock tree 524C.0 can distribute the signal on the output terminal T _1D0 to each of the plurality of sampling circuits RX[0] and RX[1]. The clock tree 524C.1 can distribute the signal on the output terminal T _1D1 to each of the plurality of sampling circuits RX[2] and RX[3]. The clock tree 524C.2 can distribute the signal on the output terminal T _1D2 to each of the plurality of sampling circuits RX[4] and RX[5].

For example, a plurality of multiplexers 522C.0˜522C.2 can select a plurality of channels LA[0], LA[2] and LA[4] as a plurality of clock channels. Therefore, the sampling circuit RX[1] can sample the signal on channel LA[1] according to the signal on channel LA[0]. The sampling circuit RX[3] can sample the signal on channel LA[3] according to the signal on channel LA[2]. The sampling circuit RX[5] can sample the signal on channel LA[5] according to the signal on channel LA[4]. The integrated circuit 510C can be divided into three interfaces, and each interface can support "1D1C" channel configuration (one channel can be used as a clock channel, and the other channel can be used as a data channel).

FIG. 6 is a schematic diagram of another implementation of the integrated circuit 110 shown in FIG. 1 according to certain embodiments of the present disclosure. The integrated circuit 610 can be an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be used commonly for clock channels and data channels, N=6). In this embodiment, the integrated circuit 610 may use a plurality of clock tree groups G1 to G3 as shown in FIGS. 5A to 5C to support different channel configurations. The integrated circuit 610 includes a channel selection circuit 620, the multi-channel interface 314 shown in FIG. 3 and a plurality of sampling circuits RX[0]˜RX[5]. The channel selection circuit 620 may be an embodiment of the channel selection circuit 120 shown in FIG. 1 and may include a plurality of selection stages 622 and 624.

Selection stage 622 may include multiplexers 522A of clock tree group G1 shown in FIG. 5A , multiplexers 522B.0 and 522B.1 of clock tree group G2 shown in FIG. 5B , and FIG. 5C Shown is a plurality of multiplexers 522C.0-522C.2 of clock tree group G3. The selection stage 624 may include a plurality of multiplexers 624.0-624.5. The multiplexer 624.0 is used to couple one of the plurality of output terminals T _5D , T _2D0 and T _1D0 to the clock input terminal C _IN of the sampling circuit RX[0]. The multiplexer 624.1 is used to couple one of the plurality of output terminals T _5D , T _2D0 and T _1D0 to the clock input terminal C _IN of the sampling circuit RX[1]. The multiplexer 624.2 is used to couple one of the plurality of output terminals T _5D , T _2D0 and T _1D1 to the clock input terminal C _IN of the sampling circuit RX[2]. The multiplexer 624.3 is used to couple one of the plurality of output terminals T _5D , T _2D1 and T _1D1 to the clock input terminal C _IN of the sampling circuit RX[3]. The multiplexer 624.4 is used to couple one of the plurality of output terminals T _5D , T _2D1 and T _1D2 to the clock input terminal C _IN of the sampling circuit RX[4]. The multiplexer 624.5 is used to couple one of the plurality of output terminals T _5D , T _2D1 and T _1D2 to the clock input terminal C _IN of the sampling circuit RX[5].

In the mode where the integrated circuit 610 is used to support the "5D1C" channel configuration, each of the multiplexers 624.0˜624.5 is used to couple the output terminal T _5D to the corresponding sampling circuit, so that the output terminal The clock signal 5D_CLK on T _5D can be assigned to each sampling circuit. For example, the multiplexer 522A can couple the channel LA[0] to the output terminal T _5D according to the clock selection signal SEL _A. The remaining channels LA[1]~LA[5] can be used as data channels. A plurality of sampling circuits RX[1]˜RX[5] respectively coupled to a plurality of channels LA[1]˜LA[5] can perform data sampling operations according to the clock signal 5D_CLK. Please note that a plurality of multiplexers 624.0˜624.5 that can serve as a clock tree to distribute the clock signal 5D_CLK can be used to implement the clock tree 524A in the clock tree group G1 shown in FIG. 5A.

In another mode in which the integrated circuit 610 is used to support "2D1C" lane configurations with bifurcation, each of the plurality of multiplexers 624.0-624.2 is used to couple the output terminal T _2D0 For the corresponding sampling circuit, the clock signal 2D_CLK0 on the output terminal T _2D0 can be distributed to each of the plurality of sampling circuits RX[0]˜RX[2]. Each multiplexer among the plurality of multiplexers 624.3˜624.5 is used to couple the output terminal T _2D1 to the corresponding sampling circuit, so that the clock signal 2D_CLK1 on the output terminal T _2D1 can be distributed to the plurality of sampling circuits RX[3 ]~RX[5] for each sampling circuit. A plurality of multiplexers 624.0˜624.5 may be used to implement a plurality of clock trees 524B.0 and 524B.1 in the clock tree group G2 shown in FIG. 5B. Therefore, the plurality of sampling circuits RX[0]~RX[5] can be divided into two groups of sampling circuits. The physical layer where the integrated circuit 610 is located can be operated into two separate physical layers. One of the physical layers includes a plurality of channels LA[0]~LA[2] and a plurality of sampling circuits RX[0]~RX[2 ], and another physical layer includes a plurality of channels LA[3]~LA[5] and a plurality of sampling circuits RX[3]~RX[5].

In another mode in which the integrated circuit 610 is used to support a "1D1C" bifurcated channel configuration, each multiplexer of the plurality of multiplexers 624.0 and 624.1 is used to couple the output terminal T _1D0 to a corresponding sampling circuit , so that the clock signal 1D_CLK0 on the output terminal T _1D0 can be distributed to each of the plurality of sampling circuits RX[0] and RX[1]. Similarly, each multiplexer in the plurality of multiplexers 624.2 and 624.3 is used to couple the output terminal T _1D1 to a corresponding sampling circuit, so that the clock signal 1D_CLK1 on the output terminal T _1D1 can be distributed to a plurality of sampling circuits. Each sampling circuit in RX[2] and RX[3]. Each multiplexer in the plurality of multiplexers 624.4 and 624.5 is used to couple the output terminal T _1D2 to the corresponding sampling circuit, so that the clock signal 1D_CLK2 on the output terminal T _1D2 can be distributed to the plurality of sampling circuits RX [4 ] and each sampling circuit in RX[5]. A plurality of multiplexers 624.0-624.5 may be used to implement a plurality of clock trees 524C.0-524C.2 in the clock tree group G3 shown in FIG. 5C. Therefore, the plurality of sampling circuits RX[0]~RX[5] can be divided into three groups of sampling circuits. The physical layer in which the integrated circuit 610 is located can operate into three separate physical layers to support three transmitters.

With a plurality of multiplexers 522A, 522B.0, 522B.1 and 522C.0~522C.2, the selection stage 622 can be operated into 6 pairs of M multiplexers, where and M can be equal to 1, 2 or 3 (depending on in the integrated circuit 610 mode). In addition, with a plurality of multiplexers 624.0-624.5, the selection stage 624 can operate into M clock trees, where and M can be equal to 1, 2, or 3 (depending on the mode of the integrated circuit 610). Therefore, the integrated circuit 610 can divide the plurality of lanes LA[0]˜LA[5] into one or more lane groups (groups of lanes), where each lane group includes a clock lane and a data lane to support a or multiple transmitters.

The circuit structure and operation described above with reference to FIG. 6 are for convenience of illustration only and are not intended to limit the scope of the present disclosure. In some embodiments, the integrated circuit 610 can operate in a bifurcated mode supporting both a "3D1C" channel configuration and a "1D1C" channel configuration. For example, a plurality of multiplexers 624.0～624.3 can couple the output terminal T _5D to the corresponding sampling circuit, so that the clock signal 5D_CLK on the output terminal T _5D can be distributed to a plurality of sampling circuits RX[0]～ Each sampling circuit in RX[3]. Each multiplexer in the plurality of multiplexers 624.4 and 624.5 is used to couple the output terminal T _1D2 to the corresponding sampling circuit, so that the clock signal 1D_CLK2 on the output terminal T _1D2 can be distributed to the plurality of sampling circuits RX [4 ] and each sampling circuit in RX[5]. Therefore, the physical layer in which the integrated circuit 610 is located can be operated into two separate physical layers to support two transmitters with different numbers of data channels.

In some embodiments, it is possible to not use a channel as a data channel when transmitting data. For example, when used to support a "5D1C" channel configuration, the integrated circuit 610 may use five or less than five data channels to receive data information transmitted from the transmitting side. The number of data channels used may depend on the number of data signals sent to the multi-channel interface 314 .

In some embodiments, the selection stage 622 may be implemented using other multiplexer circuits to select one or more channels according to the mode of the integrated circuit 610 . In some embodiments, the selection stage 624 may be implemented using other clock tree structures to allocate one or more clock signals in response to the mode of the integrated circuit 610 . These design modifications and changes all follow the spirit of this disclosure and fall within the scope of this disclosure.

FIG. 7 is a schematic diagram of another implementation of the integrated circuit 110 shown in FIG. 1 according to certain embodiments of the present disclosure. The integrated circuit 710 can be an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be used commonly for clock channels and data channels, N=6). In this embodiment, the integrated circuit 710 may be disposed in the physical media connection layer in the physical layer to perform serial-to-parallel conversion.

The integrated circuit 710 includes a channel selection circuit 720, a plurality of serial-to-parallel converters (hereinafter referred to as "S2P converters") 730.0-730.5, and the multi-channel interface 314 shown in Figure 3 . The channel selection circuit 720 may be an embodiment of the channel selection circuit 120 shown in FIG. 1 , and may include a plurality of selection stages 722 and 724 . Selection stage 722 may include a plurality of multiplexers 722.0 and 722.1. The multiplexer 722.0 is used to couple a plurality of channels LA[0]˜LA[5] to an output terminal T ₇₀ according to a clock selection signal SEL ₇₀ . The multiplexer 722.0 is used to couple a plurality of channels LA[0]˜LA[5] to an output terminal T ₇₁ according to a clock selection signal SEL ₇₁ . The selection stage 724 may be implemented to include a multiplexer 724.0, which may couple a plurality of output terminals T ₇₀ and T ₇₁ to an output terminal T ₇₂ according to a clock selection signal SEL ₇₂ .

Each S2P converter among the plurality of S2P converters 730.0˜730.5 is used to output a multi-bit parallel output signal. The multi-bit parallel output signal may be a parallel data signal, a byte data signal, a parallel clock signal or a byte clock signal. byte clock signal). In this embodiment, each S2P converter includes a sampling circuit and a deserializer (that is, one of the plurality of sampling circuits RX[0]˜RX[5] shown in Figure 3 and a plurality of One of the deserializers DS[0]~DS[5]). The plurality of deserializers DS[0]˜DS[5] can be used as an output circuit 740, which can output one or more clock signals according to the sampling results SR of the plurality of sampling circuits RX[0]˜RX[5].

In the mode where the integrated circuit 710 is used to support the "5D1C" channel configuration, the multiplexer 724.0 is used to couple the output terminal T ₇₀ to the output terminal T ₇₂ . When the multiplexer 722.0 selects one of the plurality of channels LA[0]~LA[5] as a clock channel, the signal on the clock channel can be coupled to the output terminal T ₇₀ and distributed to a plurality of The respective clock input terminals C _IN of the sampling circuits RX[0]~RX[5]. For example, multiplexer 722.0 may select channel LA[0] as the clock channel. Each of the plurality of sampling circuits RX[1] to RX[5] can sample data according to the same clock signal (that is, the signal on channel LA[0]). The deserializer DS[0] can output a clock signal (ie, a parallel clock signal) according to the sampling result SR. Please note that in this mode, a plurality of multiplexers 722.0 and 724.0 can serve as an embodiment of the clock tree group G1 shown in FIG. 5A.

In a mode in which the integrated circuit 710 is used to support a "2D1C" bifurcated channel configuration, the multiplexer 724.0 is used to couple the output terminal T ₇₁ to the output terminal T ₇₂ . When the multiplexer 722.0 selects one of the plurality of channels LA[0]~LA[5] as a clock channel, the multiplexer 722.1 can select one of the plurality of channels LA[0]~LA[5]. The other option is a clock channel. Therefore, the signals on the remaining channels can be sampled based on the signals on the selected clock channel. Two of the plurality of deserializers DS[0] to DS[5] can output two clock signals according to the sampling result SR. For example, multiplexer 722.0 can select channel LA[0] as the clock channel, and each sampling circuit in the plurality of sampling circuits RX[1] and RX[2] can be based on the signal on channel LA[0]. Carry out data sampling. Multiplexer 722.1 can select channel LA[3] as the clock channel, and each sampling circuit in the plurality of sampling circuits RX[4] and RX[5] can sample data according to the signal on channel LA[3]. The deserializer DS[0] can output a parallel clock signal related to the signal on the channel LA[0], and the plurality of deserializers DS[1] and DS[2] can respectively output the plurality of channels LA[ 1] A plurality of parallel data signals associated with respective signals on LA[2]. In addition, the deserializer DS[3] can output a parallel clock signal related to the signal on the channel LA[3], and a plurality of deserializers DS[4] and DS[5] can respectively output a plurality of channels. A plurality of parallel data signals related to the respective signals on LA[4] and LA[5]. In this mode, a plurality of multiplexers 722.0, 722.1 and 724.0 may serve as an embodiment of the clock tree group G2 shown in FIG. 5B.

The circuit structure and operation described above with reference to FIG. 7 are not intended to limit the scope of the present disclosure. For example, the channel selection circuit 720 may be implemented by the channel selection circuit 320 shown in FIG. 3 or the channel selection circuit 620 shown in FIG. 6 without departing from the scope of the present disclosure. For another example, the plurality of multiplexers 722.0, 722.1 and 724.0 in the channel selection circuit 720 can be arranged as shown in FIG. 8 . Referring to FIG. 8 , except for the channel selection circuit 820 , the structure of the integrated circuit 810 is similar/identical to the structure of the integrated circuit 710 shown in FIG. 7 . In this embodiment, the multiplexer 724.0 can couple one of the plurality of clock selection signals SEL ₇₀ and SEL ₇₁ to the output terminal T ₇₂ according to the clock selection signal SEL ₇₂ . The multiplexer 722.1 can couple the plurality of channels LA[0]˜LA[5] to the output terminal T ₇₁ according to the signal output by the multiplexer 724.0. Since those with ordinary knowledge in the art should be able to understand the operational details of the channel selection circuit 820 after reading the relevant paragraphs of FIG. 1 to FIG. 7 , further description of the channel selection will not be repeated here.

Please note that in order to facilitate channel selection, a clock selection signal used in the clock forwarding scheme provided by this disclosure can have a signal value/signal that matches a lane identifier of a clock channel to be selected. signal pattern. The channel selection circuit can select the current clock channel according to the clock selection signal. In some embodiments, the channel identification code may be a lane name of the selected clock channel, or a pin name of a signal pin located in the selected clock channel. ), or the pin number of the signal pin. For example, the channel identification code may be marked on a circuit board provided with an integrated circuit having the selected clock channel, or on a package that encapsulates the integrated circuit. For another example, the channel identification code can be marked or described in the datasheet, data book or device specification of the integrated circuit. In some embodiments, the channel identification code may be identification information carried by the selected clock channel. The integrated circuit can determine which channel should be selected as the clock channel by detecting the identification information.

See Figure 7 again. The integrated circuit 710 also includes a control circuit 750 that can be used to generate a plurality of clock selection signals SEL ₇₀ -SEL ₇₂ to control the channel selection circuit 720 . When the clock selection signal SEL ₇₀ /SEL ₇₁ has a signal value matching the channel identification code of one of the plurality of channels LA[0]˜LA[5], the channel selection circuit 720 can select the clock selection signal SEL ₇₀ / SEL ₇₁ selects the channel among multiple channels LA[0]~LA[5]. In this embodiment, the channel identification codes of each of the plurality of channels LA[0]～LA[5] may include a numeric symbol, and the respective channel identification codes of the plurality of channels LA[0]～LA[5] The plurality of digit symbols contained in the identification code indicates a group of consecutive numbers. For example (but this disclosure is not limited thereto), a pin name corresponding to a channel can be used as a channel identification code of the channel. The pair of signal pins of channel LA[0] can be named "dp0" and "dn0", the pair of signal pins of channel LA[1] can be named "dp1" and "dn1", and so on. The respective numerical symbols (that is, "0" to "5") of the plurality of pin names dp0 to dp5 can indicate a group of consecutive numbers (0 to 5).

In this embodiment, the control circuit 750 can generate a plurality of clock selection signals SEL ₇₀ -SEL ₇₂ in response to a control input IN _CT7 , where the control input IN _CT7 can indicate information about a channel identification code of the selected clock channel. The control input IN _CT7 may include (but is not limited to) a mode selection signal mss, a channel selection signal cks0 and a channel selection signal cks1. The mode selection signal mss can indicate the mode of the integrated circuit 710 . For example, the mode selection signal mss may include one bit to indicate whether the integrated circuit 710 operates in the "1C" mode or the "2C" mode. Integrated circuit 710 operates in "1C" mode to receive a single clock signal via multi-channel interface 314 . The integrated circuit 710 operates in the “2C” mode to receive two clock signals via the multi-channel interface 314 .

The channel selection signal cks0 may include (but is not limited to) three bits, and may indicate a channel identification of a selected clock channel (ie, one of the plurality of channels LA[0]~LA[5]) code. The channel select signal cks0 may have a bit pattern or signal value that matches the channel identification code of the selected clock channel. For example, a channel select signal cks0 with bit pattern "000" (corresponding to signal value "0") may indicate that channel LA[0] is selected as the clock channel. As another example, the channel selection signal cks0 with bit pattern "011" (corresponding to signal value "3") may indicate that channel LA[3] is selected as the clock channel.

The channel selection signal cks1 may include (but is not limited to) three bits, and may indicate a channel identification of a selected clock channel (ie, one of the plurality of channels LA[0]~LA[5]) code. The channel select signal cks1 may have a bit pattern or signal value that matches the channel identification code of the selected clock channel. When the integrated circuit 710 operates in the "2C" mode to receive two clock signals via the selected two clock channels, the channel selection signal cks0 may indicate a channel identification of one of the selected clock channels. The channel selection signal cks1 may indicate a channel identification code of another one of the selected clock channels. For example, when multiple channel selection signals cks0 and cks1 have bit patterns "000" and "011" respectively in "2C" mode, the control input IN _CT7 can indicate channel LA[0] and channel LA[3] Both are selected as clock channels to receive corresponding clock signals respectively.

In operation, when the integrated circuit 710 operates in a mode (such as the "1C" mode) to receive a single clock signal CKA via the multi-channel interface 314, the control circuit 750 may generate the clock selection signal SEL in response to the control input IN _{CT7 72} . The clock selection signal SEL ₇₂ can have a first signal value, so that the signal on the output terminal T ₇₀ can be distributed to each sampling circuit. For example, the control circuit 750 can generate the clock selection signal SEL ₇₂ according to the mode selection signal mss. For another example, the control circuit 750 may use the mode selection signal mss as the clock selection signal SEL ₇₂ . It is worth noting that in some embodiments, the mode selection signal mss in the control input IN _CT7 can be directly input to the multiplexer 724.0 to serve as the clock selection signal SEL ₇₂ .

In addition, the control circuit 750 can generate the clock selection signal SEL ₇₀ according to the channel identification code of the channel to which the clock signal CKA is input. In this embodiment, the control circuit 750 can generate the clock selection signal SEL ₇₀ according to the channel selection signal cks0, where the channel selection signal cks0 can indicate the channel identification code of the channel to which the clock signal CKA is input. For example, when the channel selection signal cks0 indicates that the channel LA[0] is set as a clock channel to receive the clock signal CKA, the control circuit 750 can generate a clock signal with a signal value of "0" according to the channel selection signal cks0. The pulse selection signal SEL ₇₀ matches the digital symbol "0" of the pin name dp0/dn0 (that is, the channel identification code of channel LA[0]). For another example, when the channel selection signal cks0 indicates that the channel LA[3] is set as a clock channel to receive the clock signal CKA, the control circuit 750 can generate a clock with a signal value of "3" according to the channel selection signal cks0 Select the signal SEL ₇₀ , which matches the numeric symbol "3" in the pin name dp3/dn3. It is worth noting that in some embodiments, since the channel selection signal cks0 may have a channel identification code matching the selected clock channel, the control circuit 750 may use the channel selection signal cks0 as the clock selection signal SEL ₇₀ .

When the integrated circuit 710 operates in another mode (such as the "2C" mode) to receive two clock signals CKB and CKC through the multi-channel interface 314, the control circuit 750 can generate the clock selection signal SEL in response to the control input IN _{CT7 72} . The clock selection signal SEL ₇₂ may have a second signal value that is different from the first signal value. Therefore, the signal on the output terminal T ₇₀ can be allocated to a plurality of sampling circuits RX[0]～RX[2], and the signal on the output terminal T ₇₁ can be allocated to a plurality of sampling circuits RX[3]～RX[5] . For example, the control circuit 750 can generate the clock selection signal SEL ₇₂ according to the mode selection signal mss, or use the mode selection signal mss as the clock selection signal SEL ₇₂ . It is worth noting that in some embodiments, the mode selection signal mss in the control input IN _CT7 can be directly input to the multiplexer 724.0 to serve as the clock selection signal SEL ₇₂ .

In addition, the control circuit 750 can generate the clock selection signal SEL ₇₀ according to the channel identification code of the channel to which the clock signal CKB is input, and generate the clock selection signal SEL ₇₁ according to the channel identification code of the channel to which the clock signal CKC is input. In this embodiment, the control circuit 750 can generate a plurality of clock selection signals SEL ₇₀ and SEL ₇₁ according to a plurality of channel selection signals cks0 and cks1 respectively in another mode (such as the "2C" mode). For example, when a plurality of channel selection signals cks0 and cks1 can indicate that a plurality of channels LA[0] and LA[3] are set as clock channels to receive a plurality of clock signals CKA and CKC respectively, the control circuit 750 can according to The channel selection signal cks0 generates a clock selection signal SEL ₇₀ with a signal value of "0", and a clock selection signal SEL ₇₁ with a signal value of "3" is generated according to the channel selection signal cks1. It is worth noting that in some embodiments, since the plurality of channel selection signals cks0 and cks1 can each have a channel identification code matching the selected clock channel, the control circuit 750 can convert the plurality of channel selection signals cks0 and cks1 respectively as a plurality of clock selection signals SEL ₇₀ and SEL ₇₁ .

In some embodiments, the transmitting side may send a preamble signal to a channel on the receiving side before sending a clock signal to the channel. By detecting the presence of the pilot signal, the receiving side can determine whether the clock signal will arrive at the channel. When a preamble signal appearing on one of the predetermined channels on the receiving side is detected, the receiving side may operate in a bifurcated mode to support multi-clock transmission. For example, in the embodiment shown in FIG. 7 , the control circuit 750 may include a state machine 755 to automatically select the mode of the integrated circuit 710 .

FIG. 9 is a schematic diagram of the operation of the state machine 755 shown in FIG. 7 according to certain embodiments of the present disclosure. Please refer to Figure 9 in conjunction with Figure 7. When the physical layer of integrated circuit 710 is enabled, state machine 755 may stay in state ST0 (eg, initial state). In the state ST0, the clock selection signal SEL ₇₂ can have the first signal value, so that the signal on the selected clock channel can be distributed to each sampling circuit through the output terminal T ₇₂ . After a period of time T_wait, the state machine 755 can enter the state ST1, so that the control circuit 750 can be used to detect whether the multi-channel interface 314 receives a preamble signal. When the preamble signal is detected on one of the predetermined channels of the multi-channel interface 314 (ie, another selected clock channel), the state machine 755 may enter state ST2, and the clock select signal SEL ₇₂ may have the The second signal value enables the integrated circuit 710 to operate in the bifurcation mode. After the predetermined channel is deactivated, state machine 755 may return to state ST0. The signal value of the clock selection signal SEL ₇₂ may be set to the first signal value.

In some embodiments, the predetermined channel may be the channel indicated by the channel selection signal cks1. By detecting whether a preamble signal is input to the channel indicated by the channel select signal cks1, the control circuit 750 can determine the signal value of the clock select signal SEL ₇₂ . In some embodiments, in addition to the channel indicated by the channel selection signal cks1, the control circuit 750 can also be used to detect whether any channel receives a preamble signal. Each channel detected by the control circuit 750 may correspond to the predetermined channel detected in state ST1.

The automatic channel detection operation described above is for illustrative purposes only and is not intended to limit the scope of the present disclosure. Referring again to FIG. 7 , in some embodiments, the control circuit 750 shown in FIG. 7 can be used to detect whether more than one pilot signal arrives at the multi-channel interface 314 . When more than one preamble signal is detected arriving at the multi-channel interface 314, the control circuit 750 may operate in a bifurcation mode to support multi-clock transmission. For example, the control circuit 750 can be coupled to the multi-channel interface 314, and can generate the clock selection signal SEL ₇₂ having the first signal value when detecting a single preamble signal on a channel. When multiple pilot signals on two channels are detected, the control circuit 750 can generate the clock selection signal SEL ₇₂ with the second signal value, so that the integrated circuit 710 operates in the bifurcated mode.

In addition, the above-mentioned implementation of channel selection using the matching relationship between the channel identification code and the control input is only for illustrative purposes and is not intended to limit the scope of the present disclosure. In some embodiments, the control circuit 750 may include a decoder (not shown in FIG. 7 ). The decoder can decode a channel select signal to generate a clock select signal for a clock channel to be selected, wherein the channel select signal has a signal value/signal pattern that matches a channel identification code of the clock channel. Like. Therefore, the control circuit 750 can correctly select the clock channel according to the matching relationship between the channel identification code of the clock channel and the channel selection signal of the control input IN _CT7 .

Please note that the signal value of a channel selection signal (or the signal value of a clock selection signal) can directly or indirectly correspond/match (map) to the channel ID of a clock channel to be selected. For example, when the clock signal CKA/CKB is input to channel LA[0], the channel selection signal cks0 can have the bit pattern "000001", which corresponds to the digital symbol "0" corresponding to the pin name dp0/dn0. Matching signal value "2 ⁰ ". Additionally, alternatively, the control circuit 750 may generate the clock selection signal SEL ₇₀ having a bit pattern "000001", wherein the bit pattern "000001" corresponds to the digital symbol "0" corresponding to the pin name dp0/dn0 Matching signal value "2 ⁰ ". For another example, when the clock signal CKC is input to channel LA[3], the channel selection signal cks1 can have the bit pattern "001000", which corresponds to the signal matching the digital symbol "3" of the pin name dp3/dn3 The value is "2 ³ ". Additionally, alternatively, the control circuit 750 may generate the clock selection signal SEL ₇₁ having a bit pattern "001000", wherein the bit pattern "001000" corresponds to the digital symbol "3" of the pin name dp3/dn3. Matching signal value "2 ³ ".

In some embodiments, other types of channel identifiers (such as channel names, pin numbers, or identification information carried by the channel) may be matched to the signal value of the channel select signal. In some embodiments, the control circuit 750 may determine the signal value of the clock selection signal based on other types of channel identification codes (such as channel names, pin numbers, or identification information carried by the channels). In some embodiments, the numeric symbols of the channel identification code may be in the form of Arabic numerals, Roman numerals, letters, or other types of numeric symbols. In some embodiments, the set of consecutive numbers indicated by the respective numeric symbols of the plurality of channel identification codes may be a plurality of consecutive odd numbers, a plurality of consecutive even numbers, or a plurality of numbers in a predetermined consecutive order. For example, according to certain embodiments of the present disclosure, some embodiments of the channel identification codes of the plurality of channels LA[0]˜LA[5] shown in FIG. 7 are shown in FIG. 10 . These design modifications and changes all follow the spirit of this disclosure and fall within the scope of this disclosure.

The above-mentioned channel selection operation can be applied to the integrated circuit 110 shown in FIG. 1, the integrated circuit 310 shown in FIG. 3, the plurality of integrated circuits 510A˜510C shown in FIGS. The integrated circuit 610 shown in FIG. 8 and the integrated circuit 810 shown in FIG. 8 . For example, see Figure 3 again. The integrated circuit 310 also includes a control circuit 350 that can generate a plurality of clock selection signals SEL ₀₀ , SEL ₀₁ and SEL ₁₀ ˜SEL ₁₅ in response to a control input IN _CT3 to control the channel selection circuit 320 .

Control input IN _CT3 can indicate the channel identification code information of the selected clock channel. For example. The control input IN _CT3 may include a plurality of channel selection signals, and each channel selection signal may indicate the channel identification code information of a selected clock channel. The control circuit 350 can generate the clock selection signal SEL ₀₀ according to one channel selection signal, and generate the clock selection signal SEL ₀₁ according to another channel selection signal. For another example, the control input IN _CT3 may further include a mode selection signal, which may indicate the mode of the integrated circuit 310 . The control circuit 350 can generate a plurality of clock selection signals SEL ₁₀ -SEL ₁₅ according to the mode selection signal.

In the "5D1C" channel configuration, a plurality of clock selection signals SEL ₁₀ ~ SEL ₁₅ can have the same signal value, so that one of the plurality of output sides S02 and S12 can be coupled to each sampling circuit. When the clock signal 5D_CLK is input to one of the plurality of channels LA[0]～LA[2], the plurality of clock selection signals SEL ₁₀ ～SEL ₁₅ can have a first signal value, so that the output side S02 can be coupled in each sampling circuit. The control circuit 350 may generate the clock selection signal SEL ₀₀ according to a channel selection signal in the control input IN _CT3 , wherein the channel selection signal has a signal value matching the channel identification code of the channel. Additionally, or alternatively, the clock select signal SEL ₀₀ may have a signal value that matches the channel identification code of the channel. When the clock signal 5D_CLK is input to one of the plurality of channels LA[3]-LA[5], the plurality of clock selection signals SEL ₁₀ -SEL ₁₅ can have a second signal value, so that the output side S12 can be coupled in each sampling circuit. The control circuit 350 may generate the clock selection signal SEL ₀₁ according to another channel selection signal in the control input IN _CT3 , wherein the other channel selection signal has a signal value matching the channel identification code of the channel. Additionally, or alternatively, the clock select signal SEL ₀₁ may have a signal value that matches the channel identification code of the channel.

In the "2D1C" bifurcated channel configuration, each of the plurality of clock selection signals SEL ₁₀ ~ SEL ₁₂ can have a signal value, wherein the signal value is different from the plurality of clock selection signals SEL ₁₃ ~The signal value of each clock selection signal in SEL ₁₅ . Therefore, the output side S02 can be coupled to a plurality of sampling circuits RX[0]˜RX[2], and the output side S12 can be coupled to a plurality of sampling circuits RX[3]˜RX[5]. Since the clock signal 2D_CLK0 is input to one of the plurality of channels LA[0]˜LA[2], the control circuit 350 can generate the clock selection signal SEL ₀₀ according to a channel selection signal in the control input IN _CT3 , where The channel select signal has a signal value that matches the channel ID of the channel. Additionally, or alternatively, the clock select signal SEL ₀₀ may have a signal value that matches the channel identification code of the channel. Similarly, since the clock signal 2D_CLK0 is input to one of the plurality of channels LA[3]˜LA[5], the control circuit 350 can generate a clock selection signal according to another channel selection signal in the control input IN _CT3 SEL ₀₁ , wherein the other channel selection signal has a signal value that matches the channel identification code of the channel. Additionally, or alternatively, the clock select signal SEL ₀₁ may have a signal value that matches the channel identification code of the channel.

In some embodiments, the clock select signal SEL ₀₀ and the clock select signal SEL ₀₁ may be implemented as a single clock select signal. Multiple channel selection units 322.0 and 322.1 can perform channel selection operations according to the single clock selection signal. The control circuit 350 can determine the signal value/signal pattern of the single clock selection signal according to one or more channel identification codes of one or more channels to be selected. For example, in the "5D1C" channel configuration, the single clock signal has a signal value that matches the channel ID of the channel where the clock signal 5D_CLK is input. For another example, in the "2D1C" bifurcated channel configuration, the first three least significant bits (LSB) of the single clock signal have a signal value that is consistent with the plurality of channels LA[0]~LA Matches one of the channel identifiers in [2]. The first three most significant bits (MSB) of the single clock signal have a signal value that matches the channel identification code of one of the plurality of channels LA[3]˜LA[5].

Similarly, please refer to FIG. 1 again. The integrated circuit 110 further includes a control circuit 150, which can generate a clock selection signal according to a control input IN _CT1 , or according to a selected signal of a plurality of clock channels. The channel identification code generates the clock selection signal. Control input IN _CT1 indicates the channel identification code. Additionally, or alternatively, the clock selection signal may have a signal value that matches the channel identification code. Therefore, the channel selection circuit 120 can select the channel according to the clock selection signal. In addition, alternatively, in the embodiments shown in FIG. 5A, FIG. 5B, FIG. 5C and FIG. 6, the signal value of the clock selection signal SEL _A /SEL _B1 /SEL _B2 /SEL _C1 /SEL _C2 /SEL _C3 can be based on Determined by the channel identification code of the clock signal input channel. Since those with ordinary knowledge in the art should understand that the clock selection signal SEL _A / Details of SEL _B1 /SEL _B2 /SEL _C1 /SEL _C2 /SEL _C3 , therefore, further explanation will not be repeated here.

At least one of the above-mentioned channel exchange scheme and channel selection operation can be applied to other sub-layers of the physical layer, such as the physical coding sub-layer. FIG. 11 illustrates a functional block diagram of an exemplary receiver according to certain embodiments of the present disclosure. Receiver 1104 may be an embodiment of receiver 104 shown in FIG. 1 . The physical layer 1108 of the receiver 1104 includes a physical media connection layer (PMA) 1105 and a physical coding sublayer (PCS) 1107. The physical media connection layer 1105 may adopt the circuit structure and operation described with reference to FIGS. 1 to 10 .

The physical media connection layer 1105 includes (but is not limited to) a multi-channel interface 1114, a channel selection circuit 1120 and a plurality of S2P converters 1130 ₀ to 1130 _N-1 , where N is an integer greater than 1. The multi-channel interface 1114 and the channel selection circuit 1120 can be respectively used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 . The multi-channel interface 114 may include N channels LA[0]˜LA[N-1] as shown in FIG. 1 . The channel selection circuit 1120 is used to select one or more channels in the multi-channel interface 1114 as one or more clock channels according to a set of clock selection signals {SEL _PMA }. In addition, a plurality of S2P converters 1130 ₀ to 1130 _N-1 can be implemented using N sampling circuits RX[0] to RX[N-1] and the output circuit 140 shown in FIG. 1 .

The physical coding sublayer 1107 includes (but is not limited to) a multi-channel interface 1116, a channel selection circuit 1122 and a plurality of processing circuits 1132 ₀ to 1132 _N-1 . The multi-channel interface 1116 may be an embodiment of the multi-channel interface 114 shown in FIG. 1 . The multi-channel interface 1116 includes N channels LS[0]˜LS[N-1] coupled to the physical media connection layer 1105 . The channel selection circuit 1122 can be used as an embodiment of the channel selection circuit 120 shown in FIG. 1 . The channel selection circuit 1122 is used to select one or more channels among the N channels LS[0]˜LS[N-1] as one or more clock channels according to a set of clock selection signals {SEL _PCS }. Each channel among the N channels LS[0]~LS[N-1] can be used commonly for clock channels and data channels. In addition, the plurality of processing circuits 1132 ₀ to 1132 _N-1 may be implemented to respectively include N sampling circuits RX[0] to RX[N-1] as shown in FIG. Multiple clock signals are used for data sampling.

In operation, the physical media connection layer 1105 may be used to output M clock signals CKD ₁ -CKD _M respectively related to M different clock domains (clock domains), where M is a positive integer less than N. The physical coding sublayer 1107 can select M channels among the N channels LS[0]˜LS[N-1] as M clock channels to receive M clock signals CKD ₁ ˜CKD _M . That is to say, the physical coding sub-layer 1107 can perform corresponding channel selection operations in response to the channel selection operations of the physical media connection layer 1105. For example, the multi-channel interface 1114 of the physical media connection layer 1105 can receive M clock signals transmitted by M transmitters (not shown in Figure 11) to generate M clock signals CKD ₁ to CKD _M , where the The M transmitters respectively operate in the M different clock domains. The channel selection circuit 1120 can select the M channels in the multi-channel interface 1114 as M clock channels according to a set of clock selection signals {SEL _PMA }. M S2P converters (coupled to the selected M channels) among the plurality of S2P converters 1130 ₀ to 1130 _N-1 can respectively generate M clock signals CKD ₁ to CKD _M . In response to the channel selection operation of the physical media connection layer 1105, the channel selection circuit 1122 in the physical encoding sublayer 1107 can select N channels LS[0]～LS[N-1] according to a set of clock selection signals {SEL _PCS }. The M channels in are selected as M clock channels. One or more channels included in the remaining (NM) channels among the N channels LS[0]~LS[N-1] can be used as one or more data channels. A plurality of processing circuits 1132 ₀ to 1132 _N-1 can process data on one or more data channels according to M clock signals CKD ₁ to CKD _M.

A set of clock selection signals {SEL _PMA } and a set of clock selection signals {SEL _PCS } may be generated by a control input shared by the physical media connection layer 1105 and the physical coding sublayer 1107 . In this embodiment, the physical encoding sublayer 1107 may also include a control circuit 1150, which may be an embodiment of the control circuit 150 shown in FIG. 1 . The control circuit 1150 can generate a set of clock selection signals {SEL _PMA } and a set of clock selection signals {SEL _PCS } according to a control input IN _CTRL . The control input IN _CTRL may indicate the channel identification code of the clock channel selected in the physical media connection layer 1105 and the channel identification code of the clock channel selected in the physical encoding sublayer 1107 . For example, when the control input IN _CTRL has a signal pattern/signal value that matches the channel identification code of the channel LA[0] of the physical media connection layer 1105, the control circuit 1150 may generate a set of clocks according to the control input IN _CTRL . Select the signal {SEL _PMA } so that channel LA[0] can be set as a clock channel to receive the clock signal sent by the transmitter (not shown in Figure 11). In addition, the control circuit 1150 can generate a set of clock selection signals {SEL _PCS } according to the control input IN _CTRL , so that the channel LS[0] (having a channel identification code matching the signal pattern/signal value of the control input IN _CTRL ) can It is configured as a clock channel to receive the clock signal output by the physical media connection layer 1105, where the clock signal output by the physical media connection layer 1105 is generated in response to the clock signal transmitted by the transmitter.

For example (but this disclosure is not limited thereto), the control input IN _CTRL may include a plurality of channel selection signals, wherein each channel selection signal may indicate the channel identification code of a selected clock channel. As another example, the control input IN _CTRL may be a mode selection signal and a plurality of channel selection signals, wherein the mode selection signal may indicate the mode of the receiver 1104, such as "1C" mode or bifurcated mode. After reading the paragraphs related to Figures 1 to 10, a person with ordinary knowledge in the art should understand that the control circuit 1150 can use the matching relationship between the channel identification code and the control input to control the channel selection circuit 1120 and the channel selection circuit 1122, therefore, the repeated instructions on channel selection will not be described again here.

In some embodiments, the common control circuit 1150 may be disposed in the physical media connection layer 1105 instead of the physical encoding sublayer 1107 . In some embodiments, the physical media connection layer 1105 may have a first control circuit disposed therein, and the physical encoding sublayer 1107 may have a second control circuit disposed therein. The first control circuit and the second control circuit may control channel selection operations based on the same control input, such as control input IN _CTRL . These design modifications and changes all follow the spirit of this disclosure and fall within the scope of this disclosure.

Some examples are provided below to further illustrate the physical coding sublayer 1107 using the channel interchange scheme. Those with ordinary knowledge in the art should understand that other entity encoding sub-layers that adopt the channel interchange scheme described with reference to FIGS. 1 to 10 follow the spirit of this disclosure and fall within the scope of this disclosure.

FIG. 12 is a schematic diagram of an embodiment of an integrated circuit in the physical encoding sub-layer 1107 shown in FIG. 11 according to certain embodiments of the present disclosure. The integrated circuit 1210 in the physical coding sub-layer 1207 can be used as an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6). In this embodiment, the physical coding sublayer 1207 is used to receive the clock and data information transmitted by the physical media connection layer (PMA) 1205, where the physical media connection layer 1205 can be used as a component of the physical media connection layer 1105 shown in Figure 11. Example. The integrated circuit 1210 may include a multi-channel interface 1214, a channel selection circuit 1220 and a plurality of sampling circuits RM[0]˜RM[5]. The multi-channel interface 1214 and the channel selection circuit 1220 can be respectively used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 . The plurality of sampling circuits RM[0]˜RM[5] can be used as embodiments of the plurality of sampling circuits RX[0]˜RX[5] shown in FIG. 1 .

The multi-channel interface 1214 is coupled to the physical media connection layer 1205 and includes a plurality of channels LS[0]˜LS[5] as shown in FIG. 11 . The plurality of channels LS[0]~LS[5] can be used as an embodiment of the N channels LA[0]~LA[N-1] shown in Figure 1 (that is, N=6). In this embodiment, each of the plurality of channels LS[0]˜LS[5] can carry a multi-bit output signal, such as a byte data signal or a byte clock signal.

The channel selection circuit 1220 is used to select one or more channels among the plurality of channels LS[0]˜LS[5] as one or more clock channels. One or more of the remaining channels can serve as one or more data channels. The channel selection circuit 1220 includes (but is not limited to) a plurality of selection stages 1222 and 1224, which can be respectively used as embodiments of the plurality of selection stages 122 and 124 shown in FIG. 1 . In this embodiment, the selection stage 1222 may couple one or two channels to the selection stage 1224 according to the mode of the integrated circuit 1210 . The selection stage 1222 includes a plurality of channel selection units 1222.0 and 1222.1. The channel selection unit 1222.0 is used to couple a plurality of channels LS[0]˜LS[5] to an output terminal T ₁₀₀ according to a clock selection signal SEL ₁₀₀ . The channel selection unit 1222.1 is used to couple a plurality of channels LS[0]˜LS[5] to an output terminal T ₁₀₁ according to a clock selection signal SEL ₁₀₁ . The selection stage 1224 may be implemented to include a channel selection unit 1224.0, which may couple one of the output terminal T ₁₀₀ and the output terminal T ₁₀₁ to an output terminal T ₁₀₂ according to a clock selection signal SEL ₁₀₂ .

A plurality of sampling circuits RM[0]˜RM[5] are coupled to the multi-channel interface 1214 and the channel selection circuit 1220, and are used for sampling data according to the clock information and data information transmitted by the physical media connection layer 1205. In this embodiment, each of the plurality of sampling circuits RM[0]˜RM[5] may include a clock input terminal PC _IN and a data input terminal PD _IN . Each sampling circuit can use the signal input to the corresponding clock input terminal PC _IN to sample the signal input to the corresponding data input terminal PD _IN .

In the mode where the integrated circuit 1210 is used to support the "4D1C" channel configuration, the channel selection unit 1224.0 is used to couple the output terminal T ₁₀₀ to the output terminal T ₁₀₂ . When the channel selection unit 1222.0 selects one of the plurality of channels LS[0]~LS[5] as a clock channel, the signal on the clock channel can be coupled to the output terminal T ₁₀₀ and distributed to a plurality of The respective clock input terminals PC _IN of the sampling circuits RM[0]~RM[5]. For example, when a clock signal is input to channel LS[0], the channel selection unit 1222.0 can select channel LS[0] as the clock channel, and the plurality of sampling circuits RM[0]~RM[5] The four sampling circuits can sample data based on the same clock signal (ie, the signal on channel LS[0]).

In the mode where the integrated circuit 1210 is used to support the "2D1C" bifurcated channel configuration, the channel selection unit 1224.0 is used to couple the output terminal T ₁₀₁ to the output terminal T ₁₀₂ . When the channel selection unit 1222.0 selects one of the plurality of channels LS[0]～LS[5] as a clock channel, the channel selection unit 1222.1 selects another one of the plurality of channels LS[0]～LS[5]. The channel is selected as a clock channel. Therefore, the signals on the remaining plurality of clock channels can be sampled according to the signals on the selected plurality of clock channels. For example, when two clock signals are input to channel LS[1] and channel LS[4] respectively, the channel selection unit 1222.0 can select channel LS[1] as a clock channel, and the channel selection unit 1222.1 can select channel LS [4] Select another clock channel. Four sampling circuits among the plurality of sampling circuits RM[0]~RM[5] can perform data sampling according to the two clock signals involving different clock domains.

It is worth noting that the physical coding sub-layer 1207 can adopt the channel selection operation described above. In this embodiment, the integrated circuit 1210 further includes a control circuit 1250 that can generate a plurality of clock selection signals SEL ₁₀₀ ˜SEL ₁₀₂ according to a control input IN _CT12 to control the channel selection circuit 1220 . For example, when a clock signal transmitted by the physical media connection layer 1205 is input to one of the plurality of channels LS[0]˜LS[5] in the “4D1C” channel configuration, the control circuit 1250 can control The input IN _CT12 generates a clock selection signal SEL ₁₀₀ , which indicates the channel identification code of the channel. For another example, when two clock signals are input to two of the plurality of channels LS[0]～LS[5] in the "2D1C" bifurcated channel configuration, the control circuit 1250 can generate according to the control input IN _CT12 The clock selection signal SEL ₁₀₀ can indicate the channel identification code of one of the two channels. In addition, the control circuit 1250 can generate the clock selection signal SEL ₁₀₁ according to the control input IN _CT12 , which can indicate the channel identification code of the other one of the two channels.

The channel selection operation described above can be applied to the data channel selection operation. For example, the channel selection circuit 1220 also includes a plurality of channel selection units 1232.0-1232.3, which can be controlled by a plurality of data selection signals SEL ₁₁₀ -SEL ₁₁₃ generated by the control circuit 1250. In this embodiment, the plurality of channel selection units 1232.0˜1232.3 can provide the data transmitted by the physical media connection layer 1205 to the plurality of sampling circuits RM[0], RM[2], RM[3] and RM[5 respectively. ].

In the "4D1C" channel configuration mode (one of the plurality of channels LS[0]~LS[5] is selected as the clock channel), the control circuit 1250 can generate a plurality of data selection signals according to the control input IN _CT12 SEL ₁₁₀ ~ SEL ₁₁₃ , in which the control input IN _CT12 can indicate the channel identification codes of each of the four channels carrying the data signals transmitted by the physical media connection layer 1205. For example, the respective signal values of the plurality of data selection signals SEL ₁₁₀ ~ SEL ₁₁₃ can be respectively matched with the channel identification codes of the four channels.

In the "2D1C" channel configuration mode (two of the plurality of channels LS[0]~LS[5] are selected as clock channels), the control circuit 1250 can generate a plurality of data selection signals according to the control input IN _CT12 SEL ₁₁₀ and SEL ₁₁₁ , the control input IN _CT12 can indicate the channel identification codes of the two channels. The two channels can carry data signals related to the clock signal output by the channel selection unit 1222.0. For example, the respective signal values of the plurality of data selection signals SEL ₁₁₀ and SEL ₁₁₁ can be respectively matched with the respective channel identification codes of the two channels. In addition, the control circuit 1250 can generate a plurality of data selection signals SEL ₁₁₂ and SEL ₁₁₃ according to the respective channel identification codes of the other two channels, wherein the other two channels can carry data related to the clock signal output by the channel selection unit 1222.1 signal. For example, the signal values of the plurality of data selection signals SEL ₁₁₂ and SEL ₁₁₃ can respectively match the channel identification codes of the other two channels.

Since those with ordinary knowledge in the art should understand that the data channel selection operation used in the clock forwarding scheme can be similar/identical to the clock channel selection operation described with reference to Figures 1 to 11, therefore, repeated The explanation will not be repeated here.

In some embodiments, the control circuit 1250 may be shared by the physical media connection layer 1205 and the physical encoding sublayer 1207. For example, the control circuit 1250 may generate one or more clock selection signals to control the clock selection operation of the physical media connection layer 1205 . For another example, the control circuit 1250 can use one or more clock selection signals of the channel selection circuit 1220 to control the channel selection circuit (not shown in FIG. 12 ) of the physical media connection layer 1205, thereby causing the physical media connection layer 1205 to communicate with the physical encoding. The respective channel selection operations of the sub-layers 1207 are consistent with each other.

It is worth noting that the circuit structure and operation of the channel selection circuit 1220 shown in FIG. 12 are for illustration purposes only. In some embodiments, the channel selection circuit 1220 may utilize the channel selection circuit 120 shown in FIG. 1, the channel selection circuit 320 shown in FIG. 3, a plurality of channel selection circuits 520A˜520C shown in FIGS. 5A to 5C, The channel selection circuit 620 shown in FIG. 6, the channel selection circuit 720 shown in FIG. 7, the channel selection circuit 820 shown in FIG. 8, and the related design changes described above can be implemented without departing from the scope of the present disclosure.

For example, please refer to FIG. 13 , which illustrates a schematic diagram of another embodiment of an integrated circuit in the physical encoding sub-layer 1107 shown in FIG. 11 according to certain embodiments of the present disclosure. Except for the channel selection circuit 1320, the structure of the integrated circuit 1310 of the physical encoding sublayer 1307 may be similar/identical to the structure of the integrated circuit 1210 shown in FIG. 12 . In this embodiment, the selection stage 1322 in the channel selection circuit 1320 includes a channel selection unit 1322.a, a channel selection unit 1322.b and the channel selection unit 1222.1 shown in FIG. 12 . The channel selection unit 1322.a can couple a plurality of channels LS[0]˜LS[5] to an output terminal T _13A according to the clock selection signal SEL ₁₀₀ , wherein the output terminal T _13A is coupled to a plurality of sampling circuits RM[ 0]~RM[2] respective clock input terminal PC _IN . The channel selection unit 1322.b can couple a plurality of channels LS[0]˜LS[5] to an output terminal T _13B according to the clock selection signal SEL ₁₀₀ , where the output terminal T _13B is coupled to the channel selection unit 1224.0. Since a person with ordinary knowledge in the art should be able to understand the operational details of the channel selection circuit 1320 after reading the relevant paragraphs of FIG. 1 to FIG. 12 , further description will not be repeated here.

In addition, the channel selection scheme described above can also be applied to the transmission side. FIG. 14 illustrates a functional block diagram of an exemplary multi-channel communication system according to certain embodiments of the present disclosure. Multi-channel communication system 1400 may include a transmitter 1402 and a receiver 1404. The transmitter 1402 may be an embodiment of one of the K transmitters TX[0]˜TX[K-1] shown in FIG. 1 . The receiver 1404 may adopt the circuit structure and operation described with reference to FIGS. 1-13. In this embodiment, the transmitter 1402 can cause the signals transmitted on the clock channel and the data channel to be interchanged with each other. The transmitter 1402 includes (but is not limited to) a plurality of signal generation circuits 1410.0-1410.2, a channel selection circuit 1420, and a plurality of parallel-to-serial converters (hereinafter referred to as "P2S converters") 1430.0 ~1430.2, a multi-channel interface 1440 and a control circuit 1450.

Each of the plurality of signal generating circuits 1410.0-1410.2 can generate a multi-bit output signal on a data bus, such as a parallel clock signal or a parallel data signal. In this embodiment, the signal generating circuit 1410.0 and the signal generating circuit 1410.1 can both be implemented by a data signal generator, and the signal generating circuit 1410.2 can be implemented by a clock signal generator. Therefore, the plurality of signal generating circuits 1410.0 and 1410.1 can generate a plurality of parallel data signals PD0 and PD1 on the plurality of data buses DB0 and DB1 respectively. The signal generating circuit 1410.2 can generate a parallel clock signal PC0 on the data bus DB2.

The channel selection circuit 1420 is coupled to the plurality of signal generating circuits 1410.0˜1410.2, and is used to distribute the plurality of multi-bit output signals generated by the plurality of signal generating circuits 1410.0˜1410.2 to the plurality of P2S converters 1430.0˜1430.2. In this embodiment, the channel selection circuit 1420 includes a plurality of channel selection units 1422.0˜1422.2, where each channel selection unit can select according to a corresponding selection signal (ie, one of the plurality of selection signals SEL _T0 ˜SEL _T2 ). To output one of the plurality of output signals on the plurality of data buses DB0~DB2.

Each P2S converter among the plurality of P2S converters 1430.0˜1430.2 can convert a parallel output signal into a serial output signal. The multi-channel interface 1440 can be an embodiment of one of the K multi-channel interfaces TF[0]˜TF[K-1] shown in FIG. 1 . The multi-channel interface 1440 may include a plurality of channels LT[0]˜LT[2]. At least one channel among the plurality of channels LT[0]~LT[2] can be used commonly for the clock channel and the data channel. In this embodiment, each of the plurality of channels LT[0]˜LT[2] can be implemented using a two-wire channel, which is a differential channel including a pair of signal pins. The pair of signal pins included in channel LT[0] can be named "dpt0" and "dnt0", and the pair of signal pins included in channel LT[1] can be named "dpt1" and "dnt1". Analogy. In some embodiments, each of the plurality of channels LT[0]˜LT[2] may be implemented using other types of channels, such as single-wire channels or channels with more than two wires, without departing from the teachings of the present disclosure. Scope.

The control circuit 1450 is used to generate a plurality of selection signals SEL _T0 ˜SEL _T2 according to a control input IN _CT14 to thereby control the channel selection circuit 1420 . The signal value of each of the plurality of selection signals SEL _T0 ~ SEL _T2 can be determined according to the control input IN _CT14 , where the control input IN _CT14 can indicate the channel identification code corresponding to a channel. For example, the receiver 1404 can use the channel 1406.0 as a clock channel to receive the clock information transmitted by the transmitter 1402. Both channel 1406.1 and channel 1406.2 can be used as data channels of the receiver 1404. By coupling the signal generation circuit 1410.2 to the P2S converter 1430.0, the channel selection unit 1422.0 can select the channel LT[0] (which is coupled to the channel 1406.0) as a clock channel according to the selection signal SEL _T0 . The control circuit 1450 may determine the signal value of the selection signal SEL _T0 according to the channel identification code of the channel LT[0] (such as the pin name "dpt0/dnt0" or the channel name "LT[0]"). In addition, the channel selection unit 1422.1 can select the channel LT[1] as a data channel according to the selection signal SEL _T1 , and the channel selection unit 1422.2 can select the channel LT[2] as a data channel according to the selection signal SEL _T2 . Since a person with ordinary knowledge in the art should be able to understand the details of the clock/data channel selection operation of the channel selection circuit 1420 after reading the above description of the clock/data channel selection operation on the receiving side, further explanation is provided. I won’t go into details here.

The circuit structure described above is for illustrative purposes only and is not intended to limit the scope of the present disclosure. In some embodiments, the number of channels of the above-mentioned multi-channel interface can be changed according to different design requirements and applications. For example, the multi-channel interface may include four channels, eight channels, or other channel numbers according to different embodiments. In some embodiments, one or more of the above-mentioned channel selection units may be implemented using one or more multiplexers, or other circuits with signal path selection capabilities. In some embodiments, one or more of the multiplexers described above may be implemented based on inverters, OR-logic gates, other circuits with signal path selection capabilities, or combinations thereof.

By using at least one channel that is common to both the clock channel and the data channel, the physical layer on the receiving side can support different channel configurations on the transmitting side. For example, the physical layer can be divided into multiple physical interfaces to support multiple transmitters. In addition, a clock/data channel can be selected based on its channel identification code to facilitate clock/data channel selection.

The foregoing description briefly sets out features of certain embodiments of the present disclosure to enable those of ordinary skill in the art to more fully understand the various aspects of the present disclosure. It will be understood by those of ordinary skill in the art to which this disclosure belongs that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and/or achieve the same results as the embodiments described herein. advantages. Those of ordinary skill in the art to which this disclosure belongs should understand that these equivalent embodiments still belong to the spirit and scope of this disclosure, and that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure.

1D_CLK0~1D_CLK2,CKA,CKB,CKC,CKD ₁ ~CKD _M : Clock signal 5D ₀ ~5D ₄ , 2D 00, 2D ₀₁ , 2D ₁₀ , 2D ₁₁ : Data signal 100, ₁₄₀₀ : Multi-channel communication system 104, 300, 1104 , 1404: Receiver 106: Communication link 108, 1108: Physical layer 110, 310, 510A~510C, 610, 710, 810, 1210, 1310: Integrated circuit 114, 314, 1114, 1116, 1214, TF[0]~TF[N-1]: Multiple Channel interface 120, 320, 520A, 520B, 520C, 620, 720, 820: Channel selection circuit 1120, 1122, 1220, 1320, 1420: Channel selection circuit 122, 124, 322, 324, 622, 624, 722, 724, 1222, 1224, 1322: Selection stage 14 0,740,1440: Output circuit 150,350,750,1150,1250,1450 : Control circuit 322.0, 322.1, 324.0~324.5, 1222.0, 1222.1, 1224.0: Channel selection unit 1232.0~1232.3, 1322.a, 1322.b, 1422.0~1422.2: Channel selection unit 522A, 522B.0, 522B.1, 522C.0 ~522C.2: Multiplexer 722.0, 722.1, 724.0: Multiplexer 524A, 524B.0, 524B.1, 524C.0~524C.2, CT: Clock tree 730.0~730.5, 1130 ₀ ~1130 _N-1 : Serial to parallel converter 755: State machine 1105, 1205: Physical media connection layer 1107, 1207, 1307: Physical encoding sublayer 1132 ₀ ~ 1132 _N-1 : Processing circuit 1402, TX[0]~TX[N-1 ]: Transmitter 1406.0~1406.2, LA[0]~LA[N-1], L0[0]~L0[P]: Channel L1[0]~L1[Q], L2[0]~L2[R] ,LS[0]~LS[N-1],LT[0]~LT[2]: Channel 1410.0~1410.2: Signal generation circuit 1430.0~1430.2: Parallel to serial converter C0~C3,5D_CLK,2D_CLK0,2D_CLK1 : Clock signal C _IN , PC _IN : Clock input terminal CK ₀ ~CK _(M-1) : Signal cks0, cks1: Channel selection signal D0 ₀ ~D0 _(P-1) , D1 ₀ ~D1 _{(Q-1 )} ,D2 ₀ ~D2 _(R-1) : data signal DA ₀ ~DA _(NM-1) : signal DB0~DB2: data bus D _IN , PD _IN : data input terminal DP_a~DP_f,DN_a~DN_f,dpt0 ~dpt2,dnt0~dnt2: pin names dp0~dp5, dn0~dn5,DP_0~DP_5, DN_0~DN_5: pin names DS[0]~DS[5]: deserializer G1~G3: clock tree group Group IN _CT1 , IN _CT3 , IN _CT7 , IN _CT12 , IN _CT14 , IN _CTRL : control input mss: mode selection signal OP1~OP3: mode PC0: parallel clock signal PD0, PD1: parallel data signal RS: receiving side RX[ 0]~RX[N-1],RM[0]~RM[5]: Sampling circuit S1, S01, S11: Input side S2, S02, S12: Output side SEL ₀₀ , SEL ₀₁ , SEL ₁₀ ~SEL ₁₅ , SEL _A , SEL _B0 , SEL _B1 : Clock selection signal SEL ₁₁₀ ~ SEL ₁₁₃ : Data selection signal SEL _C0 ~ SEL _C2 , SEL ₇₀ ~ SEL ₇₂ , SEL ₁₀₀ ~ SEL ₁₀₂ : Clock selection signal SEL _T0 ~ SEL _T2 : Selection signal SR: sampling result ST0~ST2: state T_wait: a period of time T ₁₀₀ ~ T ₁₀₂ , T _13A , T _13B : output terminal T _5D , T _2D0 , T _2D1 , T _1D0 , T _1D1 , T _1D2 , T ₇₀ ~ T ₇₂ : Output terminal TS: Transmission side {SEL _PMA }, {SEL _PCS }: A set of clock selection signals

The various aspects of the present disclosure can be clearly understood by reading the following embodiments in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the art, various features in the drawings have not necessarily been drawn to scale. In fact, the dimensions of certain features may be arbitrarily exaggerated or reduced for clarity of description. FIG. 1 is a functional block diagram of an exemplary multi-channel communication system according to certain embodiments of the present disclosure. 2A to 2C are schematic diagrams of different modes of the receiver shown in FIG. 1 according to certain embodiments of the present disclosure. . FIG. 3 is a schematic diagram of a specific implementation of the integrated circuit shown in FIG. 1 according to certain embodiments of the present disclosure. 4A to 4C are operational schematic diagrams of the integrated circuit shown in FIG. 3 according to certain embodiments of the present disclosure. 5A to 5C are schematic diagrams of other specific implementations of the integrated circuit shown in FIG. 1 according to certain embodiments of the present disclosure. FIG. 6 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1 according to certain embodiments of the present disclosure. FIG. 7 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1 according to certain embodiments of the present disclosure. FIG. 8 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1 according to certain embodiments of the present disclosure. Figure 9 is a schematic diagram of the operation of the state machine shown in Figure 7 in accordance with certain embodiments of the present disclosure. FIG. 10 is a schematic diagram of a specific implementation of channel identification codes for the plurality of channels shown in FIG. 7 according to certain embodiments of the present disclosure. FIG. 11 is a functional block diagram of an exemplary receiver according to certain embodiments of the present disclosure. FIG. 12 is a schematic diagram of an embodiment of an integrated circuit in the physical coding sub-layer shown in FIG. 11 according to certain embodiments of the present disclosure. FIG. 13 is a schematic diagram of another embodiment of an integrated circuit in the physical coding sub-layer shown in FIG. 11 according to certain embodiments of the present disclosure. 14 is a functional block diagram of an exemplary multi-channel communication system according to certain embodiments of the present disclosure.

1400:Multi-channel communication system

1402:Transmitter

1404:Receiver

1406.0~1406.2,LT[0]~LT[2]: channel

1420: Channel selection circuit

1422.0~1422.2: Channel selection unit

1410.0~1410.2: Signal generation circuit

1430.0~1430.2: Parallel to serial converter

1440:Output circuit

1450:Control circuit

DB0~DB2: data bus

IN _CT14 : Control input

PC0: Parallel clock signal

PD0, PD1: parallel data signal

SEL _T0 ~SEL _T2 : Select signal

dpt0~dpt2,dnt0~dnt2: pin name

Claims (20)

An integrated circuit in a transmitter containing: A multi-channel interface with N channels, where N is an integer greater than 1; N signal generating circuits are coupled to the multi-channel interface, wherein M signal generating circuits among the N signal generating circuits are respectively used to generate M clock signals, and (N-M) of the N signal generating circuits The signal generation circuits are respectively used to generate (N-M) data signals, where M is a positive integer less than N; A control circuit for generating a set of selection signals according to a control input indicating respective channel identification codes of M channels among the N channels, wherein each of the M channels is coupled to a receiving A clock channel of the receiver, the clock channel of the receiver is used to receive one of the M clock signals; and A channel selection circuit is coupled between the multi-channel interface and the N signal generation circuits. The channel selection circuit is controlled by the set of selection signals to combine the M clock signals with the (N-M) data. Signals are distributed to the N channels, wherein the channel selection circuit is used to select the M channels as M clock channels by coupling the M clock signals to the M channels respectively, and the channel selects The circuit is further used to couple the (N-M) data signals to the remaining (N-M) channels respectively, and the remaining (N-M) channels serve as (N-M) data channels. The integrated circuit of claim 1, wherein the control input includes a channel selection signal, and the channel selection signal has a signal value matching a channel identification code of one of the M channels. The integrated circuit as described in claim 1, wherein the control input further indicates the channel identification code of each of the (N-M) channels, and the control input includes a channel selection signal, the channel selection signal has a value matching the (N-M) ) The signal value of the channel ID of one of the channels. The integrated circuit as described in claim 1, wherein the channel selection circuit includes: N channel selection units are respectively controlled by N selection signals in the group of selection signals. Each channel selection unit is coupled to the N signal generation circuits through N data buses and is used to generate signals according to the corresponding one. Select a signal to output one of the N output signals on the N data buses; the M output signals of the N output signals are the M clock signals, and the remaining (N-M) output signals The signals are the (N-M) data signals. The integrated circuit of claim 4, wherein each of the M clock signals and the (N-M) data signals is a multi-bit output signal; the integrated circuit further includes: N parallel-to-serial converters are respectively coupled to the N channel selection units, where each parallel-to-serial converter is used to convert an output signal output by a corresponding channel selection unit into a serial output signal, and output the serial output signal to a channel coupled to the parallel-to-serial converter among the N channels. The integrated circuit of claim 1, wherein each of the M clock signals and the (N-M) data signals is a multi-bit output signal; the integrated circuit further includes: N parallel-to-serial converters are coupled between the channel selection circuit and the multi-channel interface. The N parallel-to-serial converters are used to separate the M clock signals and the (N-M) data signals. Convert into N serial output signals, and output the N serial output signals to the N channels respectively. The integrated circuit as described in claim 1, wherein the channel identification codes of each of the N channels each include a numeric symbol, and the plurality of numeric symbols included in the channel identification codes of each of the N channels indicate a group of consecutive Numbers. The integrated circuit of claim 1, wherein the channel identification code of one of the M channels is the channel name of the channel of the M channels. The integrated circuit as described in claim 1, wherein the channel identification code of one of the M channels is the pin name or pin number of the signal pin included in the channel of the M channels. An integrated circuit in a transmitter containing: A multi-channel interface with N channels, where N is an integer greater than 1; N signal generating circuits are coupled to the multi-channel interface, wherein M signal generating circuits among the N signal generating circuits are respectively used to generate M clock signals, and (N-M) of the N signal generating circuits The signal generation circuits are respectively used to generate (N-M) data signals, where M is a positive integer less than N; A control circuit for generating a set of selection signals according to a control input indicating respective channel identification codes of M channels among the N channels, wherein each of the M channels is coupled to a receiving A clock channel of the receiver, the clock channel of the receiver is used to receive one of the M clock signals; and A channel selection circuit is coupled between the multi-channel interface and the N signal generation circuits. The channel selection circuit is controlled by the set of selection signals to combine the M clock signals with the (N-M) data. The signals are distributed to the N channels, wherein the channel selection circuit is used to select the M channels as M clock channels, and the remaining (N-M) channels are used as (N-M) data channels; in a mode, the N One of the channels is selected as a clock channel for outputting one of the M clock signals based on the set of selection signals; in another mode, the selected channel of the N channels A signal is selected based on the set as a data channel for outputting a data signal among the (N-M) data signals. The integrated circuit of claim 10, wherein the control input includes a channel selection signal having a signal value matching a channel identification code of one of the M channels. The integrated circuit of claim 10, wherein the control input further indicates the channel identification code of each of the (N-M) channels, and the control input includes a channel selection signal, the channel selection signal has a value matching the (N-M) ) The signal value of the channel ID of one of the channels. The integrated circuit as described in claim 10, wherein the channel selection circuit includes: N channel selection units are respectively controlled by N selection signals in the group of selection signals. Each channel selection unit is coupled to the N signal generation circuits through N data buses and is used to generate signals according to the corresponding one. Select a signal to output one of the N output signals on the N data buses; the M output signals among the N output signals are the M clock signals, and the remaining (N-M) outputs The signals are the (N-M) data signals. The integrated circuit of claim 13, wherein each of the M clock signals and the (N-M) data signals is a multi-bit output signal; the integrated circuit further includes: N parallel-to-serial converters are respectively coupled to the N channel selection units, where each parallel-to-serial converter is used to convert an output signal output by a corresponding channel selection unit into a serial output signal, and output the serial output signal to a channel coupled to the parallel-to-serial converter among the N channels. The integrated circuit of claim 10, wherein each of the M clock signals and the (N-M) data signals is a multi-bit output signal; the integrated circuit further includes: N parallel-to-serial converters are coupled between the channel selection circuit and the multi-channel interface. The N parallel-to-serial converters are used to separate the M clock signals and the (N-M) data signals. Convert into N serial output signals, and output the N serial output signals to the N channels respectively. The integrated circuit of claim 10, wherein the channel identification codes of each of the N channels each include a numeric symbol, and the plurality of numeric symbols included in the channel identification codes of each of the N channels indicate a group of consecutive Numbers. The integrated circuit of claim 10, wherein the channel identification code of one of the M channels is the channel name of the channel of the M channels. The integrated circuit of claim 10, wherein the channel identification code of one of the M channels is the pin name or pin number of the signal pin included in the channel of the M channels. An integrated circuit in a transmitter containing: A multi-channel interface with N channels, where N is an integer greater than 1; N signal generating circuits are coupled to the multi-channel interface, wherein M signal generating circuits among the N signal generating circuits are respectively used to generate M clock signals, and (N-M) of the N signal generating circuits The signal generation circuits are respectively used to generate (N-M) data signals, M is a positive integer less than N; and A channel selection circuit has an input side and an output side, the input side is coupled to the N signal generation circuits, the output side is coupled to the multi-channel interface, wherein when M channels among the N channels are coupled When connected to M clock channels included in a receiver for receiving the M clock signals, the channel selection circuit is used to couple the M clock signals received from the input side to The M channels located on the output side are used to select the M channels as the M clock channels of the transmitter. The channel selection circuit is also used to separately couple the (N-M) data signals received from the input side. Connected to the remaining (N-M) channels located on the output side, the remaining (N-M) channels serve as (N-M) data channels. The integrated circuit of claim 19, wherein each of the M clock signals and the (N-M) data signals is a multi-bit output signal; the integrated circuit further includes: N parallel-to-serial converters are coupled between the channel selection circuit and the multi-channel interface. The N parallel-to-serial converters are used to separate the M clock signals and the (N-M) data signals. Convert into N serial output signals, and output the N serial output signals to the N channels respectively.