JPS60107168A - Signal transmission and reception circuit - Google Patents

Abstract

PURPOSE:To obtain a signal transmission/reception circuit connecting the device of the parallel system to a serial data transmission line by selecting each one signal line among plural signals lines. CONSTITUTION:Signal lines DI01,...DI08 inputting/outputting a 1-byte data as a data bus signal, a DAV representing the effective period of a transmission data, an NRFD representing the reception enable state at the reception side and NDAC representing the end of reception, three control signals are connected. To simplify a signal selection synchronism circuit A5, an external clock signal CLK is used. All signal transmission/reception circuits connected to a serial transmission line S1 are synchronized with the external clock CLK, the DI01 is selected at a time slot T1, the DI02,... are selected at a time slot T2, the DAV is selected at a time slot T9, the NDAC is selected at a time slot T10 and the NRFD signal is selected at a time slot T11 sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmitting/receiving circuit for a data bus terminal device used in a digital data processing device such as a computer 2 communication control device or a measuring instrument.

2. Description of the Related Art Conventionally, digital data processing devices such as converter 2 communication control devices and measuring instruments transmit and receive signals and data using a plurality of signal lines called paths. On the other hand, with recent advances in 'LE4I technology, circuits have become smaller and more inexpensively available, and serial data transfer systems incorporating a parallel-to-serial conversion circuit and a protocol control circuit have come to be adopted. In this serial data transfer method, the number of signals connecting devices or circuits is small, so L
In addition to the advantages of reducing the cost of connectors and connection cables, which are expensive compared to SI, and making it possible to miniaturize the device, it is easy to increase the length of the connection cable, and the device can be made smaller. Connection/disconnection becomes easy, and furthermore,
There is an advantage that isolation between connected devices and circuits is also dramatically simplified. For these reasons, attempts have been made to connect parallel data bus type devices using higher bandwidth serial data transmission lines.

However, immediately changing from a conventional serial data node system to a serial data node system would require major changes to the hardware and software because the data transmission and reception procedures are different. ,
Therefore, it requires a lot of cost. Against this background,
It is desired to connect devices and circuits based on the conventional (conventional) parallel data bus system using a serial data transmission line through a simple additional circuit without changing the hardware or software. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal transmitting/receiving circuit for connecting a serial data transmission line to a serial data transmission line.

The present invention provides a signal transmitting/receiving circuit that transmits and receives binary signals on a plurality of bidirectional signal lines via one bidirectional serial data transmission path.
means for outputting the signal of the selected signal line to the bidirectional serial data transmission line when each book is selected; means for inputting and temporarily holding the signal of the transmission line at the time of output; and means for outputting the temporarily held signal input simultaneously with the selection to the signal line selected at the time of the selection.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a digital data processing device in which devices are connected to each other using a general parallel data bus method. A set of signal lines constituting the bus are PI, P2. P3
．． ..., pt is shown by one line, and n connected to it
El, E2゜E3. ..., indicated by En. FIG. 2 is a block diagram of a digital data processing apparatus in which an embodiment of the present invention is inserted into the configuration of FIG. 1. CI in the figure.

C2, Cs, , -, Cn I/i Sono Real IFa In the example, L and sl indicate serial data transmission paths. A set of signals [Ptl.

PI2. ...-, PI t], (P2 l, P22.
....

P2t], [:Pa1. Pa2. ..., P3t]+
....

[Pn 1. P n 2. −=, P n t] is 1
By the function of the embodiment of the present invention (signal transmitting/receiving circuit), the first
A set of signals [:Pl, P2 . ..., Pt]
Since the values are exactly the same, the devices El, E2 . E3゜-
--, all of them are connected by the serial data transmission line Sl without affecting En at all.

FIG. 3 is a block diagram showing the configuration of the embodiment of FIG. 2. This embodiment includes one bidirectional signal line PI, P2
．． ..., PL and one serial data transmission line S1 are connected. A1 is the signal line P1゜P2. ..., Pt signal is selected and inputted, and the selected signal D is sent to the transmitting circuit section A3.
This figure shows a parallel-to-serial conversion circuit section that outputs LE.

Further, A2 is the signal 02t input from the receiving circuit section A4,
Signal line Pi.

P2. . . . shows a serial-to-parallel converter circuit section of Pt which outputs to the selected signal line.

A5 is a signal line selection synchronization circuit section which generates a selection signal D5 and also outputs a transmission control signal D3 and a reception control signal D.
Generates 4.

FIG. 4 is a block diagram showing the circuit configuration of a specific example applied to the IEEE-488 standard in Embodiment 6 of FIG. 3, and FIG. 5 is a waveform diagram of the external clock signal CLK input to this specific example. This standard, which is widely used as a parallel data bus, uses eight data signals and eight control signals to perform 1:n data transfer all at the same time. Fourth
In the figure, only the three-wire handshake signals necessary for data transfer are described, but the invention can also be applied to the other five control lines without any problem.

The specific example in this figure includes signal lines DIOI, DI02.・・・
・DIO3 and DAV indicating the validity period of the transmitted data,
Three control signals are connected: NRFD indicating a reception ready state on the receiving side and NDAC indicating completion of reception. In order to simplify the No. 100 selection synchronization circuit A5, an external clock signal CLKili is used. As shown in the clock waveform diagram in FIG.
All the signal transmitting/receiving circuits connected as shown in the diagram (the application example in Figure 4) synchronize with this external clock CLK, time slot Ttic is DIO1, time slot T2 is DIO1, etc. 1) in time slot T9
AV, N1) AC in time slot T10.

Then, the NRFD signals are sequentially selected for the time slot Tll.

The operation of the signal transmitting/receiving circuit during one time slot (one time slot) is as follows. First, time slot T1
0 will be explained. In the first half when the TIO (time slot) is at the no-y level, the parallel-serial conversion circuit section A1 and the transmission circuit section A3 select the signal NDAC and output it to Sl.
At the same time, the OR signal on Sl received by the receiving circuit section A4 is outputted as an N1) AC signal via the serial-to-parallel conversion circuit section A2. In the first half of the time slot TIO, which is at the no-y level, the output of the serial-parallel conversion circuit A2 is connected to the NDAC signal, and the output control signal EN3 is turned on (low level) to form a wired OR logic. ing. Time slot T1o where the next clock is at low level
In the second half of , the output control signal EN3 is turned off () / level)
becomes.

Therefore, since the signal line Nu)AC is separated from the output line of the serial/parallel conversion circuit section A2, the output value of the NDAC signal line of the device to which the signal transmitting/receiving circuit is directly connected is input to A1 and is input to Sl is output to. At the rising edge of the external clock signal CLK in the time slot Tll, the signal value on 81 of the preceding cycle (time slot Tlo) is latched into A2 via A4 and output to gN3 again.
is turned on (low level), and the signal NDAC becomes wired OR logic.

The operation of one clock cycle (one time slot) for the signal NDAC has been explained above, but D-process Q1 to Q8.
NRFi) and DAv are transmitted and received in exactly the same way.

Next, a data transmission/reception procedure using three-wire handshake will be explained. FIG. 6 is an explanatory diagram of the three-wire handshake operation. A device that transmits data in one data transfer is called a talker, and a device that receives data is called a listener. The talker uses signals DI01-8. and DAV are used exclusively for output, and N1 (FD and NDAC are used as input-only lines. The listener uses signals DIO1 to 8 and DAV only for input. There is only one talker, but there are usually multiple listeners. The talker detects the listener's receivable state, and when the output data becomes stable, it sets the DAVi low level, which indicates the data validity period.When the listener detects the DAV low level, it indicates that it is receiving data. In order to notify, set NRFD to low level ■ and set data signal 1) IO1
-Include the contents of 8. When the listener completes inputting data, it turns off (N1) AC (high level). When the NDAC outputs from all listeners are off (1 level), the NDAC signal becomes high level, and the talker detects this and sets the DAV to no level -2, and turns off the data signal. As for the listener, DAV is no level.■
It detects that the NDAC has become low level again.
Return it to When the listeners are ready for the next data transfer, they turn NRFDi off ( ), and when all listeners are ready to receive data, the signal N RF D becomes high again.

The signal transmitting/receiving circuit of this specific example detects the falling edge of DAV and determines whether it is a talker or a listener. If it is a talker, all NRFD and NDAC signals are input exclusively, and the following control is performed. . 't That is, when the signal selection cycle becomes NRFD and NDACiC,
The signal EN1 is turned off (high level) so that no signal is output to Sl, and all the corresponding output control signals EN2 and EN3 are kept on (low level) for that period, and the information signal lines NRF D and The NDAC is configured so that a signal value always appears from the listener. In addition, if it is determined that the listener is a listener, the signals DI01 to
8. and performs exactly the same control as described above for DAVi input only.

As described above, according to the present invention, it is possible to provide a No. 13 transmitter/receiver circuit that connects devices that are conventionally connected to each other via a parallel bus consisting of a plurality of information signal lines to each other via a single serial transmission line. According to this signal transmitting/receiving circuit, the transmission capacity, which is limited by increasing the distance between devices or increasing the distance, is increased. In addition to the performance benefits of easing the isolation between devices, which was difficult due to the large number of lines 18, there is also the economic benefit of lowering the prices of connectors and cables. . Historically, if the signal transmitting/receiving circuit of the present invention is used, it is possible to connect with a serial transmission line without changing the protocol of the conventional parallel data bus, so no new development is required on the device side.

In addition, in the above-mentioned embodiment, the transmitting circuit section A3 and the receiving circuit section A4 are provided with an electrical-to-optical converter and an optical-electrical converter, respectively, and an optical fiber is used through the serial transmission line. Then, the transmission distance, transmission capacity, and isolation characteristics will also be more effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a digital data processing device in which devices are connected to each other using a general parallel data bus system. Fig. 2 is a block diagram of a digital data processing device in which an embodiment of the present invention is inserted into the configuration of Fig. 1. Figure 3 is a block diagram showing the configuration of the embodiment shown in Figure 2, Figure 4 is a block diagram of a specific example in which the embodiment shown in Figure 3 is applied to the IKEE-488 standard, and Figure 5 is a block diagram showing the configuration of the embodiment shown in Figure 4. FIG. 6 is an explanatory diagram of the operation of the three-wire handshake in the specific example of FIG. 4. Et, E2, E3, ..., En... Data bus terminal device, PI, P2, ----=Pt, Pi 1,
-Pnt...Data path signal line, C1, C2,
C3... CIl...Coding transmission/reception circuit of one embodiment of the present invention, A1...Parallel-serial conversion circuit section, A
2... Serial-parallel conversion circuit section, A3.
...Transmission circuit section, A4...Reception circuit section,
A5...Signal selection synchronization circuit section, DI...
・Transmission signal, l)2... Reception signal, D3...
...Transmission control signal, D4...Reception control signal,
D5... Signal selection signal, Sl... Serial transmission line, CLK... External clock for signal selection signal, N R FI)... Can be received. Signal line indicating status, NDAC... Signal line indicating reception completion status, DAV... Signal line indicating that the transmitted data is valid, DIOI~8... Data Signal line, ENl...... Regulatory signal line, EN2, which turns off the output in the case of a receive-only signal. EN3..., ENl2... Signal lines that control the output from the serial to parallel conversion circuit section.

Claims (1)

[Claims] In a signal transmitting/receiving circuit that transmits and receives binary signals on a plurality of bidirectional signal lines via one bidirectional serial data transmission path, one of the plurality of signal lines is selected and the means for outputting the signal on the selected signal line to the bidirectional serial data transmission line; means for inputting and temporarily holding the signal on the transmission line at the time of output; and means for inputting and temporarily holding the signal on the transmission line at the time of output; and means for outputting the temporarily held signal input at the same time as the selection.