JPH0795249A - Ternary transmission device - Google Patents

Abstract

PURPOSE:To increase the data amount to be sent without increasing the number of transmission lines and to shorten the time required for the transmission. CONSTITUTION:A binary-ternary number conversion part 3 of a transmission circuit 1 converts the binary data into the ternary data. An inverter circuit 11, NAND circuit 12, NOR circuit 13, and P-type MOS transistor 14, and N-type MOS transistor 15 output the low-level state, high-level state, and high- impedance state to a transmission line 100 corresponding to the ternary data from the binary-ternary number conversion part 3. Comparator circuits 25 and 26 of a reception circuit 2 detect whether or not the potential of nodes 27 and 28 is higher than that of the intermediate voltage 1/2 VDD. A ternary-binary number conversion part 4 converts the identification result of the comparator circuit 25 and 26 into binary data at the output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary transmission device, and more particularly to a digital data transmission system.

[0002]

2. Description of the Related Art Conventionally, in a digital data transmission system, as shown in FIG. 6, digital data transmitted from a driver circuit 71 of a transmission side circuit 7 onto a transmission path 200 is received by a receiver circuit 81 of a reception side circuit 8. I am receiving.

At this time, the transmission side circuit 7 and the reception side circuit 8
A clock signal 101 is input to each of the circuits, and the clock signal 101 causes the transmission side circuit 7 and the reception side circuit 8 to operate in synchronization.

Now, in the transmitting side circuit 7, the clock signal 10
When binary data of either high level or low level is input to the signal line IN in synchronization with 1, the driver circuit 7
Binary data synchronized with the clock signal 101 is sent from 1 to the transmission path 200.

This binary data (data 1 to data 4, ...
Is transmitted from the transmission side circuit 7 to the reception side circuit 8 through the transmission path 200.

In the receiving side circuit 8 that receives the binary data, the binary data is input from the transmission path 200 to the input terminal of the receiver circuit 81, and the binary data is output from the output terminal of the receiver circuit 81 to the signal line OUT. To be done.

In the conventional digital data transmission system, as described above, one binary data of either high level or low level per clock is transmitted by the transmission line 200.
Is transmitted from the transmission side circuit 7 to the reception side circuit 8 via.

[0008]

In the above-mentioned conventional digital data transfer method, since the data transmitted on the transmission path is binary data of either high level or low level, data that can be transmitted per unit clock. Quantity 1
It has become a bit. Therefore, there is a drawback that the number of transmission lines must be increased in order to increase the amount of data that can be transmitted per unit clock.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and to provide a ternary transmission apparatus capable of increasing the amount of data that can be transmitted and increasing the transmission time without increasing the number of transmission paths. is there.

[0010]

A ternary transmission device according to the present invention comprises a conversion means for converting a binary input signal into a ternary signal, and a high level state, a low level state and a high level state according to the ternary signal. The transmitting side is provided with an output means for outputting one of the impedance state.

According to another ternary transmission device of the present invention, the transmission line is based on an intermediate voltage between a high level power supply voltage indicating a high level state of the transmission line and a low level power supply voltage indicating a low level state of the transmission line. Receiving identification means for identifying which state among the high level state, the low level state and the high impedance state, and means for converting the identification result of the identification means into a binary output signal. Be prepared for the side.

Another ternary transmission device according to the present invention is provided on the transmission side and is provided with conversion means for converting a binary input signal into a ternary signal, and is provided on the transmission side according to the ternary signal. Output means for outputting one of a high level state, a low level state and a high impedance state, and provided on the receiving side,
The output signal from the output means is based on an intermediate voltage between a high level power supply voltage indicating the high level state and a low level power supply voltage indicating the low level state, the high level state, the low level state and the high impedance state. It is provided with an identification means for identifying which of the two states is present and a means provided on the receiving side for converting the identification result of the identification means into a binary output signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the transmission side circuit 1 and the reception side circuit 2 are connected by a transmission line 100. Further, the clock signal 10 is applied to each of the transmitter circuit 1 and the receiver circuit 2.
1 is input, and the clock signal 101 causes the transmission side circuit 1 and the reception side circuit 2 to operate in synchronization.

In the transmission side circuit 1, a binary / ternary conversion unit (hereinafter referred to as a conversion unit) 3 converts an input signal 110 which is binary data and control signals 111 and 11 which indicate ternary data.
Convert to 2.

The converter 3 converts the control signal 111 into a NAND (NA).
The control signal 112 is output to the ND) circuit 12 and the NOR circuit 13, and the control signal 112 is output to the inverter (INV) circuit 11, the NAND circuit 12, and the NOR circuit 13, respectively.

The inverter circuit 11 inverts the control signal 112 and outputs an inverted output 113 to the NAND circuit 12.

The NAND circuit 12 takes the NAND of the control signal 111 and the inverted output 113 and outputs the result as the output signal 114.
Is output to the gate of the P-type MOS transistor 14.

The NOR circuit 13 takes the NOR of the control signals 111 and 112 and outputs the result as an output signal 115 for the N-type MO.
Output to the gate of the S transistor 15.

In the P-type MOS transistor 14, the gate input is connected to the output signal 114 from the NAND circuit 12, the source input is connected to the high level power supply VDD, and the drain output is connected to the transmission line 100.

The N-type MOS transistor 15 has a gate input connected to the output signal 115 from the NOR circuit 13, a source input connected to the low-level power supply GND, and a drain output connected to the transmission line 100.

In the transmission side circuit 1, when the conversion unit 3 outputs the ternary number "0" to set the control signals 111 and 112 to low levels, respectively, the inverted output 113 from the inverter circuit 11 and the NAND circuit 12 are outputted. The output signal 114 and the output signal 115 from the NOR circuit 13 become high level, respectively.

As a result, the P-type MOS transistor 1
4 is turned off and the N-type MOS transistor 15 is turned on, so that the low level state is output on the transmission path 100.

Further, in order for the conversion unit 3 to output a ternary number "1", the control signal 111 is set to a high level, and the control signal 11
When 2 is set to low level, the inverted output 113 from the inverter circuit 11 becomes high level, and the output signal 114 from the NAND circuit 12 and the output signal 115 from the NOR circuit 13 become low level, respectively.

As a result, the P-type MOS transistor 1
4 is turned on and the N-type MOS transistor 15 is turned off, so that the high level state is output on the transmission path 100.

Further, when the conversion unit 3 outputs the ternary number "2" to set the control signal 112 to the high level, the inverted output 113 from the inverter circuit 11 becomes the low level,
The output signal 114 from the NAND circuit 12 goes high and the output signal 115 from the NOR circuit 13 goes low.

As a result, the P-type MOS transistor 1
4 is turned off and the N-type MOS transistor 15 is also turned off, so that a high impedance state is output on the transmission path 100 regardless of the level value of the control signal 111 from the conversion unit 3.

Therefore, the ternary data represented by the control signals 111 and 112 output from the conversion unit 3 is output on the transmission line 100 in the low level state, the high level state, or the high impedance state, whichever corresponds.

In the receiving side circuit 2, the resistance element 21 is inserted between the high level power supply VDD and the node 27, and the resistance element 22 is inserted between the node 27 and the transmission path 100. The resistance element 23 is connected to the transmission line 100 and the node 28.
And the resistance element 24 is inserted between the node 28 and the low-level power supply GND.

In the comparator circuit 25, the node 27 is connected to the non-inverting input terminal, and the high level power supply VDD is connected to the inverting input terminal.
And an intermediate voltage ½ VDD of the low level power supply GND is connected. That is, the comparator circuit 25 is connected to the node 2
It is detected whether the potential of 7 is higher than the intermediate voltage 1/2 VDD.

In the comparator circuit 26, the node 28 is connected to the non-inverting input terminal, and the high level power supply VDD is connected to the inverting input terminal.
And an intermediate voltage ½ VDD of the low level power supply GND is connected. That is, the comparator circuit 26 is connected to the node 2
It is detected whether the potential of 8 is higher than the intermediate voltage 1/2 VDD.

However, assuming that the resistance values of the resistance elements 21 to 24 are R21 to R24, respectively, the resistance values of the resistance elements 21 to 24 are designed so that R21 = R24> R22 = R23.

The ternary / binary number conversion unit (hereinafter referred to as a conversion unit) 4 is the result of the state on the transmission line 100 being identified by the comparator circuits 25 and 26, that is, the output signals 121 and 121 from the comparator circuits 25 and 26. Based on 122, the ternary data represented by the state on the transmission path 100 is converted into binary data and output as the output signal 120.

In the receiving side circuit 2, when the state of the transmission line 100 becomes the high level state, the potential of the node 27 becomes the high level state. At this time, the potential of the node 28 is (potential of the transmission line 100-low level potential) .R24 / (R
23 + R24).

By substituting the previously set R23 and R24 into this equation, the potential of the node 28 becomes higher than 1/2 VDD. Therefore, high levels are output to the output signals 121 and 122 from the comparator circuits 25 and 26, respectively.

When the transmission line 100 is in the low level state, the potential of the node 28 is in the low level state. At this time, the potential of the node 27 is (high level potential-potential of the transmission line 100) .R22 / (R
21 + R22).

By substituting the previously set R21 and R22 into this equation, the potential of the node 27 becomes lower than 1/2 VDD. Therefore, low levels are output to the output signals 121 and 122 from the comparator circuits 25 and 26, respectively.

Further, when the state of the transmission line 100 becomes a high impedance state, the potential of the node 27 becomes VDD (R22 + R23 + R24) / (R21 + R22 + R23 + R24).

By substituting the previously set R21 to R24 into this equation, the potential of the node 27 becomes higher than 1/2 VDD. At this time, the potential of the node 28 becomes VDDR24 / (R21 + R22 + R23 + R24).

By substituting the previously set R21 to R24 into this equation, the potential of the node 28 becomes lower than 1/2 VDD. Therefore, a high level is output to the output signal 121 from the comparator circuit 25, and the comparator circuit 26
A low level is output as the output signal 122 from.

Therefore, the conversion unit 4 changes the state of the transmission line 100 based on the result of the discrimination of the state on the transmission line 100 by the comparator circuits 25 and 26, that is, the output signals 121 and 122 from the comparator circuits 25 and 26. It is converted into corresponding binary data and output as an output signal 120.
As a result, the transmission line 1
It is possible to transfer three values of low level state, high level state, and high impedance state by 00.

For example, when transferring a number of 238 (decimal number), it is 23 in the conventional digital data transmission system.
Since 8 is represented by a binary number “11101110” and this is transmitted digit by digit, the number of clocks required for the transfer is 8.

On the other hand, in the embodiment of the present invention, when "11101110" is input to the input signal 110, this "11101110" is converted into a binary number "222" by the conversion unit 3.
11 ”and is output to the transmission line 100 in three states of a low level state, a high level state, and a high impedance state.

The state on the transmission path 100 is discriminated by the comparator circuits 25 and 26, and is converted into a binary number "11101110" by the conversion unit 4 in accordance with the state and output as an output signal 120.

Therefore, in one embodiment of the present invention, the binary number "11101110" is converted into the ternary number "22211" and this is transmitted digit by digit. Therefore, the number of clocks required for the transfer is 5, and the transfer time is reduced. It can be shortened as compared with the conventional one.

FIG. 2 is a block diagram showing the configuration of the conversion unit 3 of FIG. In the figure, the converter 3a of the converter 3 receives the input signal 110 which is binary data and parallel data, converts the binary data into ternary data, and outputs the signal indicating the ternary data to the terminal. a1-a6, b1-b6
To parallel-to-serial conversion circuits 3b and 3c, respectively.

In this case, the signals from the terminals a1 and b1 are 1
It shows the ternary data of the bit, the signals from the terminals a2 and b2 show the ternary data of the second bit, the signals from the terminals a3 and b3 show the ternary data of the third bit, and the terminals a4 and a4.
The signal from b4 shows the 4-bit ternary data, the signals from the terminals a5 and b5 show the 5-bit ternary data, and the signals from the terminals a6 and b6 show the 6-bit ternary data. ing.

The parallel-serial conversion circuits 3b and 3c serially convert the signals from the terminals a1 to a6 and b1 to b6 of the converter 3a, respectively, and control the signals from the terminals a1 to a6 and b1 to b6 from the conversion unit 3. The signals 111 and 112 are sequentially output.

Therefore, the parallel-serial conversion circuit 3
From b and 3c, signals from terminals a1 and b1, terminals a2 and
Signal from b2, signal from terminals a3 and b3, terminal a
4, the signals from b4, the signals from terminals a5 and b5, and the signals from terminals a6 and b6 are output in this order.

The converter 3a is a decoder configured to convert the input signal 110, which is binary data, into two signals that represent ternary data. As this decoder, a normal decoder including an inverter and a NAND gate is used. Can be used.

When the input signal 110 is a serial signal, the input signal 110 may be input to the converter 3a after being converted into a parallel signal by a serial / parallel conversion circuit.

FIG. 3 is a block diagram showing the configuration of the conversion unit 4 of FIG. In the figure, the serial / parallel conversion circuits 4b and 4c of the conversion unit 4 convert the output signals 121 and 122 from the comparator circuits 25 and 26 into parallel signals and output them to the converter 4a.

The converter 4a is a serial-parallel conversion circuit 4
The signals input from the terminals b and 4c to the terminals c1 to c6 and d1 to d6 are converted into binary data, and this binary data is output as the output signal 120.

The converter 4a has two output signals 121, 1 from the comparator circuits 25, 26 which indicate ternary data.
It is a decoder configured to convert 22 into an output signal 120 which is binary data, and as this decoder, a normal decoder including an inverter and a NAND gate can be used.

When the output signal 120 is a serial signal, the signal from the converter 4a is converted into a serial signal by a serial / parallel conversion circuit, and then the output signal 120 is output.
Should be output as.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, according to another embodiment of the present invention, the ternary data converted by the converter 3 is transmitted in one of three states of a low level state, a high level state and a high impedance state.
1 has the same configuration as that of the embodiment of the present invention shown in FIG. 1 except that the configuration of the circuit to be output to 00 is different, and the same components are designated by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The inverter circuit 51 of the transmission side circuit 5 inverts the control signal 111 from the conversion unit 3 and outputs the inverted output 151 to the clocked inverter circuit 52. The inverter circuit 53 inverts the control signal 112 from the conversion unit 3 and outputs an inverted output 152 to the clocked inverter circuit 52.

The clocked inverter circuit 52 has an inverting output 151 of the inverter circuit 51 connected to an input, and a control signal 11 from the conversion section 3 to an N-channel side control terminal.
2 is connected, the inverted output 152 of the inverter circuit 53 is connected to the P-channel side control terminal, and the transmission line 100 is connected to the output.

FIG. 5 shows the clocked inverter circuit 5 of FIG.
It is a circuit diagram which shows the structure of 2. In the figure, a clocked inverter circuit 52 is a P-type MOS transistor 52a,
52b and N-type MOS transistors 52c and 52d.

In the P-type MOS transistor 52a, the gate input is connected to the inverting output 151 of the inverter circuit 51, the source input is connected to the high level power supply VDD, and the drain output is connected to the source input of the P-type MOS transistor 52b.

In the P-type MOS transistor 52b, the gate input is the inverted output 152 of the inverter circuit 53, the source input is the drain input of the P-type MOS transistor 52a,
The drain outputs are connected to the transmission line 100, respectively.

The N-type MOS transistor 52c has a gate input for the control signal 112 from the conversion unit 3 and a source input for N.
The drain output of the type MOS transistor 52d is connected to the drain output of the MOS transistor 52d.

The N-type MOS transistor 52d has a gate input to the inverting output 151 of the inverter circuit 51, a source input to the low-level power supply GND, and a drain output to the N-type MOS transistor 52d.
The source inputs of the transistors 52c are respectively connected.

In the transmission side circuit 5, when the control signals 111 and 112 from the converter 3 become high level, the inverted outputs 151 and 152 of the inverter circuits 51 and 53 become low level.

As a result, the P-type MOS transistors 52a and 52b and the N-type MOS transistor 52c of the clocked inverter circuit 52 are turned on, and the N-type MO transistor is turned on.
Since the S transistor 52d is turned off, the transmission line 1
A high level state is output on 00.

When the control signal 111 from the conversion unit 3 goes low and the control signal 112 goes high, the inverted output 151 of the inverter circuit 51 goes high.
The inverted output 152 of the inverter circuit 53 becomes low level.

As a result, the P-type MOS transistor 52a of the clocked inverter circuit 52 is turned off, and the P-type MOS transistor 52b and the N-type MOS transistors 52c and 52d are turned on. The status is output.

Further, when the control signal 112 from the converter 3 becomes low level, the inverted output 15 of the inverter circuit 53 is generated.
2 becomes high level. As a result, both the P-type MOS transistor 52b and the N-type MOS transistor 52c of the clocked inverter circuit 52 are turned off, so that regardless of the level value of the control signal 111 from the conversion unit 3, the high level on the transmission line 100. The impedance state is output.

Therefore, the ternary data represented by the control signals 111 and 112 output from the conversion unit 3 is output on the transmission line 100 in the low level state, the high level state, or the high impedance state, whichever corresponds.

As described above, the conversion unit 3 of the transmission side circuits 1 and 5
Converts a binary signal into a ternary signal, outputs one of a high level state, a low level state, and a high impedance state on the transmission path 100 in accordance with the ternary signal, and Transmission line 1 by the comparator circuits 25 and 26
It is possible to increase the amount of data that can be transmitted in one clock by identifying the state on 00 and converting the state on the transmission path 100, that is, a ternary signal into a binary signal by the conversion unit 4 based on the identification result. it can. Therefore, the data transmission time can be shortened.

Further, even when transmission is performed using a plurality of transmission lines, a large amount of information can be transmitted with one wiring. Can be reduced.

Although the converter 3 is provided on the transmitting side and the converter 4 is provided on the receiving side in one and other embodiments of the present invention, the low level state, the high level state, and the high impedance state are transmitted. If a quantizer circuit or the like that outputs on the road is used, the conversion unit 3 becomes unnecessary.

Further, the comparator circuits 25 and 2 on the receiving side
If the receiving side has a circuit that uses the output signals 121 and 122 of No. 6 as they are, it is obvious that the conversion unit 4 is not necessary, and the present invention is not limited to these.

[0074]

As described above, according to the present invention, a converting means for converting a binary input signal into a ternary signal, and a high level state, a low level state and a high impedance state according to the ternary signal. An output means for outputting one of the above is provided on the transmission side, and the output signal from the output means is based on the intermediate voltage between the high level power supply voltage indicating the high level state and the low level power supply voltage indicating the low level state. By providing the receiving side with an identification means for identifying which of the high level state, the low level state and the high impedance state, and a means for converting the identification result into a binary output signal, the transmission line It is possible to increase the amount of data that can be transmitted and increase the transmission time without increasing the number of transmissions.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a binary number-to-binary number conversion unit in FIG.

3 is a block diagram showing a configuration of a ternary number / binary number conversion unit in FIG. 1. FIG.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

5 is a circuit diagram showing a configuration of the clocked inverter circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 5 Transmitting side circuit 2 Receiving side circuit 3 Binary number-to-binary number conversion unit 3a converter 3b, 3c Parallel-serial conversion circuit 4 Ternary-to-binary number conversion unit 4a converter 4b, 4c Serial parallel conversion circuit 11, 51, 53 inverter circuit 12 NAND circuit 13 NOR circuit 14, 52a, 52b P-type MOS transistor 15, 52c, 52d N-type MOS transistor 25, 26 comparator circuit

Claims (7)

[Claims] 1. A conversion means for converting a binary input signal into a ternary signal, and an output means for outputting one of a high level state, a low level state and a high impedance state according to the ternary signal. A ternary transmission device having a transmission side. 2. The state of the transmission line is based on an intermediate voltage between a high level power supply voltage indicating a high level state of the transmission line and a low level power supply voltage indicating a low level state of the transmission line. The receiving side has identification means for identifying which one of the low level state and the high impedance state is present, and means for converting the identification result of the identification means into a binary output signal. Value transmission device. 3. The identifying means includes first comparing means for comparing the signal on the transmission line pulled up to the high level power supply voltage side with the intermediate voltage, and pulled down to the low level power supply voltage side. Second comparing means for comparing the signal on the transmission line with the intermediate voltage; and the first and second comparing means.
Means for discriminating which of the high level state, the low level state and the high impedance state the signal on the transmission line is in from the comparison result of each of the comparing means. The three-value transmission device according to claim 2, wherein the three-value transmission device is adapted to be converted into a value output signal. 4. The first comparing means includes a first resistance element connected between a high-level power supply and a first node, a second node serving as an input, and the first node. A second resistance element connected in between, and a first comparator in which the first node is connected to a non-inverting input terminal and the intermediate voltage is connected to an inverting input terminal, and the second comparator The means includes a third resistance element connected between the second node and the third node, and a fourth resistance element connected between the third node and the low-level power supply. 4. The three-valued transmission device according to claim 3, wherein the third node comprises a second comparator connected to the non-inversion input terminal and the intermediate voltage connected to the inverting input terminal. 5. A conversion means provided on the transmission side for converting a binary input signal into a ternary signal, and provided on the transmission side.
Output means for outputting one of a high level state, a low level state and a high impedance state according to the ternary signal, a high level power supply voltage provided on the receiving side and showing the high level state, and the low level Identification means for identifying which of the high level state, the low level state and the high impedance state the output signal from the output means is based on an intermediate voltage between the low level power supply voltage indicating the state and A ternary transmission device, wherein the ternary transmission device is provided on the receiving side, and has means for converting an identification result of the identification means into a binary output signal. 6. The identifying means comprises first comparing means for comparing the output signal from the output means pulled up to the high level power supply voltage side with the intermediate voltage, and the low level power supply voltage side. Second comparing means for comparing the output signal from the output means pulled down and the intermediate voltage;
Means for identifying which of the high level state, the low level state and the high impedance state the output signal from the output means is based on the comparison result of each of the first and second comparing means. 6. The ternary transmission device according to claim 5, further comprising: converting the identification result into the binary output signal. 7. The first comparing means includes a first resistance element connected between a high level power source and a first node, a second node serving as an input, and the first node. A second resistance element connected in between, and a first comparator in which the first node is connected to a non-inverting input terminal and the intermediate voltage is connected to an inverting input terminal, and the second comparator The means includes a third resistance element connected between the second node and the third node, and a fourth resistance element connected between the third node and the low-level power supply. 7. The ternary transmission device according to claim 6, wherein the third node comprises a second comparator connected to the non-inverting input terminal and the intermediate voltage connected to the inverting input terminal.