JPS56153840A - Ternary level input circuit - Google Patents

Ternary level input circuit

Info

Publication number
JPS56153840A
JPS56153840A JP5548780A JP5548780A JPS56153840A JP S56153840 A JPS56153840 A JP S56153840A JP 5548780 A JP5548780 A JP 5548780A JP 5548780 A JP5548780 A JP 5548780A JP S56153840 A JPS56153840 A JP S56153840A
Authority
JP
Japan
Prior art keywords
channel mos
level
cmps
supplied
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5548780A
Other languages
Japanese (ja)
Inventor
Akio Kawazoe
Kenji Tadokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5548780A priority Critical patent/JPS56153840A/en
Publication of JPS56153840A publication Critical patent/JPS56153840A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To obtain a low-power consumption circuit adapted to the IC, by constituting a comparator with the P channel MOS.FET having the first threshold level and the N channel MOS.FET having the second threshold level. CONSTITUTION:The input signal is supplied from terminal 3 through setting switch 1 and is supplied to gates of FETs of comparators CMP5 and CMP6. CMPs 5 and 6 consists of P channel MOS.FET14 and N channel MOS.FET15, respectively, and bias voltages are supplied to gates of respective MOSs from the connection point of resistances RB1 and RB2 of the same value which are connected between power source voltage VDD and the earch. Outputs 7 and 8 of CMPs 5 and 6 are input to decoder 9, and the signal of a ternary level is outputted to output lines 10-12 from decoder 9. CMP5 has a threshold value higher than 1/2 VDD, and CMP6 has a threshold level lower than it. Output 7 and 8 of CMPs 5 and 6 become L or H-level as shown in the table in accordance with the position of the movable terminal of switch 1, and the H or L-level signal is outputted to output lines 10-12 on the basis of these output levels.
JP5548780A 1980-04-28 1980-04-28 Ternary level input circuit Pending JPS56153840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5548780A JPS56153840A (en) 1980-04-28 1980-04-28 Ternary level input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5548780A JPS56153840A (en) 1980-04-28 1980-04-28 Ternary level input circuit

Publications (1)

Publication Number Publication Date
JPS56153840A true JPS56153840A (en) 1981-11-28

Family

ID=12999978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5548780A Pending JPS56153840A (en) 1980-04-28 1980-04-28 Ternary level input circuit

Country Status (1)

Country Link
JP (1) JPS56153840A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177198U (en) * 1981-04-30 1982-11-09
JPS6019315A (en) * 1983-07-13 1985-01-31 Rohm Co Ltd Switching circuit
JPS622178A (en) * 1985-06-28 1987-01-08 Nec Corp Input buffer circuit
US5198707A (en) * 1990-05-30 1993-03-30 Jean Nicolai Integrated circuit with mode detection pin for tristate level detection
JPH0795249A (en) * 1993-09-22 1995-04-07 Nec Corp Ternary transmission device
US6486697B1 (en) * 1999-03-22 2002-11-26 University Of Southern California Line reflection reduction with energy-recovery driver

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177198U (en) * 1981-04-30 1982-11-09
JPS6019315A (en) * 1983-07-13 1985-01-31 Rohm Co Ltd Switching circuit
JPS622178A (en) * 1985-06-28 1987-01-08 Nec Corp Input buffer circuit
US5198707A (en) * 1990-05-30 1993-03-30 Jean Nicolai Integrated circuit with mode detection pin for tristate level detection
EP0459863B1 (en) * 1990-05-30 1993-07-21 STMicroelectronics S.A. Integrated circuit with mode detection pin
JPH0795249A (en) * 1993-09-22 1995-04-07 Nec Corp Ternary transmission device
US6486697B1 (en) * 1999-03-22 2002-11-26 University Of Southern California Line reflection reduction with energy-recovery driver
US6946868B2 (en) 1999-03-22 2005-09-20 University Of Southern California Line reflection reduction with energy-recovery driver
US7176712B2 (en) 1999-03-22 2007-02-13 University Of Southern California Line reflection reduction with energy-recovery driver
US7504852B2 (en) 1999-03-22 2009-03-17 University Of Southern California Line reflection reduction with energy-recovery driver

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