KR102338872B1 - Storage apparatus and method for processing a plurality of client data - Google Patents

Abstract

The present invention relates to a storage device and method for processing a plurality of client data. The storage device according to an embodiment of the present invention receives and stores the plurality of client data generated in burst units from a plurality of clients. a first storage unit; a second storage unit receiving the plurality of client data from the first storage unit and storing the plurality of client data in the plurality of memory banks shared by the plurality of clients in the burst unit, respectively; and a third storage unit for receiving each client data from the second storage unit and storing data in a transaction unit, which is a transmission unit for data processing.

Description

STORAGE APPARATUS AND METHOD FOR PROCESSING A PLURALITY OF CLIENT DATA

The present invention relates to a storage device and method for processing multiple client data.

In a data processing method that requires processing of a large number of different types of client data, such as a transmitter, a receiver, or a transceiver (or terminal) in a communication system, the amount of data required to be transmitted is different for each client, and the data generation time is also independent. Typically, different client data is stored in separate memories, and the size of the memory for each client data is not uniform. Therefore, if a memory configuration specialized for each client is used in the existing data processing method, the area efficiency of the memory is reduced due to some small-sized memories. In addition, the memory configuration specialized for each client has a problem in that the memory size increases in proportion to the amount of data to be processed by the processor at one time, and even if the amount of data for each client varies according to the operation scenario, memory for each client is efficiently redistributed Since it cannot be (reallocated), there is a burden of designing a larger memory overall.

The present invention provides an efficient data processing method and apparatus for collecting and transmitting data for each client.

In addition, the present invention provides a data storage method and apparatus for efficiently processing data for each client using multi-tiered memories.

A storage device for processing a plurality of client data according to an embodiment of the present invention includes a first-stage storage unit for receiving and storing the plurality of client data generated in burst units from a plurality of clients, and the first stage A second stage storage unit that receives the plurality of client data from the storage unit and stores the data in the plurality of memory banks shared by the plurality of clients in the burst unit, and transfers each client data from the second stage storage unit and a third storage unit for storing data of a transaction unit, which is a transmission unit for receiving and processing data.

In addition, a storage method for processing a plurality of client data according to an embodiment of the present invention includes a process of receiving the plurality of client data generated in burst units from a plurality of clients and storing the input data in a memory for each client; A process of receiving the plurality of client data from a memory and storing the data in a burst unit in a plurality of memory banks shared by the plurality of clients, and receiving each client data stored in the plurality of memory banks to a destination memory It includes the process of storing data in a transaction unit, which is a transmission unit for data processing.

1A is a diagram showing an example configuration of a data storage device for processing a plurality of client data in a communication system;
1B is a diagram showing another configuration example of a data storage device for processing a plurality of client data in a communication system;
2 is a diagram illustrating a pattern of data generated by a specific client;
3 is a diagram illustrating an example configuration of a data storage device for processing a plurality of client data in a communication system according to an embodiment of the present invention;
4 is a diagram showing an example of a configuration of a burst memory operating as a second stage storage unit in the storage device according to an embodiment of the present invention;
5 is a diagram illustrating an example of an access pattern of a burst memory in a storage device according to an embodiment of the present invention;
6 is a diagram illustrating an area of a memory required per 1 bit for each size of the memory according to an embodiment of the present invention;
7 is a diagram illustrating an example of an interface between a client and a data transfer unit in a storage device according to an embodiment of the present invention;
8 is a timing diagram for explaining a client data transmission operation in a storage device according to an embodiment of the present invention;
9 is a diagram illustrating an example of client data stored in a destination memory in a storage device according to an embodiment of the present invention.

In the following description of the embodiments of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

First, in a communication system, a transmitter, a receiver, or a transceiver (hereinafter, referred to as a 'terminal') includes one or a plurality of processors operating based on software, and one or a plurality of hardware blocks (or functional blocks) designed to perform predetermined operations. It can be implemented including Here, information is exchanged between the hardware block and the processor (or subsystem of the processor). Some of the result values obtained according to data operation in the hardware block may be transmitted to and processed by the processor, and various types of data may exist in the data transmitted and processed by the processor according to characteristics of the hardware block. These various types of data must be periodically or aperiodically generated in the hardware block and then transmitted to the processor within an appropriate time. Assuming a communication system, the various types of data are transmitted/received I ( Inphase/Q (Quadrature) data, processing results of cell searcher, channel estimation values of receivers, adaptive filter weights of equalizers, data such as channel decoding results, etc. can be exemplified.

Assuming that a plurality of hardware blocks operating at the same time are referred to as a plurality of clients, and different data generated in the plurality of hardware blocks is assumed to be different client data, refer to FIGS. 1A and 1B for better understanding of the present invention. An existing data storage device that processes different client data and a data processing method will be described first. Hereinafter, an embodiment of the present invention will be described assuming a storage device used in a terminal of a communication system, but the storage device according to an embodiment of the present invention can be used in various systems requiring data collection, transmission, and processing from multiple clients. The same can be applied.

1A is a diagram showing an example of a configuration of a data storage device that processes a plurality of client data in a communication system. The configuration of FIG. 1A shows a data storage device using a slave bus interface structure.

_{Referring to FIG. 1A , a plurality of client data (C 0} to C _{N -1} ) generated from a plurality of clients (clients 0 to N-1) 110 is stored in the storage unit 130 for each corresponding plurality of clients. It is stored in the memories (130 ₀ ~ 130 _N-1 ). The client-specific memory (memory 0 to _{N-1) (130 0 ~} 130 N-1) is the bit width (W ₀ ~ W _{N -1)} of the data (C ₀ ~ C _{N -1)} generated in the client and It has different memory sizes according to the amount of data generated per unit time. In addition, a processor (not shown _{) may read data output from the client-specific memories 130 0} to 130 _N-1 and multiplexed by the multiplexer 135 through the slave bus interface 150 . In FIG. 1B , reference numeral S1 denotes a memory selection for reading data from the _{memories 130 0} to 130 _{N-1 for each client in the slave bus interface structure.}

1B is a diagram showing another configuration example of a data storage device that processes a plurality of client data in a communication system. The configuration of FIG. 1B is data using a DMA (Direct Memory Access) bus interface structure that performs data input/output through interrupt It represents the storage device.

_{Referring to FIG. 1B , a plurality of client data (C 0} to C _{N −1} ) generated from a plurality of clients (clients 0 to N-1) 110 is stored in the storage unit 130 for each corresponding plurality of clients. It is stored in the memories (130 ₀ ~ 130 _N-1 ). The memories for each client (memories 0 to N-1) 130 ₀ to 130 _N-1 have different memory sizes according to different amounts of client data C ₀ to C _{N -1.} Data that is output from the memories 1300 to 130N-1 for each client and multiplexed in the multiplexer 135 is data that generates an interrupt to the processor core 180 such as a digital signal processor (DSP) or a central processing unit (CPU). It is transferred to the processor core 180 through the transfer module 160 and a random access memory (RAM) 170 .

In the above configuration of FIGS. 1A and 1B , the plurality of client-specific memories 130 ₀ to 130 _N-1 in the storage unit 130 are, for example, flip-flops or static random access memory (SRAM). It is implemented with an on-chip memory such as, but has the following problems. Specifically, in each of the client-specific memories 130 ₀ to 130 _N-1 , one client memory stores the amount of data processed at one time in software (hereinafter, “one transaction”). As a client memory, a flip-flop has the largest memory area per bit and SRAM also has a relatively large area per bit. increases

In addition, the SRAM used as the client memory includes not only a cell matrix that stores actual information, but also a control logic for decoding an address for reading and writing data and designating a cell to access. include Although the size of the cell matrix increases in proportion to the number of bits of data to be stored, the size of the control logic increases gently compared to the cell matrix, so that the smaller the memory capacity, the larger the area of silicon occupied per bit increases. As a result, the area efficiency of the memory decreases. In the existing implementation method of the client memory, the size of the client memory is also different because the amount of data for each client is different. When some of the client memories use a very small memory, the overall area efficiency decreases due to an increase in the silicon area occupied per bit. In addition, since each client memory is fixedly mapped to a specific client, the client memory cannot be efficiently reallocated and used according to the operating situation. In addition, in the existing implementation method of the client memory, when the amount of data generated by each hardware block (that is, the client) varies in various operation scenarios, each client memory should be made based on the largest data demand in all operation scenarios. Considering this, the area of the memory required as a whole is increased.

An embodiment of the present invention proposes a storage device using a memory having a multi-stage structure that can further reduce the area of a memory by using a traffic characteristic of client data transmitted from a plurality of clients. The data for each client may be understood as different types of data processed by a terminal using the storage device or the like.

In addition, in the storage device according to an embodiment of the present invention, most data of the amount of data to be processed by the processor at one time is stored in a memory having a relatively low implementation cost, and a memory having a high implementation cost is generated at once. It is proposed as a limiting method for the rapid storage of In addition, the storage device is proposed to reduce the use of a small-capacity memory in which the area efficiency of the memory is low, and to increase the overall area efficiency of the memory by using a memory of a predetermined capacity or more.

In addition, the storage device according to an embodiment of the present invention can easily change the memory allocation amount for each client through a configuration register when the memory requirement for each client varies according to various operation scenarios.

2 is a diagram illustrating a pattern of data generated by a specific client. Referring to FIG. 2 , after transmitting data, the client generates interrupts 205 and 207 to request processing from the processor. The processor collects data corresponding to one transaction (201, 203) and processes it at once, but actual data is generated by dividing it into several small bursts (211, 213). Accordingly, an embodiment of the present invention proposes a method in which one burst is first stored in an intermediate memory for each client, and the entire data of one transaction is stored in a destination memory having a relatively low implementation cost. The destination memory may use an external dynamic random access memory (DRAM) or SRAM, and the area efficiency is improved because the size of each instance is large. In an embodiment of the present invention, the burst may be understood as a generation unit of data generated by, for example, one client, and the transaction is data processed through a processor (eg, transmitted to software for performing a task). It can be understood as a transmission unit.

3 is a diagram illustrating an example of a configuration of a data storage device for processing a plurality of client data in a communication system according to an embodiment of the present invention. configuration is shown.

_{The storage device of FIG. 3 stores different types of client data (C 0} ~C _N-1 ) generated from a plurality of clients (clients 0 to N-1) 310 corresponding to a plurality of hardware blocks in the terminal. After receiving the input and temporarily storing it, it includes a data mover 330 that outputs it to the destination memory 350 . The data transfer unit 330 includes a first stage storage unit implemented with first in first out (FIFO) memories 331 for each client, and a plurality of client data (C ₀ to C) transferred from the first stage storage unit. _{N −1} ) each of which is stored in one burst unit, and a second stage storage unit implemented as a burst memory 335 that outputs the stored burst data to the destination memory 350 before the next burst data is input is included. The destination memory 350 may use an external memory or the like, and is used as a third stage storage unit. Accordingly, according to an embodiment of the present invention, the storage device configured with multi-tiered memories for processing a plurality of different types of client data may be implemented by including the first to third storage units. _{Here, different types of client data C 0} to C _{N -1} input to the FIF0 memories 331 may have different amounts of data. Meanwhile, in the above embodiment, it has been described that a plurality of client data (C ₀ ~ C _{N −1} ) transmitted from the first stage storage unit is stored in the burst memory 335 in one burst unit, respectively, but this is an example is shown, and the present invention is not limited thereto. Accordingly, it is also possible to store the client data in two or more burst units in the burst memory 335 .

Referring to the detailed operation of the data transfer unit 330 in FIG. 3 , the input FIF0 memories 331 serving as the first stage storage unit receive N different client data (C ₀ ~) from the N clients 310 . C _{N -1} ) is received and stored first in the input FIFO (First Input First Output) memory allocated for each client. Data for each client stored in the input FIFO memory for each client is formatted (333) in a predetermined manner, and is input to and stored in the burst memory 335 serving as the second stage storage unit. The format 333 is the data width (data width) (W ₀ ~ W _{N -1} ) of each client data is smaller than the memory bank width (W _B ) in the burst memory 335 After collecting the input data, again This is to efficiently use the memory by adjusting the size of the memory bank width W _{B .}

In an embodiment of the present invention, since the burst memory 335 stores one burst for each client, the amount of data to be stored in the burst memory 335 is greatly reduced compared to storing one entire transaction. Since the burst memory 335 uses a relatively high-cost memory, the embodiment of the present invention is implemented to store data in burst units, which are data generation units in the client. When one burst storage in the burst memory 335 is completed, the burst memory 335 outputs a pre-stored burst to the third storage unit before the next burst occurs and the existing data is overwritten. Each client data stored in the burst memory 335 as the second storage unit is transferred to the third storage unit during processing time between adjacent bursts. And, since the third storage unit uses a relatively low-cost memory, in the embodiment of the present invention, it is a transaction unit that is a data transmission unit (eg, a data transmission unit transmitted to software through the processor) processed through the processor. data can be saved. The software may process the data of the transaction unit at a time.

According to the above-described embodiment of the present invention, when client data is stored in a high-cost burst memory, only the burst amount generated once can be stored without storing the entire data of the transaction amount, which is a unit of one transmission, and adjacent bursts are stored. By transferring and storing the burst data to a low-cost memory during the processing time between them, it is possible to improve the memory usage efficiency compared to the cost.

If the processing time interval between the current burst and the next burst is very short and the processing time to transmit data to the third storage unit is insufficient, the corresponding client data (that is, data lacking processing time) in the second storage unit is, for example, The lack of processing time can be addressed by double buffering, which stores two or more burst quantities.

In addition, the storage device of FIG. 3 may include a configuration register (R1) for storing settings for processing each client data. The setting register R1 is, for example, a start address occupied by each client data in the burst memory 335, an address of the destination memory 350 to which each client data is finally stored, and a de-format ( 333) corresponding to the format (333) method. At least one of rules for processing each client data, such as de-formatting) 337 method, may be stored. In FIG. 3 , the output FIFO 336 temporarily stores data read from the burst memory 335 , and each client data output from the output FIFO 336 goes through a de-format 337 , and is a DMA controller eXDMAC (eXDMAC) ) (339) to the third stage storage unit. In addition, each client may request generation of an interrupt in a specific burst by using the control information transmitted to the data transfer unit 330, and an interrupt generation unit I1 for processing the interrupt may be included in the storage device of FIG. have.

In FIG. 3 , the third stage storage unit, which is the destination memory 350 , is an address space accessible by the processor as a final destination to which data is transmitted. The third storage unit may use, for example, a large-capacity data memory of an external DRAM or a specific processor inside the chip, and receives data through the eXDMAC 339, which is a DMA controller. The third storage unit stores one transaction for each client for data processing in the processor, and since the implementation cost per bit is relatively lower than that of the first storage unit or the second storage unit, the overall implementation cost is reduced. If there is a risk of data being overwritten while the data of the next transaction is transmitted before the processing of one transaction is completed due to the delay of the processor, secure space to store two or more transactions in the third storage unit and double It is also possible to perform buffering. In addition, the above-described operation of the storage device including the first to third storage units may be controlled by a control unit (not shown).

4 is a diagram illustrating a configuration example of a burst memory operating as a second stage storage unit in the storage device according to an embodiment of the present invention.

Referring to FIG. 4 , the burst memory 335 includes an input cross bar 3351 , a plurality of memory banks (banks 1 to M-1 ) 3353 , and an output multiplexer 3355 . . The N input ports are connected to the M memory banks 3353 via an input cross bar 3351 , where N<M. That is, the number of memory banks is greater than the number of input ports. Each memory bank in the present embodiment is, for example, have a width W of the _B bit. Each input port is controlled to be connected to a specific memory bank at every moment. And the output port selects and outputs one of the M memory banks at every moment.

In this embodiment, any area of the burst memory 335 may be allocated to a client, and a start address for each client in the memory banks 3353 may be set in the configuration register R1. By changing this setting during operation of the terminal, it is possible to reset according to the operation scenario. Therefore, the total size of the burst memory 335 can be designed based on an operation scenario in which the sum of one burst amount of all clients is maximum, and in other operation scenarios, burst memory 335 is dynamically created between clients through the configuration register R1. The memory 335 may be redistributed. In the present embodiment, such an allocation method of the burst memory 335 can reduce the required area of the memory while securing the space of the memory with the maximum burst size for each client.

5 is a diagram illustrating an example of an access pattern of a burst memory in a storage device according to an embodiment of the present invention.

Referring to FIG. 5 , for example, when a client accesses the burst memory 335 , all memory banks 3353 are sequentially accessed in a horizontally striped pattern. In this case, since one client accesses a specific memory bank only once every M cycles, if it is scheduled in the input crossbar 3351 so that two or more clients do not access two memory banks at a time, a maximum of M clients can be accessed without colliding with each other. You can access the memory bank at the same time. And, since reading data stored in the burst memory 335 is processed in units of one client, the number N of clients writing data to the burst memory 335 must be smaller than the number M of memory banks.

Table 1 below shows an example of assignment of the input cross bar 3351 for each client according to the present embodiment, which shows an example of assignment of a memory bank according to time when, for example, the number of clients is 8 will be.

<Table 1>

As shown in Table 1 above, if eight consecutive clock cycles are defined as eight time slots and allocated in a round-robin manner, scheduling without collision is possible. At this time, when a specific client wants to start data transmission, it may take up to 7 clocks to wait until the allocated time slot, so an input buffer (ie, an input FIFO in FIG. 3 ) that can store data is required for each client. The first-stage storage unit, the input FIFO for each client, serves to store data irregularly generated from each client without loss and transmit it to the burst memory 335 in successive cycles.

6 is a diagram illustrating an area (unit: gate count) of a memory required per bit according to a size of a memory according to an embodiment of the present invention. Here, 1 gate represents the area of a NAND gate having two inputs.

Referring to FIG. 6 , in the case of the smallest size memory (Width 4, Depth 32), the memory area is 3.83 gate/bit, and as the memory size increases, the memory area decreases and the memory area converges to 0.20 gate/bit. . In the example of FIG. 6 , it can be seen that the memory area differs by a maximum of 19 times between memories of different sizes. In addition, it can be seen that when the memory size is larger than a certain size, the memory area rapidly decreases to 0.2~0.3 gate/bit level. Accordingly, it can be seen that configuring the memory banks so that the memory sizes are uniform is more advantageous in terms of reducing the area of the memory, rather than implementing the memory banks having various distributions of memory sizes as in the examples of FIGS. 1A and 1B . Accordingly, in the present embodiment, the memory size of the memory banks is uniformly configured regardless of the amount of data generated for each client.

Meanwhile, in an embodiment of the present invention, each client may transmit additional information in addition to the client data to be transmitted to the destination memory 350 .

7 is a diagram illustrating an example of an interface between a client and a data transfer unit in a storage device according to an embodiment of the present invention.

The example of FIG. 7 shows an example in which control information (ControlInfo) and an interrupter request signal (InterruptReq) are transmitted from the client i 310 to the data transfer unit 330 in addition to the Wi-bit client data (ClientData) through the interface.

Table 2 below shows an example of the control information.

<Table 2>

8 is a timing diagram for explaining a client data transmission operation in a storage device according to an embodiment of the present invention. The timing diagram of FIG. 8 shows an example of transmitting client data using the control information of <Table 2>. For example, in <Table 2>, ContorlInfo[1:0] is "10", in FIG. 8, ContorlInf[1] is "1", and ContorlInf[0] is "0".

When the operation of FIG. 8 is described with reference to FIG. 7 , reference numeral 801 denotes a clock, 803 and 805 denote control information, 807 denote an interrupt request signal, and 809 denote client data. The client i 310 maintains the control information (ControlInfo) as “00” in the standby state. The client i 310 transmits the control information ControlInfo[0] 803, for example, as “1” when starting the first transmission, and transmits a head address at which data storage in the destination memory 350 starts. Thereafter, when the client i 310 transmits the client data 809 , it transmits the control information ControlInfo[1] 805 as “1” to notify the data transfer unit 330 that the client data 809 is valid. Client i 310 transmits control information "11" after one burst transmission is completed. After receiving the control information "11", the data transfer unit 330 confirms that the burst is the end, and operates the eXDMAC 339, which is a DMA controller, to start data transfer to the destination memory 350 . When the client i 310 transmits an interrupt request signal (InterruptReq) 807 as “1” at the end of a specific burst, the data transfer unit 330 generates an interrupt after the transmission of the corresponding burst is completed and corresponds to the processor. Notifies that the client's data transfer has been completed. _{T end} in FIG. 8 with other reference signs _{to start} means the time between one burst and the next.

9 is a diagram illustrating an example of client data stored in a destination memory in a storage device according to an embodiment of the present invention.

Referring to FIG. 9, two base addresses (BA0, BA1) can be designated for each client in the setting register R1 (refer to FIG. 3). If the two base addresses are different, the destination memory 350 is doubled. Buffering can be performed. In fact, each burst stores data from the base address plus the head address (HA0, HA1, ...) transmitted by each client, in which case the data storage unit 350 stores additional information can be stored to facilitate processing of the data by the processor. In FIG. 9, “n+1” indicates a transaction number. The transaction number is used to check whether data transmission of a new transaction is completed without using an interrupt. It is assumed that the transaction number is increased by 1 whenever an interrupt is generated for each client. Instead of performing the interrupt processing, the processor determines whether the transmission of all data has been completed by checking whether the transaction number has been updated, thereby reducing the processing time.

The storage device using the multi-tiered memories (ie, hierarchical-structured memories) according to the embodiment of the present invention is implemented by including sequentially connected first to third-tier storage units. The first stage storage unit may be implemented as FIFO memories using a small flip-flop or memory for each client to store data of each client that operates independently. If the first-stage storage unit is used, data can be stored without losing data during the waiting time until recording can be started in the second-stage storage unit.

In addition, the second stage storage unit stores one or more bursts that occur intensively for each client, but is implemented as a burst memory including a plurality of memory banks that can be shared by a plurality of clients in order to reduce the implementation cost of the storage device. can The plurality of memory banks may have a uniform memory size to reduce a memory area, and may simultaneously read and write client data transmitted from the first storage unit to the plurality of memory banks, and store the third storage unit at the same time. Collision can be prevented when transferring pre-stored data. In addition, the second stage storage unit may dynamically change the memory allocation for each client by changing the location and data amount at which data for each client is stored in the burst memory through software settings (eg, through a setting register). When the configuration of the second stage storage unit is used, the area of the memory can be reduced. In addition, in order to increase the area efficiency of the storage device, it is possible to use the traffic characteristics of data generated by each client.

In addition, the third stage storage unit stores data of a transaction unit, which is a processing unit of the processor, but may store data of one or more transaction amounts for each client. The third stage storage unit may use an external memory or on-chip memory (eg, a memory built into the processor), which has a relatively low implementation cost, and stores data of each client in a specific location of the destination memory. In the method, double buffering can be performed using two or more base addresses. In addition, it is possible to facilitate data processing by the processor by automatically transmitting additional information to a specific location of the third storage unit. The additional information may be various types of information useful for processing other data, such as the transaction number.

According to the above-described embodiment of the present invention, in a communication system in which data generated by a plurality of hardware blocks must be transmitted to a specific memory, a storage device using a shared multi-level memory capable of efficiently processing data of all clients and methods may be provided.

In addition, according to the above-described embodiment of the present invention, a memory access method can be provided in a storage device using memories having a multi-level structure. Through this configuration, the use of a small memory is reduced and large-capacity data is used as a whole by using a memory of a certain size or more. It is possible to improve the area efficiency of the memory. In addition, when the amount of data generated for each client varies according to the operation scenario, the amount of memory allocated to each client can be efficiently reallocated.

Claims (15)

A storage device for processing a plurality of client data, comprising:
a first-stage storage unit for receiving and storing the plurality of client data from a plurality of clients;
a second storage unit receiving the plurality of client data from the first storage unit and storing each of the plurality of client data in a plurality of memory banks shared by the plurality of clients in burst units; and
and a third storage unit for receiving the burst data stored in the burst unit from the second storage unit and storing it in a transaction unit that is a transmission unit for data processing,
The plurality of memory banks are included in the second stage storage,
the number of the plurality of memory banks is greater than the number of the plurality of clients;
When the third-stage storage unit stores the burst data in transaction units, a plurality of base addresses are used to perform double buffering to store the burst data, and
Each of the burst data stored in the second storage unit is transferred to the third storage unit during a time during which a plurality of client data to be stored in the second storage unit in the following order is processed.
The method of claim 1,
The plurality of clients corresponds to a plurality of processors operating independently, and each of the plurality of client data includes different types of data.
The method of claim 1,
The storage device including memories corresponding to each of the plurality of clients, wherein the first storage unit stores each of each of the plurality of client data.
The method of claim 1,
and the first-stage storage unit stores the plurality of client data until the second-stage storage unit can start recording.
The method of claim 1,
The plurality of memory banks have a uniform memory size.
delete delete The method of claim 1,
A storage device in which the location and the amount of data at which the plurality of client data are stored in the plurality of memory banks are changed through software settings.
9. The method of claim 8,
The second stage storage includes a setting register,
The software setting is changed using the setting register.
The method of claim 1,
The memory allocation of the plurality of clients to the plurality of memory banks is dynamically variable.
The method of claim 1,
The third storage unit uses an external memory or an on-chip memory included in the processor.
delete The method of claim 1,
The additional information transmitted to the specific address of the third storage unit is used for data processing by the processor.
delete A method of processing a plurality of client data, comprising:
receiving the plurality of client data from each of the plurality of clients and storing the plurality of client data in memory for each client;
receiving the plurality of client data from the memories for each client and storing each of the plurality of client data in a burst unit in a plurality of memory banks shared by the plurality of clients; and
receiving the burst data stored in the burst unit in the plurality of memory banks and storing the data in a destination memory in a transaction unit, which is a transmission unit for data processing,
the number of the plurality of memory banks is greater than the number of the plurality of clients;
The destination memory performs double buffering to store the burst data using a plurality of base addresses when storing the burst data in transaction units, and
Each of the burst data stored in the plurality of memory banks is transferred to the destination memory during a time during which a plurality of client data to be stored in the plurality of memory banks in the following order is processed.

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