CN116724287A

CN116724287A - Memory control method and memory control device

Info

Publication number: CN116724287A
Application number: CN202180090740.7A
Authority: CN
Inventors: 梁传增; 龙明直; 林祥轩
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-01-25
Filing date: 2021-01-25
Publication date: 2023-09-08
Also published as: WO2022155970A1

Abstract

The application discloses a memory control method and a memory control device, wherein the method comprises the following steps: determining priorities of read commands and write commands cached in the memory controller according to the inlet flow of the memory controller; and sending the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low. The method provided by the application can reduce the average delay of the read command while considering higher bandwidth utilization rate, so as to solve the problem of poor delay performance of the whole memory system when the average delay of the read command is higher.

Description

Memory control method and memory control device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a memory control method and a memory control device.

Background

The memory is also called an internal memory, and is used for temporarily storing operation data in a central processing unit (central processing unit, CPU) and exchanging data with an external memory such as a hard disk. And a memory controller (memory controller) for managing data exchanges from the memory to the CPU. The memory controller may be a separate chip or may be integrated into an internal memory or CPU. The performance of the memory controller directly affects the read-write speed of the CPU to the data in the memory, and two important parameters affecting the performance of the memory controller are: bandwidth utilization and latency. The bandwidth utilization rate refers to a ratio of an interface data transmission speed to a maximum transmission speed of the memory controller in a certain time. The time delay refers to the time interval from receiving a read command or a write command sent by the CPU to feeding back the read command or the write command to the CPU.

Therefore, with the development of computer technology, the transmission speed of the memory is also higher, and the design of the memory controller is also more and more complex to match the bandwidth utilization. The memory controller shown in fig. 1A is designed on the premise of ensuring high bandwidth utilization. Referring to fig. 1A: the method comprises the steps that a read command and a write command are stored in a command queue after entering a memory controller through a command interface, a command scheduling module schedules the commands cached in the command queue as soon as possible based on a greedy algorithm so as to ensure that the memory controller has higher bandwidth utilization rate, the command scheduling module informs a time sequence judging module after scheduling one command, different counters are loaded after the time sequence judging module recognizes the types of the commands so as to ensure that each command meets time sequence parameters during scheduling, after the counter counts, the command scheduling module selects the commands from the command queue to schedule after counting is completed, the write data transmission module is used for receiving write data which are issued by a processor and correspond to the write commands, and when the write commands are sent to a memory, the write data transmission module is used for receiving the read data sent by the memory and sending the read data to the processor.

In practice, when a processor issues a command, it generally issues a write command and a read command randomly, and in order to ensure high bandwidth utilization, the memory controller still uses a greedy algorithm to schedule the command from the command queue. For example: the memory controller will schedule the write command received first to the memory, wait for the write command to continue to schedule the read command to the memory for execution after the memory is finished, which is equivalent to the memory controller continuously scheduling commands from the command queue according to the sequence randomly issued by the processor, the mode generally equally divides the average delay of the read command and the write command, but the read command is more sensitive to delay than the write command in practice. When the average delay of the read command is high, the delay performance of the whole memory system is poor, and the average delay of the read command is too high to be tolerated by the existing memory system. In view of this, it is a problem in the art to reduce the average latency of latency-sensitive read commands while compromising higher bandwidth utilization.

Disclosure of Invention

In view of this, the present application provides a memory control method and a memory control device, based on the inlet flow of a memory controller, when the inlet flow of the memory controller is higher, the read command is prioritized higher than the write command so as to send the read command, and when the inlet flow of the memory controller is lower, a part of buffered write commands are issued, at this time, since the inlet flow of the memory controller is lower, the read command issued by the processor and the write command are fewer, and therefore, the read command blocked by the issued write command is fewer, and therefore, the increase of the read command delay caused by blocking is negligible. In general, compared with the existing command scheduling method, the average delay of the read command is obviously reduced, so that the average delay of the read command can be reduced while higher utilization rate is considered.

In a first aspect, an embodiment of the present application provides a memory control method, which may be applied to a memory controller, and mainly includes the following steps: determining priorities of read commands and write commands cached in the memory controller according to the inlet flow of the memory controller, wherein the inlet flow is the sum of the number of the read commands and the number of the write commands received by the memory controller in unit time; and sending the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low.

In order to solve the problem of poor delay performance of the whole memory system caused by higher average delay of the read command, firstly, the inlet flow of the memory controller needs to be identified, the priority of the read command and the write command cached in the memory controller is determined based on different inlet flows of the memory controller, and the read command and the write command cached in the memory controller are sent to the memory according to the priority of the read command and the write command. Therefore, when the inlet flow is higher, the read command can be sent to the memory faster, so that the memory can be processed as soon as possible, when the inlet flow is lower, the received read command and the write command are fewer, the write command insensitive to delay is sent, and the buffered write command is ensured not to be overstocked too much and the read command blocked by the write command is fewer. In general, among read commands scheduled by a memory controller, the majority of fast scheduling is blocked only for a small fraction.

Next, the present method will be further described:

in one possible implementation, when the ingress traffic of the memory controller meets a set condition, the priority of the read command cached in the memory controller is higher than the priority of the write command cached in the memory controller. By using the method, when the inlet flow is higher, the priority of the read command cached in the memory controller is higher than the priority of the write command cached in the memory controller, so that the low delay of the read command can be ensured when the inlet flow of the memory controller meets the set condition.

In one possible embodiment, the setting conditions include at least one of: the inlet flow of the memory controller is larger than a set threshold; the total number of the write commands cached in the memory controller is not greater than a threshold value of the number of the write commands; the bandwidth utilization of the memory controller is greater than a utilization threshold.

When the total number of the write commands cached in the write command cache queue is not greater than the threshold value of the number of the write commands, the fact that excessive write commands are not accumulated in the memory controller at this time is indicated, and at this time, the priority of the read commands cached in the memory controller is higher than the priority of the write commands cached in the memory controller, and priority scheduling of the read commands needs to be guaranteed preferentially.

The bandwidth utilization rate is the ratio of the current data transmission speed to the maximum data transmission speed of the memory controller, the current data transmission speed is the sum of the speed of sending data corresponding to a read command to the processor by the current memory controller and the speed of sending data corresponding to a write command to the memory, and when the bandwidth utilization rate of the memory controller is greater than the utilization rate threshold value, the entry flow of the memory controller is larger at the moment, and priority scheduling of the read command needs to be guaranteed preferentially.

In one possible implementation, when the ingress traffic of the memory controller does not meet a set condition, the priority of the write command cached in the memory controller is higher than the priority of the read command cached in the memory controller. By using the method, too many write commands are not accumulated in the memory controller, and the delay of the write commands cached in the memory controller is not too large.

In one possible implementation manner, when the entry flow of the memory controller does not meet a set condition, determining a target number according to the entry flow, and selecting a target number of write commands from the write commands cached in the memory controller, where the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller. By using the method, the memory controller does not send excessive write commands to the memory, and the number of the read commands is less because the number of the sent write commands is not large, so that the average delay of the read commands is ensured to be kept at a lower level all the time.

In one possible implementation, when the ingress traffic of the memory controller does not meet the set condition, a target write command is selected from the write commands cached in the memory controller according to the set rule, where the priority of the target write command is higher than the priority of the write command cached in the memory controller. The write command selected from the write commands cached in the memory controller by utilizing the setting rule according to the setting rule has a higher speed compared with the write command selected randomly, and the delay of the read command blocked by the write command can be obviously reduced.

Wherein, the setting rule may include at least one of:

the number of the same memory address set in the selected target write command is smaller than a set number threshold, wherein the memory comprises a plurality of memory spaces, each memory space corresponds to one memory address set, and each write command comprises a memory address;

by utilizing the rule, when the target write command in the write command cache queue is processed in a centralized way, a large number of write commands belonging to the same memory address set can be scheduled, so that the execution efficiency is influenced;

the selected target write command is located in the same memory row, wherein the write command further comprises memory row information, and the memory row corresponding to the write command is determined according to the memory row information contained in the write command.

By utilizing the rule, the selected target write command is located in the same memory row, and the row addresses of the memory rows in the memory addresses corresponding to the write command sent to the memory in a period of time can be ensured to be the same, so that the time for opening the memory rows is saved, and the benefit of performance is achieved.

In one possible embodiment, the method further comprises: and increasing the priority of the first write command, wherein the memory address contained in the first write command cached in the memory controller is the same as the memory address contained in the first read command cached in the memory controller. By adopting the method, the problem that the first read command cannot be executed or is delayed to be executed because the data corresponding to the first read command is not written in the memory after the first read command is sent to the memory can be prevented. After the read command sensitive to the time delay is sent to the memory, the memory can smoothly execute the read command so as to reduce the average time delay of the read command.

Further, in order to increase the execution speed of the read command sensitive to delay, in a possible implementation manner, the method further includes: and taking the data to be written corresponding to the second write command as the data to be read of the second read command, wherein the memory address contained in the second write command cached in the memory controller is the same as the memory address contained in the second read command cached in the memory controller. By adopting the method, the problem that the second read command cannot be executed or is delayed to be executed because the data corresponding to the second read command is not written in the memory after the read command is sent to the memory can be prevented. In addition, the memory controller obtains the read data corresponding to the second read command without processing the second read command by the memory, so that the scheduling speed of the second read command can be increased, and the average delay of the read command can be further reduced.

In one possible embodiment, the method further comprises: and when the total number of the write commands cached in the memory controller is greater than a total number threshold, not caching the write commands. By using the method, excessive write commands in the write command cache queue can be prevented from being cached, and the normal operation of the memory controller can be ensured.

In one possible implementation, sending the read command and the write command cached in the memory controller to the memory includes: according to a first sending period, sending a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period. By using the mode, different command sending periods can be configured according to different memory protocols or different system service scenes, so that the bandwidth of the memory controller is ensured.

In a second aspect, an embodiment of the present application provides a memory control device, where the memory control device may implement the memory control method provided in any one of the first aspects. The technical effects of the corresponding aspects of the second aspect may be referred to the technical effects that may be obtained by the corresponding aspects of the first aspect, and the details will not be repeated.

The memory control device includes: the inlet flow judging module and the command issuing module;

the access flow judging module is used for determining the priority of the read command and the write command cached in the memory controller according to the access flow of the memory controller, wherein the access flow is the sum of the number of the read command and the number of the write command received by the memory controller in unit time;

and the command issuing module is used for sending the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low.

In some possible embodiments, when the ingress traffic of the memory controller satisfies a set condition, the priority of the read command cached in the memory controller is higher than the priority of the write command cached in the memory controller.

In some possible embodiments, the setting conditions include at least one of:

the inlet flow of the memory controller is larger than a set threshold;

the total number of the write commands cached in the memory controller is not greater than a threshold value of the number of the write commands;

the bandwidth utilization of the memory controller is greater than a utilization threshold.

In some possible embodiments, the ingress flow determining module is further configured to determine, when the ingress flow of the memory controller does not meet a set condition, a target number of write commands from the write commands cached in the memory controller, where a priority of the target number of write commands is higher than a priority of the write commands cached in the memory controller.

In some possible implementations, the ingress traffic judgment module is further configured to select, when the ingress traffic of the memory controller does not meet the set condition, a target write command from write commands cached in the memory controller according to the set rule, where the priority of the target write command is higher than the priority of the write command cached in the memory controller.

In some possible embodiments, the setting rule includes at least one of:

In some possible embodiments, the memory control device further includes a priority adjustment module; the priority adjustment module is configured to increase the priority of the first write command, where the memory address included in the first write command cached in the memory controller is the same as the memory address included in the first read command cached in the memory controller.

In some possible embodiments, the memory control device further includes a read data determining module, where the read data determining module is configured to use data to be written corresponding to a second write command as data to be read of a second read command, and a memory address included in the second write command cached in the memory controller is the same as a memory address included in the second read command cached in the memory controller.

In some possible embodiments, the memory control device further includes a write command number determining module, configured to not cache the write commands when the total number of the write commands cached in the memory controller is greater than a total number threshold.

In some possible implementations, the command issuing module is further configured to send, according to a first sending cycle, a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period.

In a third aspect, an embodiment of the present application further provides a processor, where the processor may include a processor core and a memory controller related to the first aspect, where the processor core may send a write command and a read command to the memory controller, and where the memory controller may send the write command and the read command to the memory after receiving the write command and the read command.

In a fourth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a processor, a memory controller, and a memory, where the memory controller on the electronic device is configured to execute the memory control method provided in any one of the first aspects.

In a fifth aspect, embodiments of the present application also provide a computer-readable storage medium having instructions stored therein that, when executed on a memory controller, cause the memory controller to perform the methods of the above aspects.

In a sixth aspect, embodiments of the present application also provide a computer program product comprising instructions that, when run on a memory controller, cause the memory controller to perform the methods of the above aspects.

In a seventh aspect, an embodiment of the present application further provides a chip, where the chip is configured to read a computer program stored in a memory, and when the computer program is executed, the method in each aspect is implemented.

These and other aspects of the application will be more readily apparent from the following description of the embodiments.

Drawings

FIG. 1A is a schematic diagram of a conventional memory controller;

FIG. 1B is a schematic diagram of a memory array and peripheral control circuitry;

FIG. 2 is a schematic diagram of an electronic device;

FIG. 3 is a schematic diagram of a memory control method;

FIG. 4 is a schematic diagram of the inlet flow of the memory controller;

FIG. 5 is a flow chart of determining a target number according to a bandwidth utilization of a memory controller;

FIG. 6 is a flow chart illustrating determining a target number according to the total number of write commands buffered by the memory controller;

FIG. 7 is a schematic diagram of a memory control device;

FIG. 8 is a schematic diagram of an example memory controller.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. The specific method of operation in the method embodiment may also be applied to the device embodiment or the system embodiment. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present application. "and/or", describes an association relationship of an associated object, meaning that there may be three relationships, exemplary, a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.

In the following, some terms related to the embodiments of the present application will be explained for easy understanding by those skilled in the art.

(1) The memory controller (memory controller) is used to manage data exchanges from memory to the processors. It may be a separate chip or integrated into a memory or processor.

(2) The memory, also called internal memory, is used for temporarily storing the operation data in the processor and exchanging data with external memory such as a hard disk. The working principle of the memory is to store charges by using the capacitance of the memory, and whether a binary bit is 1 or 0 is represented by the magnitude of the charges. The repeated arrangement of the plurality of single bit memory cells forms a memory array. The memory array shown in FIG. 1B, plus peripheral control circuitry, constitutes a memory.

(3) Dynamic random access memory heap addresses (dynamic random access memory bank address, BA). Wherein, bank is the meaning of memory space, and a memory can be divided into a plurality of memory spaces, appoints memory space serial number when visiting, just can visit appointed memory space. How many banks are partitioned in a particular memory depends on how many bits of BA address are in the address line. For example, if the BA address is two bits, 4 banks are illustrated; if the BA address is 3 bits, 8 banks are indicated.

(4) A dynamic random access memory heap block group (dynamic random access memory bank group, BG). A memory can be divided into a plurality of grouping bank groups, and each bank group can independently read and write data, so that the internal data throughput is greatly improved, a large amount of data can be read, and the equivalent frequency of the memory is also improved. Illustratively, two or four alternative independent packets are used on the DDR4 architecture.

(5) North bridge (northbridge), the most important component of the motherboard chipset that is the closest chip to the processor on the motherboard, is responsible for interfacing with the processor and controlling memory, and serves to establish a communication interface between the processor and the PCI bus, memory, AGP (accelerated graphics port ), and secondary cache.

(6) Greedy algorithm means that when solving a problem, always the choice that is the best in view of the current situation is made. That is, only locally optimal solutions are made in a sense, without taking into account overall optimality. The greedy algorithm can not obtain the overall optimal solution for all problems, and the key is the selection of greedy strategies, wherein the selected greedy strategies have no aftereffect, namely the previous process of a certain state cannot influence the later state and only relate to the current state.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

In electronic devices (e.g., smartphones, tablets, base stations, smart cameras, controllers for autonomous vehicles, etc.), memory is the basis for operations performed by a processor, which may be coupled to the memory through a memory controller. The memory controller may be connected to the processor or integrated inside the processor.

Fig. 2 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 mainly comprises a processor 21, a memory controller 22 and a memory 23. Those skilled in the art will appreciate that memory controller 22 may be integrated into processor 21 or memory 23 or may be built into the north bridge. Embodiments of the present application are not limited to a particular location of memory controller 22. In the case where the memory controller 22 and the memory 23 are not integrated together, the memory controller 22 and the memory 23 are connected by a memory bus 25.

The processor 21 is a core and a control unit (control unit) of the electronic device 20, and the processor 21 may be a very large scale integrated circuit. An operating system and other software programs are installed in the processor 21 so that the processor 21 can provide access to the memory 23 of the electronic device 20. Those skilled in the art will appreciate that the processor 21 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. The processor 21 may further comprise a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. As integrated circuit processes develop, more and more processor cores (cores) may be integrated into the processor 21. When a plurality of processor cores are integrated in the processor 21, interconnection between the plurality of processor cores may be achieved through a network on chip. It will be appreciated that in practice, the electronic device 20 may also comprise a plurality of processors 21. The embodiment of the application is exemplified by a processor. The number of processors and the number of processor cores in a processor are not limited in embodiments of the application.

In an embodiment of the present application, the memory controller 22 may include a communication interface and a control circuit, and the memory controller 22 may communicate with the processor 21 and the memory 23 through the communication interface. Memory controller 22 may write data to memory 23 or read data from memory 23.

In an embodiment of the present application, the memory 23 may be a memory chip supporting double rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR SDRAM), where DDR SDRAM is generally referred to as DDR, and the memory 23 may also support generation 4 DDR (4 th DDR, DDR 4), such as low power DDR4 (low power DDR4, LPDDR 4). The memory 23 may support a 5th generation DDR (5 th DDR, DDR 5), such as low power DDR5 (low power DDR5, LPDDR 5).

A cache 24 may also be provided in the memory controller 22, the cache 24 being a temporary storage of the electronic device 20 between the processor 21 and the memory 23, the cache 24 being located in the memory controller 22 in the present application. In general, the cache 24 may be comprised of static random access memory (static random access memory, SRAM). The buffer 24 is used for temporarily storing write data sent by the processor 21 to the memory 23, and read data sent by the memory 23 to the processor 21.

In embodiments of the present application, memory bus 25 may include a data bus, a command/address bus, and a read data ready (ready) feedback line. The data bus is used for transmitting data, and the command/address bus is used for transmitting access commands such as read commands, write commands and the like. It should be noted that bidirectional data transfer between the memory controller 22 and the memory 23 can be achieved through the memory bus 25. Illustratively, the memory controller 22 sends write data to the memory 23 by sending a write command to the memory 23, and writes the write data by the memory 23 based on the received write command; the memory controller 22 may also read data from the inside by sending a read command to the memory 23 and based on the received read command by the memory 23 and return the read data to the memory controller 22.

It should be noted that, in the electronic device 20 provided in the embodiment of the present application, in addition to the devices shown in fig. 2, the electronic device 20 may further include a communication interface and other devices such as a magnetic disk as an external memory, which is not limited herein.

In the existing scenario, in order to ensure high bandwidth utilization, the memory controller still adopts a greedy algorithm to schedule commands from the command queue. For example: the memory controller will schedule the write command received first to the memory, wait for the write command to continue to schedule the read command to the memory for execution after the memory is finished, which is equivalent to the memory controller continuously scheduling commands from the command queue according to the sequence randomly issued by the processor, the mode generally equally divides the average delay of the read command and the write command, but the read command is more sensitive to delay than the write command in practice. In an ideal case, after the memory controller receives the read command, the faster the read data can be read from the memory, and the faster the read data can be returned to the processor, and the write command is insensitive to delay, so the memory controller can send the write command and the write data to the memory within a period of time after receiving the write command. In the current scheduling manner, the average delay of the read command is still higher, and when the average delay of the read command is higher, the delay performance of the whole memory system is poor.

In view of the above, the embodiments of the present application provide a memory control method and a memory control device, which can reduce the average delay of a read command while considering a higher bandwidth utilization rate, so as to solve the problem of poor delay performance of the whole memory system when the average delay of the read command is higher. In this embodiment, firstly, the ingress traffic of the memory controller is identified, and for different ingress traffic, the priorities of the read command and the write command cached in the memory controller are determined, and when the ingress traffic is higher, the priority of the cached read command is improved, so that the read command sensitive to delay can be quickly scheduled, and the write command is temporarily cached; when the inlet flow is low, the received read command and the write command are few, the priority of a part of cached write commands is improved, the write commands insensitive to delay are sent, and the read commands blocked by the write commands are few while the cached write commands are not overstocked too much. In general, among read commands scheduled by a memory controller, the majority of fast scheduling is blocked only for a small fraction. Therefore, the method provided by the application can obviously reduce the average delay of the read command while considering higher bandwidth utilization rate.

A memory control method according to an embodiment of the present application is described in detail below with reference to the electronic device 20 shown in fig. 2. Fig. 3 is a flowchart of a memory control method according to an embodiment of the present application, and the method is described in detail below with reference to the flowchart of the method shown in fig. 3.

In order to solve the problem of poor delay performance of the whole memory system caused by higher average delay of the read command, firstly, the inlet flow of the memory controller needs to be identified, and after the priority of the read command and the write command cached in the memory controller is determined based on different inlet flows of the memory controller, the read command and the write command cached in the memory controller are sent to the memory.

Referring to fig. 3, the memory control method provided by the present application includes steps S301 to S303:

s301: the memory controller 22 receives a read command and a write command from the processor 21, and caches the read command and the write command.

The read command is used for reading the read data in the memory 23. Each read command issued by the processor 21 includes an address where the read data in the memory 23 is located, where the read data is data to be read corresponding to the read command; the write commands are used for storing write data into the memory 23, and each write command includes an address where the write data is stored in the memory 23, where the write data is data to be stored corresponding to the write command;

Optionally, after receiving the command sent from the processor 21, the memory controller 22 may buffer the read command to the read command buffer queue and the write command to the write command buffer queue according to the types of the read command and the write command; alternatively, both the read command and the write command may be buffered in the command buffer queue, and the specific buffering manner is not limited herein, and those skilled in the art should know that the detailed description is omitted herein.

In addition, to ensure that too many write commands are not backlogged in the memory controller 22, in some possible embodiments, an upper limit on the number of write commands may be set in the write command cache queue, and when the number of write commands in the write command cache queue reaches the upper limit on the number of write commands, the write commands sent by the processor 21 are no longer stored in the write command cache queue.

S302: the memory controller 22 determines the priority of the read command and the write command cached in the memory controller 22 according to the inlet flow of the memory controller 22;

the inlet flow is the sum of the number of read commands and write commands received by the memory controller in unit time; it is appreciated that the flow of commands issued to the memory controller is not uniform, but rather there are peaks of high inlet flow and valleys of low inlet flow. When the ingress flow of the memory controller 22 is larger, i.e. the peak, it indicates that the number of read commands and write commands received by the memory controller is large, so when the commands are scheduled by greedy algorithm according to the existing method, a large number of write commands will be scheduled without considering the situation of the read commands, the read commands are more sensitive to delay, and the average delay of the read commands is higher, which may result in poor delay performance of the whole memory controller.

The manner of determining the ingress traffic of the memory controller may count the number of commands currently received, for example: the greater the number of commands received, the greater the current ingress traffic, or alternatively, may be determined based on the bandwidth utilization of the memory controller 22, the higher the bandwidth utilization, the higher the ingress traffic. The bandwidth utilization refers to the ratio of the data transmission speed of the memory controller 22 to the maximum transmission speed within a certain period of time.

Optionally, in the embodiment of the present application, when the ingress traffic is large, the memory controller 22 may schedule as many read commands as possible to ensure low latency of the read commands, and when the ingress traffic of the memory controller 22 is small, schedule a portion of write commands to ensure that too many write commands are not backlogged in the memory controller 22, and because the ingress traffic is low, the read commands blocked by the write commands will be too few.

In addition, the read command and the write command received by the memory controller 22 may include an initial priority set by the processor 21, and the memory controller 22 may combine the initial priority and the ingress traffic of the memory controller to comprehensively determine the priorities of the read command and the write command cached in the memory controller. Exemplary: the memory controller 22 receives 4 commands, including two read commands and two write commands (the smaller the priority corresponding number, the higher the priority): the priority of the read command A is 2, the priority of the read command B is 4, the priority of the write command C is 1, and the priority of the write command D is 3, when the current entry traffic is large, the priority of the read command A is reset to 1, the priority of the read command B is reset to 2, the priority of the write command C is reset to 3, and the priority of the write command D is reset to 4, so that the read command is scheduled preferentially, and the low delay of the read command is ensured.

When the priorities of the plurality of read commands are the same, the sending sequence can be determined according to the size of the read data corresponding to the read commands, and in an exemplary embodiment, the read commands with smaller corresponding read data in the read commands can be sent preferentially, and the memory can execute the read commands with faster corresponding read data, so that the average delay of the read commands can be further reduced.

S303: the memory controller 22 sends the read command and the write command cached in the memory controller 22 to the memory 23 according to the order of the priority from high to low.

After the priorities of the read command and the write command in the memory controller 22 are determined according to the ingress traffic of the memory controller 22, the buffered read command and write command in the memory controller are sent to the memory according to the order of the priorities from high to low.

In some possible embodiments, a read data buffer space may be provided in the buffer 24 of the electronic device 20, and the memory controller 22 may buffer the read data in the read data buffer space after receiving the acquired read data sent by the memory. The sending sequence of the read data may be related to the priority of the read command corresponding to the read data, and the read data corresponding to the read command with the higher priority is sent preferentially from the read data cache space.

In other possible embodiments, a write data buffer space may be further provided in the buffer 24 of the electronic device 20, and the memory controller 22 may further receive write data sent by the processor 21, buffer the write data in the write data buffer space, and send, when sending a write command to the memory 23, write data corresponding to the write command to the memory 23 together.

In addition, the write data buffer space may have an upper limit of buffered data, and when the write data occupation space in the write data buffer space reaches the upper limit of the buffered data size, the write data sent by the processor 21 is not buffered in the write data buffer space, and at the same time, the write command sent by the processor 21 is not buffered in the memory controller.

In some possible embodiments, when the ingress traffic of the memory controller 22 satisfies a set condition, the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller.

In order to ensure low latency of the read command, when the set condition is satisfied, the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller 22, so that the read command is preferentially scheduled, thereby reducing the average latency of the read command. The setting condition may be the inlet flow of the memory controller 22, or other parameters that indirectly indicate the inlet flow, such as bandwidth utilization, etc., and those skilled in the art should understand that any parameter that can be used to determine the inlet flow of the current memory controller 22 may be applied to the embodiments of the present application, and will not be described herein.

In some possible embodiments, the setting conditions include at least one of:

the memory controller 22 has an inlet flow greater than a set threshold;

the total number of write commands buffered in the memory controller 22 is not greater than a write command number threshold;

the bandwidth utilization of the memory controller 22 is greater than the utilization threshold.

The total number of write commands buffered in the memory controller 22 may be used to indirectly indicate the ingress flow of the memory controller 22, specifically, when the ingress flow of the memory controller 22 is higher, the priority of the read commands buffered in the memory controller 22 is higher than the priority of the write commands buffered in the memory controller, so each time the processor 21 issues a read command and a write command, the write commands are buffered in the memory controller, and when the total number of buffer stacks of the memory controller 22 is greater than the threshold of the number of write commands, it indicates that the ingress flow of the memory controller 22 is lower at this time. For example, the threshold value of the number of write commands may be preset to 50, and the setting condition is satisfied when the total number of write commands is not more than 50.

The bandwidth utilization of the buffer in the memory controller 22 may also be used to indirectly represent the ingress traffic of the memory controller 22, where the bandwidth utilization is a ratio of a current data transmission speed of the memory controller 22 to a maximum data transmission speed, and the current data transmission speed is a sum of a speed at which the memory controller 22 sends data corresponding to a read command to the processor 21 and a speed at which the memory 23 sends data corresponding to a write command. Referring to the schematic diagram of the inlet flow rate on the memory controller shown in fig. 4, the memory controller 22 may correspondingly set a utilization threshold, and when the bandwidth utilization is greater than the utilization threshold, it indicates that the inlet flow rate of the memory controller 22 is greater at this time, that is, the set condition is satisfied.

In order to prevent excessive write commands from being accumulated in the memory controller 22, in some possible embodiments, when the ingress traffic of the memory controller 22 does not meet a set condition, the priority of the write commands cached in the memory controller 22 is higher than the priority of the read commands cached in the memory controller 22.

Further, in order to ensure that too many write commands are not sent at a time, so that scheduling of more read commands is blocked, when the entry flow of the memory controller does not meet a set condition, determining a target number according to the entry flow, and selecting a target number of write commands from the write commands cached in the memory controller, wherein the priority of the target number of write commands is higher than that of the write commands cached in the memory controller.

Since the number of commands received is small when the ingress traffic is low, the number of read commands blocked by the write command is small, and thus the lower the ingress traffic, the greater the target number.

Specifically, determining the target number may further include the following:

mode one: the memory controller 22 determines the target number according to the bandwidth utilization; the lower the bandwidth utilization, the greater the target number. In this embodiment, the memory controller 22 may first determine the bandwidth utilization and determine the target number corresponding to the bandwidth utilization. Because the sizes of the traffic entering the memory controller 22 for the read command and the write command are not the same, the corresponding target number can be set corresponding to different bandwidth utilization rates.

Fig. 5 is a flowchart illustrating the determination of the target number according to the bandwidth utilization of the memory controller 22, and referring to fig. 5, the above method may include steps S501-S503:

s501: the memory controller 22 determines the bandwidth utilization; the bandwidth utilization rate may be acquired in real time or at regular intervals.

S502: the memory controller 22 determines whether the bandwidth utilization is not greater than the utilization threshold, and when the bandwidth utilization is not greater than the utilization threshold, step S503 is executed. For example, the utilization threshold may be set to 50%, and the target number is determined when the bandwidth utilization is not greater than 50%.

S503: the memory controller 22 determines the target number based on the bandwidth utilization. The lower the bandwidth utilization, the greater the target number. Illustratively, the target number is 10 when the bandwidth utilization of the memory controller is 40%, and the target number is 20 when the bandwidth utilization of the memory controller is 30%.

Mode two: the memory controller 22 determines the target number according to the total number of buffered write commands; the larger the total number of write commands, the larger the target number.

Referring to fig. 6, fig. 6 is a flow chart illustrating the determination of the target number by the memory controller 22 according to the total number of buffered write commands, and the above method may include steps S601-S603:

s601: the memory controller 22 determines the total number of buffered write commands.

S602: the memory controller 22 determines whether the total number of buffered write commands is greater than the write command number threshold, and when the total number of buffered write commands is greater than the write command number threshold, step S603 is performed; for example, the write command number threshold may be set to 40, and the target number is determined when the total number of write commands is greater than 40.

S603: the memory controller 22 determines the target number based on the total number of buffered write commands. For example, a range of values for the total number of write commands may be set, each range of values corresponding to a target number of values. The target number is determined to be 10 when the total number of the write commands is 40-50, and is determined to be 15 when the total number of the write commands is 50-60.

To reduce latency of blocked read commands, a set rule may be used to select a target write command from among the write commands cached in the memory controller 22 to increase the speed at which target write commands are continuously sent. In some possible embodiments, when the ingress traffic of the memory controller 22 does not meet the set condition, a target write command is selected from the write commands cached in the memory controller according to the set rule, where the target write command has a higher priority than the write command cached in the memory controller.

The setting rules can be freely set by a person skilled in the art, the purpose of which is to increase the speed with which the memory 23 continuously processes write commands. Specifically, the write command selected from the write commands cached in the memory controller according to the set rule is continuously executed in the memory 23, which is faster than the randomly selected write command, thereby reducing the delay of the read command blocked by the write command.

In some possible embodiments, the setting rule includes at least one of:

Setting a rule I: the number of the same memory address sets belonging to the selected target write command is smaller than the set number threshold.

It is known that, in the memory, data of the memory is written into a large matrix in units of bits (bits), each CELL is called a CELL, and when the memory executes a read command or a write command, a corresponding row (row) and a corresponding column (column) of the read command or the write command are determined, and then the CELL can be accurately located. The rank array is called a bank of memory chips, also called a logical bank. Because of the memory manufacturing process, the rank array is difficult to be large, so that the memory capacity is generally manufactured by dividing the memory capacity into a plurality of rank arrays, that is, a plurality of logic banks exist in the memory. Therefore, in some memory protocol standards, it may be configured that a plurality of packet logical packet Banks (BG) are divided, and each bank can independently read and write data. For the memory 23, if a large number of write commands belonging to the same bank or the same bank group are processed, the efficiency of executing the commands on the memory 23 may be affected. Thus, it is desirable to avoid having the memory 23 execute commands of the same bank or the same bank group in large amounts for a period of time.

Specifically, in order to avoid an excessive number of write commands belonging to the same memory address set (bank or bank greop) among the target write commands sent to the memory 23, when the memory controller 22 selects a target write command from the write commands cached in the memory controller, it is necessary to first determine the memory address set to which the memory address included in each write command belongs. And selecting the write command belonging to the same memory address set, the number of which is smaller than the set number threshold value, as the target write command according to the memory address set to which the memory address contained in each write command belongs. For example, one or more write commands respectively located in each set of memory addresses may be selected from among the write commands cached in the memory controller, the number of the plurality of write commands being less than a set number threshold.

Setting a second rule: the selected target write command is located in the same memory line.

When the memory 23 processes the write command continuously, if the memory corresponding to the address processed each time is different, the execution speed of the write command is reduced.

If the row addresses of the memory rows in the corresponding memory addresses are all the same write command, the memory 23 can save the time of opening the memory rows, thereby improving the execution speed of the write command.

Therefore, when selecting a write command from the write commands cached in the memory controller, the memory controller 22 first determines whether there is a write command corresponding to the same memory line, and if so, selects a write command corresponding to the same memory line from the write commands cached in the memory controller and sends the write command to the memory 23.

To increase the execution speed of read commands that are delay sensitive, in some possible embodiments, the method may include:

and increasing the priority of the first write command, wherein the memory address contained in the first write command cached in the memory controller is the same as the memory address contained in the first read command cached in the memory controller.

Specifically, after receiving the first read command sent from the processor 21, the memory controller 22 may first determine the memory address corresponding to the first read command; and searching whether a first write command which is the same as the memory address corresponding to the read command exists in the write commands cached in the memory controller according to the memory address corresponding to the first read command. When the first write command with the same memory address of the data corresponding to the read command exists in the write command cache queue, the priority of the first write command is improved, and the processing speed of the first read command is indirectly improved. Specifically, the memory controller 22 may raise the priority of the first write command above the first read command, so that the memory 23 processes the first write command before the first read command is processed, or may raise the priority of the first write command to the highest level, and directly send the first write command to the memory 23 for execution.

In order to further increase the execution speed of the read command sensitive to delay, in other possible embodiments, the method may further comprise:

and taking the data to be written corresponding to the second write command as the data to be read of the second read command, wherein the memory address contained in the second write command cached in the memory controller is the same as the memory address contained in the second read command cached in the memory controller.

Specifically, after receiving a second read command from the processor, according to a memory address corresponding to the second read command, searching whether a second write command with the same memory address as the second read command exists in the write commands cached in the memory controller. When there is a first write command with the same memory address as the data corresponding to the second read command, the memory controller 22 returns the write data corresponding to the second write command as the read data of the second read command to the processor 21, thereby further improving the average delay of the read command.

At present, different memory protocols or different system service scenarios exist, different sending periods need to be configured corresponding to the different memory protocols or the different system service scenarios, the read command and the write command are sent to the memory 23, and in some possible implementations, the sending the read command and the write command cached in the memory controller to the memory includes: according to a first sending period, sending a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period.

Wherein, the memory 23 may support different memory protocols or be in different system service scenarios, and the speeds of processing the read command and the write command by the memory 23 corresponding to the different memory protocols are different, and the memory controller 22 sends the write command cached in the memory controller to the memory 23 according to the first sending cycle; the memory controller 22 sends the read command buffered in the memory controller to the memory in a second sending cycle. The first transmission period and the second transmission period may be the same or different. For example, if the target write command selected based on the setting rule is continuously sent to the memory 23, the interval for issuing the target write command may be shortened to improve the bandwidth utilization of the memory controller. In addition, the first transmission period and the second transmission period may be 0, that is, each read command or write command is transmitted without interval when issued.

In order to solve this problem, in some possible embodiments, the method further includes:

And when the total number of the write commands cached in the memory controller is greater than a total number threshold, not caching the write commands.

Specifically, when the speed of the write command issued by the processor 21 is too high or the number of issued write commands is too high, the memory controller 22 does not cache the received write commands in the memory controller any more, and when the total number of the write commands cached in the memory controller is greater than the total number threshold, the memory controller 22 continues to cache the write commands again.

The embodiment of the application provides a memory control method, which can reduce the average delay of a read command while considering higher bandwidth utilization rate so as to solve the problem of poor delay performance of the whole memory system when the average delay of the read command is higher. The average delay of the read command is reduced in a mode of identifying the inlet flow of the memory controller, and particularly when the inlet flow is higher, the priority of the read command which is determined to be cached is improved, so that the read command which is sensitive to the delay can be quickly scheduled, and the write command is temporarily cached; when the inlet flow is low, the received read command and the write command are few, the write command insensitive to the delay is sent, and the buffered write command is ensured not to be overstocked and the read command blocked by the write command is also few. In general, among read commands scheduled by a memory controller, the majority of fast scheduling is blocked only for a small fraction. In addition, the embodiment of the application can improve the priority of the write commands of the target number, not only ensures that too many write commands are not accumulated in the memory controller, but also ensures that the read commands are not blocked by the write commands for too long. In addition, the priority of the target write command is selected and improved through the set rule, the speed of continuously processing the write command by the memory can be increased, so that the time for blocking the read command by the write command can be reduced.

Referring to fig. 7, a schematic diagram of a memory control device 700 according to an embodiment of the present application is provided, and the functions of each module in the memory control device 700 are described below with reference to fig. 7:

the memory control device 700 includes: an inlet flow judgment module 701 and a command issuing module 702;

the inlet flow judging module 701 is configured to determine priorities of a read command and a write command cached in the memory controller according to an inlet flow of the memory controller, where the inlet flow is a sum of numbers of the read command and the write command received by the memory controller in a unit time;

the command issuing module 702 is configured to send the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low.

In some possible embodiments, the setting conditions include at least one of:

the inlet flow of the memory controller is larger than a set threshold;

In some possible embodiments, the ingress flow determining module 701 is further configured to determine, when the ingress flow of the memory controller does not meet a set condition, a target number of write commands from the write commands cached in the memory controller, where the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.

In some possible embodiments, the ingress traffic judgment module 701 is further configured to select, when the ingress traffic of the memory controller does not meet the set condition, a target write command from the write commands cached in the memory controller according to the set rule, where the priority of the target write command is higher than the priority of the write command cached in the memory controller.

In some possible embodiments, the setting rule includes at least one of:

In some possible embodiments, the memory control device further includes a priority adjustment module 703; the priority adjustment module is configured to increase the priority of the first write command, where the memory address included in the first write command cached in the memory controller is the same as the memory address included in the first read command cached in the memory controller.

In some possible embodiments, the memory control device further includes a read data determining module 704, where the read data determining module 704 is configured to take the data to be written corresponding to the second write command as the data to be read of the second read command, where a memory address included in the second write command cached in the memory controller is the same as a memory address included in the second read command cached in the memory controller.

In some possible embodiments, the memory control device further includes a write command number determining module 705, where the write command number determining module 705 is configured to not cache the write command when the total number of the write commands cached in the memory controller is greater than a total number threshold.

In some possible embodiments, the command issuing module 702 is further configured to send, according to a first sending cycle, a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period.

It should be noted that, in the embodiment of the present application, the division of the modules is merely schematic, and there may be another division manner in actual implementation, and in addition, each functional module in each embodiment of the present application may be integrated in one processing unit, or may exist separately and physically, or two or more modules may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Referring to fig. 8, fig. 8 is an example schematic diagram of a memory controller, and specifically, the memory controller 800 includes the following modules: a read command storage module 801, a write command storage module 802, a command scheduling module 803, a command collision management module 804, a write data storage module 805, and a read data storage module 806.

Specifically, the read command storage module 801 is configured to receive and cache a read command from the processor;

the write command storage module 802 is configured to receive and cache a write command from a processor;

the command scheduling module 803 is configured to send a read command and a write command cached in the memory controller to a memory according to the order of the priority from high to low;

the command conflict management module 804 is configured to determine priorities of a read command and a write command cached in the memory controller according to an entry flow of the memory controller, where the entry flow is a sum of numbers of the read command and the write command received by the memory controller in a unit time;

the write data storage module 805 is configured to store write data corresponding to the write command;

The read data storage module 806 is configured to store read data corresponding to the read command;

In some possible embodiments, the setting conditions include at least one of:

the inlet flow of the memory controller is larger than a set threshold;

In some possible embodiments, the command collision management module 804 is further configured to determine, when the ingress traffic of the memory controller does not meet the set condition, a target number of write commands from the write commands cached in the memory controller, where the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.

In some possible embodiments, the command collision management module 804 is further configured to select, when the ingress traffic of the memory controller does not meet the set condition, a target write command from the write commands cached in the memory controller according to the set rule, where the priority of the target write command is higher than the priority of the write command cached in the memory controller.

In some possible embodiments, the setting rule includes at least one of:

In some possible implementations, the command collision management module 804 is further configured to:

In some possible implementations, the write command storage module 802 is further configured to:

In some possible implementations, the command scheduling module 803 is further configured to:

sending the read command and the write command cached in the memory controller to the memory, wherein the sending comprises the following steps: according to a first sending period, sending a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period.

In some possible embodiments, the memory controller 800 further includes a configuration information storage module 807, where the configuration information storage module 807 is configured to store relevant parameters for determining the ingress traffic, such as the set threshold, the write command number threshold, and the utilization threshold, etc.

In other possible embodiments, the configuration information storage module 807 is further configured to store content of protocol types and the like supported by the memory connected to the memory controller 800.

Further, the command collision management module 804 is configured to:

starting the read command storage module 801 when the read command storage module receives a read command and the write command storage module 802 receives a write command to determine the priority between the read command cached by the read command storage module 801 and the write command cached by the write command storage module 802;

When a command is sent to a memory, the read command storage module 801 is started, and a read command and a write command cached in the memory controller are sent to the memory according to the sequence from high priority to low priority;

the read command storage module 801 is dormant at other times to reduce power consumption of the overall memory controller.

Based on the above embodiments, the present application provides an electronic device, which includes a processor, a memory controller, and a memory, where the memory controller on the electronic device is configured to execute the memory control method provided in the above embodiments.

Based on the above embodiments, the present application also provides a computer-readable storage medium having stored therein a computer program which, when executed by a computer, causes the computer to execute the memory control method provided in the above embodiments.

Based on the above embodiments, the present application further provides a computer program product, which when executed on a computer, causes the computer to execute the memory control method provided in the above embodiments.

Wherein a storage medium may be any available medium that can be accessed by a computer. Taking this as an example but not limited to: the computer readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

Based on the above embodiments, the embodiments of the present application further provide a chip, where the chip is configured to read a computer program stored in a memory, so as to implement the memory control method provided in the above embodiments.

In summary, the memory control method and the memory control device provided by the application can reduce the average delay of the read command while considering higher bandwidth utilization rate, so as to solve the problem of poor delay performance of the whole memory system when the average delay of the read command is higher. The average delay of the read command is reduced in a mode of identifying the inlet flow of the memory controller, when the inlet flow is higher, the priority of the read command which determines the cache is improved, the read command which is sensitive to the delay is ensured to be rapidly scheduled, and the write command is temporarily cached; when the inlet flow is low, the received read command and the write command are few, the write command insensitive to the delay is sent, and the buffered write command is ensured not to be overstocked and the read command blocked by the write command is also few. In general, among read commands scheduled by a memory controller, the majority of fast scheduling is blocked only for a small fraction. In addition, the embodiment of the application can improve the priority of the write commands of the target number, not only ensures that too many write commands are not accumulated in the memory controller, but also ensures that the read commands are not blocked by the write commands for too long. In addition, the priority of the target write command is selected and improved through the set rule, the speed of continuously processing the write command by the memory can be increased, so that the time for blocking the read command by the write command can be reduced. And each module in the memory controller can be selected according to service requirements when the flow of the read command and the write command is not large, so that the circuit cost is low, and the power consumption of the whole system can be reduced.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

A memory control method applied to a memory controller, the method comprising:

determining priorities of read commands and write commands cached in the memory controller according to the inlet flow of the memory controller, wherein the inlet flow is the sum of the number of the read commands and the number of the write commands received by the memory controller in unit time;

and sending the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low.
The method of claim 1, wherein the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller when the ingress traffic of the memory controller satisfies a set condition.
The method of claim 2, wherein the set conditions include at least one of:

the inlet flow of the memory controller is larger than a set threshold;

the total number of the write commands cached in the memory controller is not greater than a threshold value of the number of the write commands;

the bandwidth utilization of the memory controller is greater than a utilization threshold.
A method according to any one of claims 1-3, wherein when the ingress traffic of the memory controller does not meet a set condition, determining a target number according to the ingress traffic, and selecting a target number of write commands from the write commands cached in the memory controller, wherein the target number of write commands has a higher priority than the write commands cached in the memory controller.
A method according to any one of claims 1-3, wherein when the ingress traffic of the memory controller does not meet a set condition, a target write command is selected from the write commands cached in the memory controller according to a set rule, the target write command having a higher priority than the write commands cached in the memory controller.
The method of claim 5, wherein the set rules include at least one of:

the number of the same memory address set in the selected target write command is smaller than a set number threshold, wherein the memory comprises a plurality of memory spaces, each memory space corresponds to one memory address set, and each write command comprises a memory address;

the selected target write command is located in the same memory row, wherein the write command further comprises memory row information, and the memory row corresponding to the write command is determined according to the memory row information contained in the write command.
The method according to any one of claims 1-6, further comprising:

and increasing the priority of the first write command, wherein the memory address contained in the first write command cached in the memory controller is the same as the memory address contained in the first read command cached in the memory controller.
The method according to any one of claims 1-7, further comprising:

and taking the data to be written corresponding to the second write command as the data to be read of the second read command, wherein the memory address contained in the second write command cached in the memory controller is the same as the memory address contained in the second read command cached in the memory controller.
The method according to any one of claims 1-8, further comprising:

and when the total number of the write commands cached in the memory controller is greater than a total number threshold, not caching the write commands.
The method of any of claims 1-9, wherein sending the read command and the write command cached in the memory controller to memory comprises: according to a first sending period, sending a write command cached in the memory controller to a memory; and sending the read command cached in the memory controller to the memory according to a second sending period.
A memory control device, the device comprising: the inlet flow judging module and the command issuing module;

the access flow judging module is used for determining the priority of the read command and the write command cached in the memory controller according to the access flow of the memory controller, wherein the access flow is the sum of the number of the read command and the number of the write command received by the memory controller in unit time;

And the command issuing module is used for sending the read command and the write command cached in the memory controller to the memory according to the order of the priority from high to low.
The apparatus of claim 11, wherein the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller when the ingress traffic of the memory controller satisfies a set condition.
The apparatus of claim 12, wherein the set conditions comprise at least one of:

the inlet flow of the memory controller is larger than a set threshold;

the total number of the write commands cached in the memory controller is not greater than a threshold value of the number of the write commands;

the bandwidth utilization of the memory controller is greater than a utilization threshold.
The apparatus according to any one of claims 11-13, wherein the ingress flow determination module is further configured to determine a target number of write commands from the write commands cached in the memory controller when the ingress flow of the memory controller does not satisfy the set condition, where the target number of write commands has a priority higher than a priority of the write commands cached in the memory controller.
The apparatus according to any one of claims 11-14, wherein the ingress traffic determination module is further configured to select a target write command from among the write commands cached in the memory controller according to a set rule when the ingress traffic of the memory controller does not satisfy a set condition, the target write command having a priority higher than a priority of the write command cached in the memory controller.
The apparatus of claim 15, wherein the set rules comprise at least one of:

the number of the same memory address set in the selected target write command is smaller than a set number threshold, wherein the memory comprises a plurality of memory spaces, each memory space corresponds to one memory address set, and each write command comprises a memory address;

the selected target write command is located in the same memory row, wherein the write command further comprises memory row information, and the memory row corresponding to the write command is determined according to the memory row information contained in the write command.
The apparatus of any of claims 11-16, wherein the memory control apparatus further comprises a priority adjustment module; the priority adjustment module is configured to increase the priority of the first write command, where the memory address included in the first write command cached in the memory controller is the same as the memory address included in the first read command cached in the memory controller.
The apparatus according to any one of claims 11 to 17, wherein the memory control apparatus further comprises a read data determining module, the read data determining module configured to use data to be written corresponding to a second write command as data to be read of a second read command, where a memory address included in the second write command cached in the memory controller is the same as a memory address included in the second read command cached in the memory controller.
The apparatus of any of claims 11-18, wherein the memory control apparatus further comprises a write command number determination module to not cache write commands when a total number of write commands cached in the memory controller is greater than a total number threshold.
The apparatus of any one of claims 11-19, wherein the command issuing module is further configured to send a write command cached in the memory controller to a memory according to a first sending cycle; and sending the read command cached in the memory controller to the memory according to a second sending period.