CN113791892B - Data path arbitration method, data path arbitration device and chip - Google Patents
Data path arbitration method, data path arbitration device and chip Download PDFInfo
- Publication number
- CN113791892B CN113791892B CN202110875046.8A CN202110875046A CN113791892B CN 113791892 B CN113791892 B CN 113791892B CN 202110875046 A CN202110875046 A CN 202110875046A CN 113791892 B CN113791892 B CN 113791892B
- Authority
- CN
- China
- Prior art keywords
- arbitration
- queue
- time slot
- request
- applicant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004590 computer program Methods 0.000 claims description 11
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 230000004044 response Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 238000012163 sequencing technique Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5013—Request control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5021—Priority
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/54—Indexing scheme relating to G06F9/54
- G06F2209/548—Queue
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Bus Control (AREA)
Abstract
The invention belongs to the field of chip design, and provides a data path arbitration method, a data path arbitration device and a chip. The data path arbitration method comprises the following steps: performing first-level arbitration on the request of the applicant according to the request moment of the applicant to obtain result data of the first-level arbitration; and carrying out second-stage arbitration on the result data of the first-stage arbitration according to preset rules. According to the invention, the first-stage arbitration is performed according to the request time of the applicant, and the second-stage arbitration is performed according to the preset rule, so that other arbitration factors aiming at specific application scenes can be introduced through the preset rule, and the requirements of different application scenes can be met.
Description
Technical Field
The present invention relates to the field of chip design, and in particular, to a data path arbitration method, a data path arbitration device, a chip, and a storage medium.
Background
The arbiter is a functional module commonly used in chip (integrated circuit) design, and if there are requests of a plurality of data processing apparatuses for shared resources, it is necessary to arbitrate and select a certain data processing apparatus, and sequentially perform data processing by taking up the shared resources. Various arbiters have different performance and functional goals with respect to the targeted system focus, such as arbitration fairness, system latency, system throughput, implementation complexity, and the like. In some application scenarios, time is required to be used as the first priority of arbitration, and then other weight factors are considered for arbitration. For example, in a debug trace system, various trace messages need to be sent in the corresponding bus system according to the sequence in which trace packets occur; in broadcast cache coherency protocol maintenance for multiprocessor systems, coherency transactions (transactions) should be broadcast in order of occurrence.
The existing time arbiter is realized by the following steps: sampling the applications generated in the same clock period; counting the number of applications in the same clock period, sequencing the applications according to the sequence of the application time, and endowing each application with a queue sequencing value representing the sequence of arrival of the applications; and the arbitration principle of first applying for first permission is realized by comparing the queue ordering values. The method only carries out arbitration according to the application time, other arbitration factors cannot be introduced, and the requirements of different application scenes cannot be met.
In addition, in the existing time arbitration method, in the process of sampling the applications generated in the same clock period, the requests are required to be generated by the change edge (the falling edge or the rising edge) of the application line, continuous requests are not supported, the arbiter can only respond to one applicant (agent, agent or message source) at a time, and other applicant can only wait, so that the blocking or idling of the upper level can be caused, and the overall performance of the system is affected.
Disclosure of Invention
An objective of the present invention is to provide a data path arbitration method and a data path arbitration device, so as to at least solve the problem that the above arbitration method does not support continuous requests.
To achieve the above object, an aspect of the present invention provides a data path arbitration method, including:
Performing first-level arbitration on the request of the applicant according to the request moment of the applicant to obtain result data of the first-level arbitration;
and carrying out second-stage arbitration on the result data of the first-stage arbitration according to preset rules.
Further, the first level arbitration for the request of the applicant according to the request time of the applicant includes:
recording the request time of all the requesters, and caching the data requested by all the requesters;
and carrying out first-level arbitration on the request corresponding to the earliest time in the request time.
Further, the recording the request time of all the requesters and caching the data requested by all the requesters includes: and recording the request time of all the requesters through a queue time slot register, and caching the data requested by all the requesters through a data buffer queue.
Further, one data buffer queue and one queue time slot register correspond to only one applicant; the width of each queue slot register is the sum of the depths of all data buffer queues.
Further, the recording, by the queue time slot register, the request time of all the requesters includes: the request time of the applicant is recorded at the tail of a queue time slot register corresponding to the applicant.
Further, the performing first-stage arbitration on the request corresponding to the earliest time in the request time to obtain the result data of the first-stage arbitration includes: and combining the highest bits of all queue time slot registers to obtain a combined signal, and taking the combined signal as the result data of the first-stage arbitration.
Further, the method further comprises: before recording the request time of the applicant, determining the position of the tail of the queue time slot register;
wherein determining the position of the tail of the queue time slot register comprises:
and performing a first logic operation on the bit value of the current moment of the queue time slot register, and determining the position of the tail of the queue time slot register according to the result of the first logic operation.
Further, the method further comprises: before carrying out first-level arbitration on a request corresponding to the earliest time in request time, determining whether an applicant requests the earliest time recorded by a queue time slot register;
wherein determining whether the applicant requests the earliest time recorded by the queue time slot register comprises: and performing second logic operation on bit values of the earliest moment recorded by all queue time slot registers, and determining whether the earliest moment has an applicant request according to a second logic operation result.
Further, in the case of determining the position of the tail of the queue time slot register:
if no new request exists at the current moment and the history request of the queue time slot register at the current moment is subjected to second-stage arbitration, resetting the highest bit of the queue time slot register or resetting the low bit of the queue time slot register;
and if no new request exists at the current moment and the historical request of the queue time slot register at the current moment finally carries out second-stage arbitration, the low order zero padding of the queue time slot register.
Further, the performing second-level arbitration on the result data of the first-level arbitration according to the preset rule includes:
gating the combination signals of the highest bits of all the queue time slot registers according to a preset rule to obtain gating signals; the strobe signal is used to determine the selected data buffer queue.
Further, the method further comprises:
the data requested by the applicant is read from the selected data buffer queue.
Another aspect of the present invention provides a data path arbitration device, the device comprising:
the first-stage arbitration module is used for carrying out first-stage arbitration on the request of the applicant according to the request moment of the applicant to obtain result data of the first-stage arbitration;
And the second-stage arbitration module is used for carrying out second-stage arbitration on the result data of the first-stage arbitration according to preset rules.
Further, the first level arbitration for the request of the applicant according to the request time of the applicant includes: the first-level arbitration module records the request time of all the requesters, and performs first-level arbitration on the request corresponding to the earliest time in the request time.
Further, the first level arbitration module includes a plurality of queue time slot registers;
and the queue time slot registers are used for recording the request time of all requesters.
Further, the first-level arbitration module records the request time of the applicant at the tail of a queue time slot register corresponding to the applicant.
Further, the performing first-stage arbitration on the request corresponding to the earliest time in the request time to obtain the result data of the first-stage arbitration includes: and the first-stage arbitration module combines the highest bits of all the queue time slot registers to obtain a combined signal, and takes the combined signal as result data of the first-stage arbitration.
Further, the apparatus also includes a plurality of data buffer queues;
the data buffer queues are used for buffering data requested by all requesters.
Further, one data buffer queue and one queue time slot register correspond to only one applicant; the width of each queue slot register is the sum of the depths of all data buffer queues.
Further, the first-stage arbitration module further comprises a queue tail generator;
the queue tail generator is used for performing first logic operation on the bit value of the current moment of the queue time slot register, and determining the position of the queue tail of the queue time slot register according to the result of the first logic operation.
Further, the first level arbitration module further includes a joint queue time slot;
the joint queue time slot is used for carrying out second logic operation on the bit values of the earliest moment recorded by all queue time slot registers, and determining whether the moment has an applicant request according to the result of the second logic operation.
Further, the performing second-level arbitration on the result data of the first-level arbitration according to the preset rule includes:
and the second-stage arbitration module gates the combination signals of the highest bits of all the queue time slot registers according to a preset rule to obtain gating signals.
Further, the apparatus further comprises:
and the arbitration gating module is used for determining a selected data buffer queue according to the gating signal and reading data requested by an applicant from the selected data buffer queue.
The invention also provides a chip which comprises the data path arbitration device or can execute the data path arbitration method.
The invention also provides a chip, which comprises a first-stage arbitration module, a second-stage arbitration module, a data buffer queue and an arbitration gating module;
the first-stage arbitration module is in signal connection with the second-stage arbitration module, the second-stage arbitration module is in signal connection with the arbitration gating module, and the arbitration gating module is in signal connection with the data buffer queue.
The present invention also provides a storage medium having stored thereon computer program instructions which, when executed, implement the data path arbitration method described above.
According to the data path arbitration method, the first-stage arbitration is performed according to the request time of the applicant, and the second-stage arbitration is performed according to the preset rule, so that other arbitration factors aiming at specific application scenes can be introduced through the preset rule, and the requirements of different application scenes can be met.
In addition, the invention carries out first-level arbitration based on the time of the request to select the application at the earliest moment, and then carries out final arbitration through second-level arbitration, thereby being capable of supporting continuous requests. Specifically, the invention records the time of all the applicant requests, simultaneously caches all the data requested by the applicant, supports the continuous request of the same applicant, and can realize the prior application and prior arbitration aiming at the multi-path requests of a plurality of the applicant. Compared with the scheme that each request source can only respond to one request in the prior art, the invention can avoid causing superior congestion or idle running and improve the overall performance of the system.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a method for data path arbitration according to one embodiment of the present invention;
FIG. 2 is a block diagram of a data path arbitration device provided in one embodiment of the present invention;
FIG. 3 is a logic diagram of a tail generator according to one embodiment of the present invention;
FIG. 4 is a logic diagram of a joint queue time slot provided by one embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
FIG. 1 is a flow chart of a data path arbitration method according to an embodiment of the present invention. As shown in fig. 1, the data path arbitration method provided in the embodiment of the present invention includes the following steps:
Step S1, carrying out first-level arbitration on the request of the applicant according to the request moment of the applicant, and obtaining result data of the first-level arbitration.
The applicant is proxy equipment or message source equipment, the applicant (equipment) responds to the operation of a user to generate a request, the request comprises a request time, and the data path arbitration device performs first-level arbitration according to the request time after receiving the request.
In one embodiment, the request time of all the requesters is recorded, and data requested by all the requesters is cached at the same time, and the first-level arbitration is performed on the request at the same earliest time in the request time.
Optionally, the request time of all the requesters is recorded through a queue time slot register, and the data requested by all the requesters is cached through a data buffer queue. One data buffer queue and one queue time slot register correspond to only one applicant, i.e. each applicant corresponds to one dedicated data buffer queue and one dedicated queue time slot register. The width of each queue slot register is the sum of the depths of all data buffer queues.
Time ordering multiple requests at different times for multiple request sources (i.e., proxy devices or message source devices), prior art solutions are such that: when a request appears in a certain request source, all the request sources are pressed into respective data buffer queues at the same time, the request source with the request presses effective data into the data buffer queues, the request source without the request presses invalid marks into the data buffer queues, and the first-in first-out mechanism of the data buffer queues is utilized to realize time sequencing. The disadvantage of the prior art is that the utilization of the data buffer queue is low, and when the valid data bit width to be pushed in each time is relatively wide (e.g. 32 bits), a lot of circuit resources are wasted. According to the embodiment of the invention, effective request data is recorded through the data buffer queue, the time sequence relation (time slot shift ordering mechanism) of the arrival of the request is recorded through the queue time slot register, the aim of time ordering of the data in the multi-path data buffer queue is realized by using fewer resources, and the logic design is simpler.
Taking three requesters (marked as 0, 1 and 2 respectively) as an example, adopting a queue time slot register 0 to record the time of the request of the requester 0, a queue time slot register 1 to record the time of the request of the requester 1 and a queue time slot register 2 to record the time of the request of the requester 2, adopting a data buffer queue 0 to buffer the data of the request of the requester 0, a data buffer queue 1 to buffer the data of the request of the requester 1 and a data buffer queue 2 to buffer the data of the request of the requester 2. When the request of the applicant 0 is received, if the data buffer queue 0 has enough space, the data requested by the applicant 0 is cached, and meanwhile, the moment when the data requested by the applicant 0 is written into the data buffer queue 0 (namely, the moment when the data requested by the applicant 0) is recorded at the tail of the queue time slot register 0. When the request of the applicant 1 is received, if the data buffer queue 1 has enough space, the data requested by the applicant 1 is buffered, and meanwhile, the moment when the data requested by the applicant 1 is written into the data buffer queue 1 (namely, the moment when the data requested by the applicant 1) is recorded at the end of the queue time slot register 1. When the request of the applicant 2 is received, if the data buffer queue 2 has enough space, the data requested by the applicant 2 is buffered, and meanwhile, the moment when the data requested by the applicant 2 is written into the data buffer queue 2 (namely, the moment when the applicant 2 requests) is recorded at the end of the queue time slot register 2. The time instants recorded by the queue time slot register 0, the queue time slot register 1 and the queue time slot register 2 are used as the first priority arbitration standard.
Assuming that the depths of the data buffer queues of three applicants are 1, 2 and 3 respectively, in an extreme case, at most 6 requests at different moments can be filled in the three data buffer queues successively, so that the width of each queue time slot register should be 6, at most 6 requests at different moments can be recorded, and each bit of the queue time slot register records the request state of one time slot. The most significant bit (bit [5 ]) of each queue slot register indicates whether there is a request for arbitration at the earliest time (clock cycle) of the record, "1" indicates there is "0" indicates there is no; the lowest order bit (bit 0) of each queue slot register indicates whether there is an arbitration request at the latest instant of the record; the higher order indicates from the earlier time to the later time in order from the lower order. The combination of the same bits for all queue slot registers indicates that several requesters have issued requests at the same time. That is, each bit of the queue time slot register is ordered in time sequence, a bit identifies whether there is an arbitration request at a certain time, and the value of the earliest bit of the flag is used as the request of the second-stage arbitration. The highest order bits of all queue time slot registers are combined to obtain a combined signal, which is sent to the next level of arbitration as a request signal (i.e., the result data of the first level of arbitration).
In the first level arbitration process, the time of the applicant request is recorded at the tail of a queue time slot register corresponding to the applicant. Before recording the applicant's request time, the position of the tail of the queue time slot register needs to be determined. Specifically, a first logic operation (for example, a "bit and", "bit or" and "bit exclusive-or" operation) is performed on the bit value of the current time of the queue time slot register and the response signal corresponding to each request queue, and the position of the tail of each queue time slot register is determined according to the result of the first logic operation. In the first level arbitration process, before the first level arbitration is performed on the request corresponding to the earliest time in the request time, it is also required to determine whether the applicant requests the earliest time recorded by the queue time slot register. Specifically, a second logic operation (for example, a "bit or" operation) is performed on the bit values of the earliest time recorded in all the queue time slot registers, and whether the earliest time has a request of an applicant is determined according to the second logic operation result.
In the first-stage arbitration process, under the condition of determining the position of the tail of the queue time slot register, if no new request exists at the current moment and the history request of the queue time slot register at the current moment is subjected to second-stage arbitration, resetting the highest bit of the queue time slot register or resetting the low bit of the queue time slot register; and if no new request exists at the current moment and the historical request of the queue time slot register at the current moment finally carries out second-stage arbitration, the low order zero padding of the queue time slot register.
Specifically, the first level of arbitration includes the following cases:
1) In the initial condition, all queue time slot registers are cleared when reset, and no request is required for arbitration.
2) When a new applicant requests at the current moment and the requested data is written into the data buffer queue, the method comprises the following steps: a. the current instant own history request gets a response, but not the last request at this instant: the tail bit of the queue time slot register needs to be set to '1' (record the new request of the present queue), and the highest bit of the queue time slot register is cleared (clear the history request which has been responded by the second-stage arbitration module); the other bits remain unchanged. b. The history requests of other applicant at the current time are responded to, but not the last request at the time: the tail bit of the queue time slot register needs to be set to "1" (record the new request of the present queue); the other bits remain unchanged. c. The history request at the current moment is responded by the second-stage arbitration module, and is the last request at the moment: the queue time slot register is shifted left by one bit, the low order zero padding (the request in the earliest time slot is completely responded by the second level arbitration module, the time slot is cleared, the time slot register is not occupied any more), and the bit at the tail of the queue needs to be set to be 1 (record the new request of the queue). d. No history request at the current time gets the response of the secondary arbiter: the tail bit of the queue time slot register needs to be set to "1" (record the new request of the present queue); the other bits remain unchanged.
3) At the current moment, no new applicant requests exist, but the history request of the current moment is responded by the second-stage arbitration module, which comprises the following cases: a. if the request is not the last request responded by the second-level arbitration module at the moment, the highest bit of the queue time slot register of the applicant needs to be cleared; the other bits keep the value unchanged. b. If it is the last request at this time that was responded to by the second level arbitration module, all applicant's queue slot registers are shifted one bit to the left (low order zero padding).
4) When no new external applicant requests at the current moment, but other applicant requests at the current moment are responded, the following cases are included: a. if not the last request at that time to be responded to by the second level arbitration module, the applicant's queue time slot register remains unchanged. b. If it is the last request at this time that was responded to by the second level arbitration module, all applicant's queue slot registers are shifted one bit to the left (low order zero padding).
5) At the current moment, no new external applicant requests or history requests are responded by the second-stage arbitration module, and the queue time slot register is kept unchanged.
The first level of time-based arbitration does not need to compare queue ordering values, but naturally uses the most significant bits of the queue slot register to represent the earliest arriving application at the same time. The method only needs to distinguish whether a certain clock period is applied or not, does not need to count the application of the same clock period, does not need to generate a queue tail result according to the application count, and has relatively simple logic for realizing time arbitration.
And S2, performing second-level arbitration on the result data of the first-level arbitration according to a preset rule.
And gating the combined signals of the highest bits of all the queue time slot registers according to a preset rule to obtain gating signals. The preset rule may be a priority arbitration rule preset according to a specific application scenario for an applicant, for example, priority arbitration is performed by an application scenario applicant 0 in an application scenario a, priority arbitration is performed by an application scenario applicant 1 in an application scenario B, and priority arbitration is performed by an application scenario applicant 2 in an application scenario C.
According to the data path arbitration method provided by the embodiment of the invention, the first-stage arbitration is performed according to the request time of the applicant, and the second-stage arbitration is performed according to the preset rule, so that other arbitration factors aiming at specific application scenes can be introduced through the preset rule, and the requirements of different application scenes can be met.
The data path arbitration method provided in this embodiment further includes the following steps:
and determining a selected data buffer queue according to the gating signal obtained by the second-stage arbitration, reading data requested by an applicant from the selected data buffer queue, and processing the read data.
According to the data path arbitration method, the first-stage arbitration is carried out based on the request time (the request time of the applicant is used as a first priority arbitration standard) to select the application at the earliest moment, and then the final arbitration is carried out through the second-stage arbitration, so that continuous requests can be supported. Specifically, the invention records the time of all the applicant requests, simultaneously caches all the data requested by the applicant, supports the continuous request of the same applicant, and can realize the prior application and prior arbitration aiming at the multi-path requests of a plurality of the applicant. Compared with the scheme that each request source can only respond to one request in the prior art, the method can avoid causing superior congestion or idle running and improve the overall performance of the system.
Fig. 2 is a block diagram of a data path arbitration device according to an embodiment of the present invention. As shown in fig. 2, the data path arbitration device provided in the embodiment of the present invention includes: the system comprises a first-stage arbitration module, a second-stage arbitration module, a data buffer queue and an arbitration gating module. The first-level arbitration module is used for carrying out first-level arbitration on the request of the applicant according to the request moment of the applicant, and obtaining result data of the first-level arbitration. The second-stage arbitration module is used for carrying out second-stage arbitration on the result data of the first-stage arbitration according to preset rules. The arbitration gating module is used for reading data requested by the applicant from the corresponding data buffer queue according to the result of the second-stage arbitration.
The first-level arbitration module records the request time of all requesters and performs first-level arbitration on the earliest request at the same time in the request time. Further, the first-stage arbitration module includes a plurality of queue time slot registers, and requests of all requesters are recorded through the plurality of queue time slot registers, wherein one queue time slot register corresponds to only one requester. Specifically, the first-stage arbitration module records the moment of the request of the applicant at the tail of the queue time slot register corresponding to the applicant, combines the highest bits of all the queue time slot registers to obtain a combined signal, and uses the combined signal as the result data of the first-stage arbitration.
The data buffer queues are multiple and are used for buffering data requested by all requesters. Wherein, a data buffer queue corresponds to only one applicant, that is, each applicant corresponds to a dedicated data buffer queue and a dedicated queue time slot register. The width of each queue slot register is the sum of the depths of all data buffer queues.
Time ordering a plurality of requests at different moments of a plurality of request sources, the prior art scheme is as follows: when a request occurs to a certain request source, all the request sources are pressed into respective data buffer queues at the same time, the request source with the request is pressed into effective data, the request source without the request is pressed into an invalid mark, and the first-in first-out mechanism of the data buffer queues is utilized to realize time sequencing. The disadvantage of the prior art is that the utilization of the data buffer queue is low, and when the valid data bit width to be pushed in each time is relatively wide (e.g. 32 bits), a lot of circuit resources are wasted. According to the embodiment of the invention, effective request data is recorded through the data buffer queue, the time sequence relation (time slot shift ordering mechanism) of the arrival of the request is recorded through the queue time slot register, the aim of time ordering of the data in the multi-path data buffer queue is realized by using fewer resources, and the logic design is simpler.
As shown in fig. 2, this embodiment takes three requesters (marked as 0, 1, and 2 respectively) as an example, and uses the queue time slot register 0 to record the time when the requester 0 requests, the queue time slot register 1 to record the time when the requester 1 requests, and the queue time slot register 2 to record the time when the requester 2 requests, and uses the data buffer queue 0 to buffer the data requested by the requester 0, the data buffer queue 1 to buffer the data requested by the requester 1, and the data buffer queue 2 to buffer the data requested by the requester 2. When the request of the applicant 0 is received, if the data buffer queue 0 has enough space, the data requested by the applicant 0 is cached, and meanwhile, the moment when the data requested by the applicant 0 is written into the data buffer queue 0 (namely, the moment when the data requested by the applicant 0) is recorded at the tail of the queue time slot register 0. When the request of the applicant 1 is received, if the data buffer queue 1 has enough space, the data requested by the applicant 1 is buffered, and meanwhile, the moment when the data requested by the applicant 1 is written into the data buffer queue 1 (namely, the moment when the data requested by the applicant 1) is recorded at the end of the queue time slot register 1. When the request of the applicant 2 is received, if the data buffer queue 2 has enough space, the data requested by the applicant 2 is buffered, and meanwhile, the moment when the data requested by the applicant 2 is written into the data buffer queue 2 (namely, the moment when the applicant 2 requests) is recorded at the end of the queue time slot register 2. The time instants recorded by the queue time slot register 0, the queue time slot register 1 and the queue time slot register 2 are used as the first priority arbitration standard. And if the requests of a plurality of requesters are received at the same time, writing the requests of all the requesters at the current time into the queue tail of the corresponding queue time slot register. All bits of the queue time slot register in the initial state are 0, and the request states of all requesters at the current moment can be recorded by setting the corresponding bits.
Assuming that the depths of the data buffer queues of three applicants are 1, 2 and 3 respectively, in an extreme case, at most 6 requests at different moments can be filled in the three data buffer queues successively, so that the width of each queue time slot register should be 6, at most 6 requests at different moments can be recorded, and each bit of the queue time slot register records the request state of one time slot. The most significant bit (bit [5 ]) of each queue slot register indicates whether there is a request for arbitration at the earliest time (clock cycle) of the record, "1" indicates there is "0" indicates there is no; the lowest order bit (bit 0) of each queue slot register indicates whether there is an arbitration request at the latest instant of the record; the higher order indicates from the earlier time to the later time in order from the lower order. The combination of the same bits for all queue slot registers indicates that several requesters have issued requests at the same time. That is, each bit of the queue time slot register is ordered in time sequence, a bit identifies whether there is an arbitration request at a certain time, and the value of the earliest bit of the flag is used as the request of the second-stage arbitration. The highest order bits of all queue time slot registers are combined to obtain a combined signal, which is sent to the next level of arbitration as a request signal (i.e., the result data of the first level of arbitration).
In the first level arbitration process, the time of the applicant request needs to be recorded at the end of the queue time slot register corresponding to the applicant. Before recording the request time of the applicant, the position of the tail of the queue time slot register needs to be determined, and whether the earliest time recorded by the queue time slot register has the request of the applicant or not is determined. In this embodiment, the first level arbitration module further includes a queue tail generator and a joint queue time slot. The queue tail generator performs a first logic operation on the bit value of the current moment of the queue time slot register and the response signals corresponding to the request queues, and determines the position of the queue tail of the queue time slot register according to the result of the first logic operation. And the joint queue time slot carries out second logic operation on the bit values of the earliest moment recorded by all queue time slot registers, and determines whether the moment has an applicant request according to the result of the second logic operation.
FIG. 3 is a logic diagram of a tail generator according to one embodiment of the present invention. The queue tail generator records the position of the time slot applied at the next moment by the queue time slot register, and all the queue time slots of the applicant share the same queue tail. The queue tail generator obtains the position of the queue tail through exclusive or operation and shift logic by utilizing the characteristic that the high order of the joint time slot is necessarily continuous to be 1. As shown in fig. 3, considering whether all requests at the earliest time can be processed in the current clock cycle, it is determined whether there is only one request in the current earliest time slot and the request has been received by the next level of arbitration by means of three and one or operation (i.e., the first logical operation). When the current_time_finish signal is high, the last request in the time slot indicating the earliest moment has been responded to, so the tail position of the upcoming write should be "shifted one bit left" operation. The final tail position is indicated by the Tail_Point [6:1] signal, with the non-zero bit indicating where the new request should be written to the corresponding queue slot register. For example, tail_point [6:1] is 6b100000, indicating that the tail position of the queue slot register is [5]; tail_Point [6:1] is 6b001000, indicating that the tail position of the queue slot register is [3].
FIG. 4 is a logic diagram of a joint queue time slot provided by one embodiment of the present invention. As shown in fig. 4, the joint time slot is the result of all queue time slot registers performing a "bit or" operation (i.e., the second logical operation), each bit indicating whether or not an applicant has issued an arbitration request at a corresponding time (time slot). If any applicant has a request at a certain moment, the bit corresponding to the joint queue time slot is '1', otherwise, the bit is '0'. Since the queue slot register records requests sequentially from high to low, the position of the first "0" of the joint slot from the highest indicates the slot position not recorded to any application, and thus the tail position of the queue slot register is the position of the highest "0" bit of the joint slot.
In an optional implementation manner, the second-stage arbitration module gates the highest-order combined signal of all the queue time slot registers according to a preset rule to obtain a gating signal. The preset rule may be a priority arbitration rule preset according to a specific application scenario for an applicant, for example, priority arbitration is performed by an application scenario applicant 0 in an application scenario a, priority arbitration is performed by an application scenario applicant 1 in an application scenario B, and priority arbitration is performed by an application scenario applicant 2 in an application scenario C. The arbitration gating module determines a selected data buffer queue according to the gating signal of the second-stage arbitration module, and reads data requested by an applicant from the selected data buffer queue for processing.
According to the data path arbitration device provided by the embodiment of the invention, the first-stage arbitration is performed according to the request time of the applicant, and the second-stage arbitration is performed according to the preset rule, so that other arbitration factors aiming at specific application scenes can be introduced through the preset rule, and the requirements of different application scenes can be met.
In this embodiment, the specific operation of the first level arbitration module is as follows:
1) In the initial condition, all queue time slot registers are cleared when reset, and no request is required for arbitration.
2) When a new applicant requests at the current time and the requested data is written into the data buffer queue (represented by a signal push_i), the following cases are included: a. the current instant own history request gets a response, but not the last request at this instant: the bit in the queue time slot register indicated by Tail_Point [6:1] (i.e., the position of the tail of the queue) needs to be set to "1" (record the new request for this queue); the most significant bit [5] clears (clears the history request that has been responded to by the second level arbitration module); the other bits remain unchanged. b. The history requests of other applicant at the current time are responded to, but not the last request at the time: the bits in the queue time slot register indicated by Tail_Point [6:1] need to be set to "1" (record the new request for this queue); the other bits remain unchanged. c. The history request at the current moment is responded by the second-stage arbitration module, and is the last request at the moment: the queue slot register is shifted left by one bit, the low order zero padding (the request in the earliest slot has been fully responded to by the second level arbitration module, this slot is cleared, the slot register is no longer occupied), and then the bit indicated by Tail_Point [6:1] needs to be set to "1" (record the new request for this queue). d. No history request at the current time gets the response of the secondary arbiter: the bits in the queue time slot register indicated by Tail_Point [6:1] need to be set to "1" (record the new request for this queue); the other bits remain unchanged.
3) At the current moment, no new applicant requests exist, but the history request of the current moment is responded by the second-stage arbitration module, which comprises the following cases: a. if the request is not the last request responded by the second-level arbitration module at the moment, the highest bit of the queue time slot register of the applicant needs to be cleared; the other bits keep the value unchanged. b. If it is the last request at this time that was responded to by the second level arbitration module, all applicant's queue slot registers are shifted one bit to the left (low order zero padding).
4) When no new external applicant requests at the current moment, but other applicant requests at the current moment are responded, the following cases are included: a. if not the last request at that time to be responded to by the second level arbitration module, the applicant's queue time slot register remains unchanged. b. If it is the last request at this time that was responded to by the second level arbitration module, all applicant's queue slot registers are shifted one bit to the left (low order zero padding).
5) At the current moment, no new external applicant requests or history requests are responded by the second-stage arbitration module, and the queue time slot register is kept unchanged.
The data path arbitration device of the present embodiment performs first-stage arbitration to select the application at the earliest time based on the request time, and then performs final arbitration by second-stage arbitration, so that continuous requests can be supported. The invention records the time of all the applicant requests through the queue time slot register, simultaneously caches the data of all the applicant requests through the data buffer queue, supports the continuous request of the same applicant, and can realize the prior application and prior arbitration for the multi-path requests of a plurality of the applicant. Compared with the scheme that each request source can only respond to one request in the prior art, the device can avoid causing superior congestion or idle running, and improves the overall performance of the system.
The data path arbitration device adopts a structure completely different from the prior arbiter, the arbitration device does not need to compare queue ordering values, and the highest bit of a queue time slot register is used for naturally representing the application of the same time of earliest arrival. Each applicant can continuously send requests, write the requested data into the corresponding data buffer queue, record the writing time through the queue time slot register, realize the first-stage arbitration based on time, and then select the request with highest priority by the second-stage arbitration module (which can be the arbitration mode suitable for application scenes). The device can be suitable for different application scenes.
The embodiment of the invention also provides a chip which comprises the data path arbitration device or can execute the data path arbitration method.
The embodiment of the invention also provides a chip which comprises a first-stage arbitration module, a second-stage arbitration module, a data buffer queue and an arbitration gating module. The first-stage arbitration module is in signal connection with the second-stage arbitration module, the second-stage arbitration module is in signal connection with the arbitration gating module, and the arbitration gating module is in signal connection with the data buffer queue. The signal transmission process and implementation principle between the modules of the chip are described above, and are not repeated here.
The embodiment of the invention also provides a storage medium, on which computer program instructions are stored, the computer program instructions, when executed, implement the data path arbitration method.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.
Claims (19)
1. A method of data path arbitration, the method comprising:
performing first-level arbitration on the request of the applicant according to the request moment of the applicant to obtain result data of the first-level arbitration;
performing second-stage arbitration on the result data of the first-stage arbitration according to preset rules;
The first-stage arbitration for the request of the applicant according to the request time of the applicant comprises the following steps:
recording the request time of all requesters through a plurality of queue time slot registers, and caching the data requested by all requesters through a plurality of data buffer queues;
and combining the highest bits of all queue time slot registers to obtain a combined signal, and taking the combined signal as the result data of the first-stage arbitration.
2. The method of claim 1, wherein one data buffer queue and one queue time slot register correspond to only one applicant;
the width of each queue slot register is the sum of the depths of all data buffer queues.
3. The method of claim 1, wherein the recording request time of all requesters by a plurality of queue time slot registers comprises:
the request time of the applicant is recorded at the tail of a queue time slot register corresponding to the applicant.
4. A data path arbitration method according to claim 3, wherein the method further comprises:
before recording the request time of the applicant, determining the position of the tail of the queue time slot register;
Wherein determining the position of the tail of the queue time slot register comprises:
and performing a first logic operation on the bit value of the current moment of the queue time slot register, and determining the position of the tail of the queue time slot register according to the result of the first logic operation.
5. The data path arbitration method of claim 4, wherein the method further comprises:
before carrying out first-level arbitration on a request corresponding to the earliest time in request time, determining whether an applicant requests the earliest time recorded by a queue time slot register;
wherein determining whether the applicant requests the earliest time recorded by the queue time slot register comprises:
and performing second logic operation on bit values of the earliest moment recorded by all queue time slot registers, and determining whether the earliest moment has an applicant request according to a second logic operation result.
6. The data path arbitration method according to claim 4, wherein in the case of determining the position of the tail of the queue time slot register:
if no new request exists at the current moment and the history request of the queue time slot register at the current moment is subjected to second-stage arbitration, resetting the highest bit of the queue time slot register or resetting the low bit of the queue time slot register;
And if no new request exists at the current moment and the historical request of the queue time slot register at the current moment finally carries out second-stage arbitration, the low order zero padding of the queue time slot register.
7. The method of claim 1, wherein performing the second level arbitration on the result data of the first level arbitration according to the preset rule comprises:
gating the combination signals of the highest bits of all the queue time slot registers according to a preset rule to obtain gating signals; the strobe signal is used to determine the selected data buffer queue.
8. The data path arbitration method of claim 7, wherein the method further comprises:
the data requested by the applicant is read from the selected data buffer queue.
9. A data path arbitration device, the device comprising:
the first-stage arbitration module is used for carrying out first-stage arbitration on the request of the applicant according to the request moment of the applicant to obtain result data of the first-stage arbitration;
the second-stage arbitration module is used for carrying out second-stage arbitration on the result data of the first-stage arbitration according to preset rules;
the first-stage arbitration module comprises a plurality of queue time slot registers, the request moments of all requesters are recorded through the plurality of queue time slot registers, the highest bits of all queue time slot registers are combined to obtain a combined signal, and the combined signal is used as result data of first-stage arbitration.
10. The data path arbitration device of claim 9, wherein the first level arbitration module records the request time of the applicant at the end of the queue time slot register corresponding to the applicant.
11. The data path arbitration device of claim 9, wherein the device further comprises a plurality of data buffer queues;
the data buffer queues are used for buffering data requested by all requesters.
12. The data path arbitration device of claim 11, wherein one data buffer queue and one queue time slot register correspond to only one applicant;
the width of each queue slot register is the sum of the depths of all data buffer queues.
13. The datapath arbitration device of claim 10, wherein the first stage arbitration module further comprises a queue tail generator;
the queue tail generator is used for performing first logic operation on the bit value of the current moment of the queue time slot register, and determining the position of the queue tail of the queue time slot register according to the result of the first logic operation.
14. The datapath arbitration device of claim 13, wherein the first stage arbitration module further comprises a joint queue time slot;
The joint queue time slot is used for carrying out second logic operation on the bit values of the earliest moment recorded by all queue time slot registers, and determining whether the moment has an applicant request according to the result of the second logic operation.
15. The data path arbitration device according to claim 9, wherein the performing the second level arbitration on the result data of the first level arbitration according to the preset rule includes:
and the second-stage arbitration module gates the combination signals of the highest bits of all the queue time slot registers according to a preset rule to obtain gating signals.
16. The data path arbitration device of claim 15, wherein the device further comprises:
and the arbitration gating module is used for determining a selected data buffer queue according to the gating signal and reading data requested by an applicant from the selected data buffer queue.
17. A chip, characterized in that it comprises a data path arbitration device according to any of claims 9-16 or is capable of performing the data path arbitration method according to any of claims 1-8.
18. The chip is characterized by comprising a first-stage arbitration module, a second-stage arbitration module, a data buffer queue and an arbitration gating module;
The first-stage arbitration module is in signal connection with the second-stage arbitration module, the second-stage arbitration module is in signal connection with the arbitration gating module, and the arbitration gating module is in signal connection with the data buffer queue;
the first-stage arbitration module comprises a plurality of queue time slot registers, the request moments of all requesters are recorded through the plurality of queue time slot registers, the highest bits of all queue time slot registers are combined to obtain a combined signal, and the combined signal is used as result data of first-stage arbitration;
and the second-stage arbitration module performs second-stage arbitration on the result data of the first-stage arbitration according to preset rules.
19. A storage medium having stored thereon computer program instructions, which when executed implement the data path arbitration method of any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110875046.8A CN113791892B (en) | 2021-07-30 | 2021-07-30 | Data path arbitration method, data path arbitration device and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110875046.8A CN113791892B (en) | 2021-07-30 | 2021-07-30 | Data path arbitration method, data path arbitration device and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113791892A CN113791892A (en) | 2021-12-14 |
| CN113791892B true CN113791892B (en) | 2024-03-26 |
Family
ID=78877081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110875046.8A Active CN113791892B (en) | 2021-07-30 | 2021-07-30 | Data path arbitration method, data path arbitration device and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113791892B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115469804B (en) * | 2022-08-30 | 2023-07-28 | 中科驭数（北京）科技有限公司 | NVMe multi-queue arbitration method and device |
| CN117312199B (en) * | 2023-11-30 | 2024-03-08 | 杭州海康威视数字技术股份有限公司 | Multi-port access arbitration method, device, equipment and storage medium |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4473880A (en) * | 1982-01-26 | 1984-09-25 | Intel Corporation | Arbitration means for controlling access to a bus shared by a number of modules |
| US5371893A (en) * | 1991-12-27 | 1994-12-06 | International Business Machines Corporation | Look-ahead priority arbitration system and method |
| US5832278A (en) * | 1997-02-26 | 1998-11-03 | Advanced Micro Devices, Inc. | Cascaded round robin request selection method and apparatus |
| CN1479542A (en) * | 2002-08-30 | 2004-03-03 | 深圳市中兴通讯股份有限公司上海第二 | Fair bus arbitration method and arbitration device |
| US7054330B1 (en) * | 2001-09-07 | 2006-05-30 | Chou Norman C | Mask-based round robin arbitration |
| CN101344871A (en) * | 2008-08-20 | 2009-01-14 | 北京中星微电子有限公司 | Bus arbitration unit for guaranteeing access sequence and its implementing method |
| CN105718394A (en) * | 2016-01-25 | 2016-06-29 | 东南大学 | On-chip cache memory access interface of coarse-grained reconfigurable system and access method thereof |
| JP2017162431A (en) * | 2016-03-04 | 2017-09-14 | キヤノン株式会社 | Memory control device and imaging device |
| CN107728953A (en) * | 2017-11-03 | 2018-02-23 | 记忆科技(深圳)有限公司 | A kind of method for lifting solid state hard disc mixing readwrite performance |
| CN111711574A (en) * | 2020-06-29 | 2020-09-25 | 中国人民解放军国防科技大学 | Ultra-high order single-cycle message scheduling method and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004099995A2 (en) * | 2003-05-09 | 2004-11-18 | Koninklijke Philips Electronics N.V. | Hierarchical memory access via pipelining |
| WO2006045216A1 (en) * | 2004-10-28 | 2006-05-04 | Magima Digital Information Co., Ltd. | An arbitrator and its arbitration method |
-
2021
- 2021-07-30 CN CN202110875046.8A patent/CN113791892B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4473880A (en) * | 1982-01-26 | 1984-09-25 | Intel Corporation | Arbitration means for controlling access to a bus shared by a number of modules |
| US5371893A (en) * | 1991-12-27 | 1994-12-06 | International Business Machines Corporation | Look-ahead priority arbitration system and method |
| US5832278A (en) * | 1997-02-26 | 1998-11-03 | Advanced Micro Devices, Inc. | Cascaded round robin request selection method and apparatus |
| US7054330B1 (en) * | 2001-09-07 | 2006-05-30 | Chou Norman C | Mask-based round robin arbitration |
| CN1479542A (en) * | 2002-08-30 | 2004-03-03 | 深圳市中兴通讯股份有限公司上海第二 | Fair bus arbitration method and arbitration device |
| CN101344871A (en) * | 2008-08-20 | 2009-01-14 | 北京中星微电子有限公司 | Bus arbitration unit for guaranteeing access sequence and its implementing method |
| CN105718394A (en) * | 2016-01-25 | 2016-06-29 | 东南大学 | On-chip cache memory access interface of coarse-grained reconfigurable system and access method thereof |
| JP2017162431A (en) * | 2016-03-04 | 2017-09-14 | キヤノン株式会社 | Memory control device and imaging device |
| CN107728953A (en) * | 2017-11-03 | 2018-02-23 | 记忆科技(深圳)有限公司 | A kind of method for lifting solid state hard disc mixing readwrite performance |
| CN111711574A (en) * | 2020-06-29 | 2020-09-25 | 中国人民解放军国防科技大学 | Ultra-high order single-cycle message scheduling method and device |
Non-Patent Citations (3)
| Title |
|---|
| Concurrent Multiresource Arbiter: Design and Applications;Stanislavs Golubcovs et.al;《IEEE Transactions on Computers》;第62卷(第1期);31–44 * |
| MACRON: The NoC-Based Many-Core Parallel Processing Platform and Its Applications in 4G Communication Systems;Xiang Ling et.al;《2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing》;387-403 * |
| 光互连网络中资源预留的多级光互连仲裁机制;翦杰等;《 国防科技大学学报》;第38卷(第5期);39-44 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113791892A (en) | 2021-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113791892B (en) | Data path arbitration method, data path arbitration device and chip | |
| KR100932359B1 (en) | Switch matrix system with multiple bus arbitrations per cycle with high frequency mediator | |
| KR101557090B1 (en) | Hierarchical memory arbitration technique for disparate sources | |
| JP5576030B2 (en) | System for reordering data responses | |
| US20090172284A1 (en) | Method and apparatus for monitor and mwait in a distributed cache architecture | |
| JP2011150397A (en) | Bus arbitration device | |
| JP2006331426A (en) | Interconnect logic for data processing apparatus | |
| JP2008046997A (en) | Arbitration circuit, crossbar, request selection method, and information processor | |
| US7490219B2 (en) | Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors | |
| US20120047299A1 (en) | Data transfer device, method of transferring data, and image forming apparatus | |
| CN115361336B (en) | Router with cache, route switching network system, chip and routing method | |
| US20150160720A1 (en) | Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline | |
| US6467032B1 (en) | Controlled reissue delay of memory requests to reduce shared memory address contention | |
| JP5650441B2 (en) | Arithmetic device, cache device, control method thereof, and computer program | |
| KR20130075139A (en) | Semiconductor chip and control method of memory, and recording medium storing program for executing method of the same in computer | |
| JP2005092630A (en) | Memory control unit and control method | |
| US7774513B2 (en) | DMA circuit and computer system | |
| US9892067B2 (en) | Multiprocessor cache buffer management | |
| US8667233B2 (en) | Competition testing device | |
| JP2002024007A (en) | Processor system | |
| US11886367B2 (en) | Arbitration allocating requests during backpressure | |
| JP3570877B2 (en) | Information processing equipment | |
| CN109413122B (en) | Data processing method, network processor and computer storage medium | |
| US7975086B1 (en) | Apparatus for real-time arbitration between masters and requestors and method for operating the same | |
| KR20050004157A (en) | Data transfer unit with support for multiple coherency granules |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |