CN115469804B

CN115469804B - NVMe multi-queue arbitration method and device

Info

Publication number: CN115469804B
Application number: CN202211058202.2A
Authority: CN
Inventors: 张宇军; 段宗胜; 孟繁毅
Original assignee: Yusur Technology Co ltd
Current assignee: Yusur Technology Co ltd
Priority date: 2022-08-30
Filing date: 2022-08-30
Publication date: 2023-07-28
Anticipated expiration: 2042-08-30
Also published as: CN115469804A

Abstract

The application provides an NVMe multi-queue arbitration method and device, wherein the method comprises the following steps: the host updates the tail pointer information corresponding to the tail pointer of any NVMe queue to perform independent record except the RAM; and carrying out arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are independently recorded, so as to obtain a corresponding NVMe multi-queue arbitration result. According to the method and the device, invalid arbitration in the process of queue arbitration of the NVMe controller can be avoided, a plurality of scheduling periods can be saved, and the arbitration efficiency of the NVMe controller for a plurality of queues is effectively improved.

Description

NVMe multi-queue arbitration method and device

Technical Field

The application relates to the technical field of computers, in particular to an NVMe multi-queue arbitration method and device.

Background

The interface standard NVMe (Non Volatile Memory Host Controller Interface Specification) protocol of the nonvolatile memory host controller adopts a multi-queue mode to improve the parallelism of Input/Output IO (Input/Output), the queues of NVMe are divided into a commit queue SQ (Submission Queue), and a completion queue CQ (Completion Queue) is a circular queue. The specific queue pattern is shown in fig. 1, where each queue has two sets of registers, a head pointer and a tail pointer (also called a head doorbell and a tail doorbell). In the initial state, the head pointer and the tail pointer are both 0, when a host computer has a storage command, the NVMe command is filled into the SQ, the corresponding tail pointer is updated, and the NVMe controller can judge whether the queue is empty and full or not through the head pointer maintained by the NVMe controller and the tail pointer updated by the host computer.

Currently, in the conventional queue arbitration mode of the NVMe controller, when the NVMe queue uses RR for arbitration, the flow is as shown in fig. 2, assuming that all queues are used (all queues are created and then participate in arbitration, but the host may not send a command), the queue for each arbitration uses a queue, in the arbitrated result, if there is no command in the queue, it is an invalid arbitration or invalid scheduling), the head pointer and the tail pointer of the first queue (the 0 th queue is a management command and does not participate in arbitration) are read first, whether the phase difference is 0 or not is judged to be 0, if the phase difference is not 0 indicates that there is a command in the queue, a request for reading the NVMe command is sent, the head pointer and the tail pointer of the next queue are read sequentially, and the steps are continuously executed, in this case, no matter whether there is a command in the queue, the head pointer and the tail pointer are read first and then judged, and thus the invalid arbitration result is a lotThe method comprises the steps of carrying out a first treatment on the surface of the The worst result is: if only the first and last queues have commands, the arbitration method for reading the head pointer and the tail pointer wastes (64K-2) arbitration cycles because the NVMe protocol supports at most 64K queues. Even if the doorbell register storage is optimized and the packets are stored (i.e., the 64K queues are divided into n groups), the worst results will be wastedThere is still an invalid schedule for each arbitration cycle, thereby affecting the queue arbitration efficiency of the NVMe controller.

Disclosure of Invention

In view of this, embodiments of the present application provide an NVMe multi-queue arbitration method and apparatus to obviate or mitigate one or more disadvantages in the prior art.

One aspect of the present application provides an NVMe multi-queue arbitration method, including:

the host updates the tail pointer information corresponding to the tail pointer of any NVMe queue to perform independent record except the RAM;

and carrying out arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are independently recorded, so as to obtain a corresponding NVMe multi-queue arbitration result.

In some embodiments of the present application, further comprising:

and reading head pointer information and tail pointer information of the corresponding NVMe queue from the RAM according to the arbitration result, and updating an arbitration request of the corresponding NVMe queue according to the difference value between the head pointer information and the tail pointer information.

In some embodiments of the present application, the updating, by the host, the tail pointer information corresponding to the tail pointer of any NVMe queue, each of which is independently recorded except for the RAM, includes:

when the host updates the tail pointer information corresponding to the tail pointer of any NVMe queue to the local RAM, the tail pointer information is also stored to the local FIFO queue.

In some embodiments of the present application, before the arbitration processing is performed on the arbitration request of the NVMe queue corresponding to each of the tail pointer information recorded independently, the method includes:

and periodically judging whether the FIFO queue is not empty, if so, reading all the current tail pointer information in the FIFO queue, and determining arbitration requests of NVMe queues corresponding to the tail pointer information respectively.

In some embodiments of the present application, the arbitrating the arbitration request of the NVMe queue corresponding to each of the tail pointer information recorded independently includes:

and carrying out parallel arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are independently recorded, and outputting corresponding arbitration results.

In some embodiments of the present application, before the updating, by the host, the tail pointer information corresponding to the tail pointer of any NVMe queue, each of the tail pointer information is independently recorded except for the RAM, the method further includes:

after the host fills the NVMe command into the corresponding NVMe queue and updates the tail pointer of the NVMe queue, receiving corresponding tail pointer information;

and storing the tail pointer information into a local RAM.

Another aspect of the present application provides an NVMe multi-queue arbitration device, including:

the independent recording module is used for independently recording the tail pointer information corresponding to the tail pointer of any NVMe queue updated by the host except the RAM;

and the arbitration processing module is used for performing arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are recorded independently, so as to obtain a corresponding NVMe multi-queue arbitration result.

In some embodiments of the present application, further comprising:

and the checking and updating module is used for reading the head pointer information and the tail pointer information of the corresponding NVMe queue from the RAM according to the arbitration result, and updating the arbitration request of the corresponding NVMe queue according to the difference value between the head pointer information and the tail pointer information.

In another aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the NVMe multi-queue arbitration method when executing the computer program.

Another aspect of the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the NVMe multi-queue arbitration method.

According to the NVMe multi-queue arbitration method, the host is updated with the tail pointer information corresponding to the tail pointer of any NVMe queue, and independent records except the RAM are carried out; arbitration processing is carried out on the arbitration requests of the NVMe queues corresponding to the tail pointer information which is recorded independently, so that corresponding NVMe multi-queue arbitration results are obtained; by updating the tail pointer of the independent record except the RAM, the queue participating in arbitration each time is a queue with commands, so that the result of arbitration each time of the NVMe controller is meaningful and invalid scheduling is not generated; the method and the device fundamentally solve the problems of more invalid arbitration, low efficiency and the like in the process of queue arbitration of the NVMe controller, can save (64K-2) scheduling periods to the maximum, and effectively improve the arbitration efficiency of the NVMe controller for multiple queues.

Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

It will be appreciated by those skilled in the art that the objects and advantages that can be achieved with the present application are not limited to the above-detailed description, and that the above and other objects that can be achieved with the present application will be more clearly understood from the following detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this application. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. Corresponding parts in the drawings may be exaggerated, i.e. made larger relative to other parts in an exemplary device actually manufactured according to the present application, for convenience in showing and describing some parts of the present application. In the drawings:

fig. 1 is an exemplary diagram of an NVMe queuing mechanism.

Fig. 2 is an exemplary schematic diagram of NVMe hardware detecting whether there is a command in the queue.

Fig. 3 is a general flow chart of an NVMe multi-queue arbitration method according to an embodiment of the present application.

Fig. 4 is a schematic flow chart of an NVMe multi-queue arbitration method according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of an NVMe multi-queue arbitration device according to another embodiment of the present application.

Fig. 6 is a schematic structural diagram of an NVMe multi-queue arbitration device according to another embodiment of the present application.

Fig. 7 is an exemplary schematic diagram of an NVMe controller for implementing the NVMe multi-queue arbitration method provided in the application example of the present application.

Fig. 8 is an exemplary schematic diagram of 2K queue RR arbitration provided in the application example of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the embodiments and the accompanying drawings. The exemplary embodiments of the present application and their descriptions are used herein to explain the present application, but are not intended to be limiting of the present application.

It should be noted here that, in order to avoid obscuring the present application due to unnecessary details, only structures and/or processing steps closely related to the solution according to the present application are shown in the drawings, while other details not greatly related to the present application are omitted.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.

It is also noted herein that the term "coupled" may refer to not only a direct connection, but also an indirect connection in which an intermediate is present, unless otherwise specified.

Hereinafter, embodiments of the present application will be described with reference to the drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

The inventor finds that the existing queue arbitration mode of the NVMe controller has invalid scheduling when designing the queue arbitration method of the NVMe controller, so that the problem of influencing the queue arbitration efficiency of the NVMe controller is solved, and the problem is worsened along with the increase of the number of queues supported by the NVMe controller. As can be seen from the NVMe queue mechanism, each time there is a command in the queue, the host updates the tail-gate bell of the queue, and based on this, the inventor considers: if the updated tail gate bell information is recorded, the arbitration update request is carried out according to the updated tail gate bell information, so that the result of each arbitration is meaningful, invalid scheduling cannot be generated, and the problems of more invalid arbitration, low efficiency and the like in the process of queue arbitration of the NVMe controller are fundamentally solved.

Therefore, through a great deal of research and verification, the application designs an NVMe multi-queue arbitration method, namely a multi-queue (K-level) fast arbitration method based on an NVMe doorbell update mechanism, which can solve (overcome) the problem that a great deal of invalid scheduling exists when an NVMe controller arbitrates a large-scale queue, so that each scheduling can be effectively scheduled, and further, the application reliability and the service life of the NVMe controller can be effectively improved.

The following examples are provided to illustrate the invention in more detail.

Based on this, the embodiment of the application provides an NVMe multi-queue arbitration method, referring to fig. 3, which may be implemented by an NVMe controller, specifically includes the following contents:

step 100: and updating the tail pointer information corresponding to the tail pointer of any NVMe queue by the host computer, and independently recording the tail pointer information except the RAM.

It will be appreciated that each time the host fills the SQ queue with NVMe commands and updates the tail doorbell, the NVMe controller stores all the updated tail pointer register information in the random access memory RAM (Random Access Memory), as well as the updated queue tail pointer information this time in other independent store queues.

Step 200: and carrying out arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are independently recorded, so as to obtain a corresponding NVMe multi-queue arbitration result.

In step 200, an existing arbitration module Arbiter of the NVMe controller may be used to perform arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information recorded independently, so as to obtain and output a corresponding NVMe multi-queue arbitration result.

As can be seen from the above description, in the method for arbitrating multiple NVMe queues provided in the embodiments of the present application, by updating the tail pointer of the independent record except the RAM, the queue involved in the arbitration each time is the queue with the command, so that the result of each arbitration of the NVMe controller is meaningful, and no invalid scheduling is generated; the method and the device fundamentally solve the problems of more invalid arbitration, low efficiency and the like in the process of queue arbitration of the NVMe controller, can save (64K-2) scheduling periods to the maximum, and effectively improve the arbitration efficiency of the NVMe controller for multiple queues.

In order to further ensure reliability and effectiveness of the NVMe multi-queue arbitration, in the method for NVMe multi-queue arbitration provided in the embodiment of the present application, referring to fig. 4, step 200 in the method for NVMe multi-queue arbitration further specifically includes the following:

step 300: and reading head pointer information and tail pointer information of the corresponding NVMe queue from the RAM according to the arbitration result, and updating an arbitration request of the corresponding NVMe queue according to the difference value between the head pointer information and the tail pointer information.

Specifically, the arbitration result notification Check update module check_and_update reads head-tail pointer information from the register RAM, judges the difference value, if many commands in the queue cannot be executed at one time, updates the register head pointer in the RAM, updates the corresponding queue request bit in the Arbiter module, and still sets 1 to participate in the next arbitration; if all the execution can be completed, the register head pointer in the RAM is updated, the corresponding queue request position in the Arbiter module is updated to be 0, the next arbitration is not participated, and the command in each queue is ensured not to be lost.

As can be seen from the above description, in the NVMe multi-queue arbitration method provided in the embodiments of the present application, the queue arbitration request is updated by checking the difference value of the head pointer and the tail pointer of the queue; the command of each queue is not lost, so that the reliability and the effectiveness of NVMe multi-queue arbitration can be further ensured on the basis of improving the arbitration efficiency of the NVMe controller for the multi-queue.

In order to further improve the arbitration efficiency of the NVMe controller for multiple queues, in an NVMe multiple queue arbitration method provided in the embodiment of the present application, referring to fig. 4, step 100 in the NVMe multiple queue arbitration method specifically includes the following steps:

step 110: when the host updates the tail pointer information corresponding to the tail pointer of any NVMe queue to the local RAM, the tail pointer information is also stored to the local FIFO queue.

It will be appreciated that each time the host fills the SQ queue with NVMe commands and updates the tail doorbell, the NVMe stores all the updated tail pointer register information in the ram RAM (Random Access Memory), and at the same time, stores the last updated tail pointer information in the fifo FIFO (First Input First Output) queue.

As can be seen from the above description, in the method for arbitrating multiple queues of NVMe provided in the embodiments of the present application, the queue participating in arbitration is the queue with command each time by updating the FIFO record tail pointer; compared with the prior queue participating in arbitration which is a created queue, the prior queue participating in arbitration is an effective queue, and each queue participating in arbitration is ordered, so that invalid scheduling is not generated, and the maximum scheduling period can be saved by 64K-2.

In order to improve the validity and efficiency of reading all the current tail pointer information in the FIFO queue, in the method for NVMe multi-queue arbitration provided in the embodiment of the present application, referring to fig. 4, the following is specifically included between step 100 and step 200 in the method for NVMe multi-queue arbitration:

step 120: and periodically judging whether the FIFO queue is not empty, if so, reading all the current tail pointer information in the FIFO queue, and determining arbitration requests of NVMe queues corresponding to the tail pointer information respectively.

Specifically, when the FIFO is not empty, the Arbiter module Arbiter takes the corresponding tail pointer information and sets the request of the corresponding queue to 1.

As can be seen from the above description, according to the NVMe multi-queue arbitration method provided by the embodiment of the present application, by periodically determining whether the FIFO queue is not empty, if yes, reading all the current tail pointer information in the FIFO queue, so that the validity and efficiency of reading all the current tail pointer information in the FIFO queue can be effectively improved, and further the validity of the arbitration process can be further improved.

In order to further improve the arbitration efficiency of the NVMe controller for multiple queues, in an embodiment of the present application, referring to fig. 4, step 200 in the NVMe multiple queue arbitration method further specifically includes the following:

step 210: and carrying out parallel arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information which are independently recorded, and outputting corresponding arbitration results.

Specifically, the arbitration module Arbiter arbitrates all the requests in parallel, and the arbitration result informs the Check update module check_and_update.

For example: the scheduling of the queue requests in the Arbiter module adopts a grouping parallel scheduling method, taking 2K queues as an example, and each group of parallel arbitrates 32 queues into 64 groups, and the parallel scheduling is adopted among the groups, two 32 requests are arbitrated in parallel, and the last stage is two-out-of-one arbitration.

As can be seen from the above description, according to the method for arbitrating multiple NVMe queues provided in the embodiments of the present application, the arbitration efficiency of the NVMe controller for multiple queues can be further improved by performing parallel arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information respectively recorded independently.

In order to further ensure the reliability and effectiveness of the internal arbitration of the NVMe controller, in an embodiment of the present application, referring to fig. 4, the following are further specifically included before step 100 in the method for NVMe multi-queue arbitration:

step 010: after the host fills the NVMe command into the corresponding NVMe queue and updates the tail pointer of the NVMe queue, receiving corresponding tail pointer information;

step 020: and storing the tail pointer information into a local RAM.

As can be seen from the above description, the method for arbitrating multiple NVMe queues according to the embodiments of the present application stores the tail pointer information into the local RAM before the tail pointer information is recorded independently, so as to improve reliability and comprehensiveness of reading the head pointer information and the tail pointer information of the corresponding NVMe queues from the RAM, and further ensure reliability and effectiveness of internal arbitration of the NVMe controller.

From the software aspect, the present application further provides an NVMe multi-queue arbitration device for executing all or part of the NVMe multi-queue arbitration method, referring to fig. 5, the NVMe multi-queue arbitration device specifically includes the following contents:

the independent recording module 10 is used for independently recording the tail pointer information corresponding to the tail pointer of any NVMe queue updated by the host except the RAM;

and the arbitration processing module 20 is configured to perform arbitration processing on the arbitration requests of the NVMe queues corresponding to the tail pointer information recorded independently, so as to obtain corresponding NVMe multi-queue arbitration results.

The embodiment of the NVMe multi-queue arbitration device provided in the present application may be specifically used to execute the processing flow of the embodiment of the NVMe multi-queue arbitration method in the above embodiment, and the functions thereof are not described herein again, and may refer to the detailed description of the embodiment of the NVMe multi-queue arbitration method.

The part of the NVMe multi-queue arbitration device for performing the NVMe multi-queue arbitration can be executed in the server, and in another practical application situation, all operations can be completed in the client device. Specifically, the selection may be made according to the processing capability of the client device, and restrictions of the use scenario of the user. The present application is not limited in this regard. If all operations are completed in the client device, the client device may further include a processor for specific processing of NVMe multi-queue arbitration.

The client device may have a communication module (i.e. a communication unit) and may be connected to a remote server in a communication manner, so as to implement data transmission with the server. The server may include a server on the side of the task scheduling center, and in other implementations may include a server of an intermediate platform, such as a server of a third party server platform having a communication link with the task scheduling center server. The server may include a single computer device, a server cluster formed by a plurality of servers, or a server structure of a distributed device.

Any suitable network protocol may be used for communication between the server and the client device, including those not yet developed at the filing date of this application. The network protocols may include, for example, TCP/IP protocol, UDP/IP protocol, HTTP protocol, HTTPS protocol, etc. Of course, the network protocol may also include, for example, RPC protocol (Remote Procedure Call Protocol ), REST protocol (Representational State Transfer, representational state transfer protocol), etc. used above the above-described protocol.

As can be seen from the above description, the NVMe multi-queue arbitration device provided in the embodiments of the present application updates the tail pointer of the independent record except the RAM, so that the queue involved in arbitration each time is a queue with a command, so that the result of arbitration each time of the NVMe controller is meaningful, and invalid scheduling is not generated; the method and the device fundamentally solve the problems of more invalid arbitration, low efficiency and the like in the process of queue arbitration of the NVMe controller, can save (64K-2) scheduling periods to the maximum, and effectively improve the arbitration efficiency of the NVMe controller for multiple queues.

In order to further ensure reliability and effectiveness of the NVMe multi-queue arbitration, in an embodiment of the present application, referring to fig. 6, the NVMe multi-queue arbitration device further specifically includes the following:

As can be seen from the above description, the NVMe multi-queue arbitration device provided in the embodiments of the present application updates the queue arbitration request by checking the difference between the head pointer and the tail pointer of the queue; the command of each queue is not lost, so that the reliability and the effectiveness of NVMe multi-queue arbitration can be further ensured on the basis of improving the arbitration efficiency of the NVMe controller for the multi-queue.

To further illustrate the present solution, the present application further provides a specific application example of an NVMe controller for implementing an NVMe multi-queue arbitration method, where the overall hardware structure of the NVMe controller is shown in fig. 7, each time the host fills the NVMe command into the SQ queue and updates the tail doorbell, the NVMe stores register information of all updated tail pointers into the random access memory RAM (Random Access Memory), and simultaneously stores the updated queue tail pointer information into the fifo FIFO (First Input First Output) queue. When the FIFO is not empty, the arbitration module Arbiter takes corresponding tail pointer information, sets the request of the corresponding queue to 1, performs parallel arbitration on all the requests of the queues in the module, notifies an arbitration result to Check an update module check_and_update, reads the head and tail pointer information from the register RAM, judges the difference value, if a plurality of commands in the queue cannot be executed at one time, updates the register head pointer in the RAM, updates the request bit of the corresponding queue in the Arbiter module, and still sets 1 to participate in the next arbitration; if all the execution can be completed, the register head pointer in the RAM is updated, the corresponding queue request position in the Arbiter module is updated to be 0, the next arbitration is not participated, and the command in each queue is ensured not to be lost.

In the Arbiter module, a method of packet parallel scheduling is adopted for scheduling queue requests, as shown in fig. 8, taking 2K queues as an example, each group of parallel arbitrates 32 queues, and is divided into 64 groups, parallel scheduling is adopted among the groups, two 32-request parallel arbitrates are adopted, and the last stage is two-out-of-one arbitration, wherein 32MUX1 represents that one queue with a request is selected from the 32 queues at the same time, and 2MUX1 represents that one queue with a request is selected from the 2 queues.

In summary, in the application example of the present application, the FIFO records the update of the tail pointer, so that the queue participating in arbitration each time is the queue with commands; the arbitration result is significant; updating the queue arbitration request by checking the difference value of the head pointer and the tail pointer of the queue; so that each queue command will not be lost.

According to the application example, by adding the FIFO to record the actions of the tail pointer (tail doorbell) of the queue updated by the host at each time, compared with the fact that the queue participating in arbitration before is the created queue, the queue participating in arbitration now is the effective queue, each queue participating in arbitration is ordered, invalid scheduling cannot be generated, and the maximum scheduling period can be saved by 64K-2.

The embodiment of the application also provides an electronic device (i.e., an electronic device), which may include a processor, a memory, a receiver, and a transmitter, where the processor is configured to execute the NVMe multi-queue arbitration method mentioned in the foregoing embodiment, and the processor and the memory may be connected by a bus or other manners, for example, through a bus connection. The receiver may be connected to the processor, memory, by wire or wirelessly. The electronic device may receive real-time motion data from a sensor in the wireless multimedia sensor network and receive an original video sequence from the video acquisition device.

The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be any other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

The memory, as a non-transitory computer readable storage medium, may be used to store a non-transitory software program, a non-transitory computer executable program, and a module, such as program instructions/modules corresponding to the NVMe multi-queue arbitration method in the embodiments of the present application. The processor executes various functional applications and data processing of the processor by running non-transitory software programs, instructions and modules stored in the memory, that is, implements the NVMe multi-queue arbitration method in the above method embodiments.

The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory may optionally include memory located remotely from the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The one or more modules are stored in the memory that, when executed by the processor, perform the NVMe multi-queue arbitration method of an embodiment.

In some embodiments of the present application, the user equipment may include a processor, a memory, and a transceiver unit, where the transceiver unit may include a receiver and a transmitter, and the processor, the memory, the receiver, and the transmitter may be connected by a bus system, the memory storing computer instructions, and the processor executing the computer instructions stored in the memory to control the transceiver unit to transmit and receive signals.

As an implementation manner, the functions of the receiver and the transmitter in the present application may be considered to be implemented by a transceiver circuit or a dedicated chip for transceiver, and the processor may be considered to be implemented by a dedicated processing chip, a processing circuit or a general-purpose chip.

As another implementation manner, a manner of using a general-purpose computer may be considered to implement the server provided in the embodiments of the present application. I.e. program code for implementing the functions of the processor, the receiver and the transmitter are stored in the memory, and the general purpose processor implements the functions of the processor, the receiver and the transmitter by executing the code in the memory.

The embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the aforementioned NVMe multi-queue arbitration method. The computer readable storage medium may be a tangible storage medium such as Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, floppy disks, hard disk, a removable memory disk, a CD-ROM, or any other form of storage medium known in the art.

Those of ordinary skill in the art will appreciate that the various illustrative components, systems, and methods described in connection with the embodiments disclosed herein can be implemented as hardware, software, or a combination of both. The particular implementation is hardware or software dependent on the specific application of the solution and the design constraints. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave.

It should be clear that the present application is not limited to the particular arrangements and processes described above and illustrated in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions, or change the order between steps, after appreciating the spirit of the present application.

The features described and/or illustrated in this application for one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.

The foregoing description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the embodiment of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An NVMe multi-queue arbitration method, comprising:

storing the tail pointer information into a local RAM;

when the NVMe controller is used for storing tail pointer information corresponding to the tail pointer of any NVMe queue updated by the host into the local RAM, the tail pointer information is also stored into the local FIFO queue;

periodically judging whether the FIFO queue is not empty, if so, reading all current tail pointer information in the FIFO queue, and determining arbitration requests of NVMe queues corresponding to the tail pointer information respectively;

the arbitration module of the NVMe controller is adopted to perform parallel arbitration processing on the arbitration requests of the NVMe queues corresponding to the independently recorded tail pointer information respectively in a grouping parallel scheduling mode, and the second-choice arbitration is performed at the last stage to obtain a corresponding NVMe multi-queue arbitration result and inform the checking and updating module of the NVMe controller, so that the checking and updating module reads the head and tail pointer information from the RAM and judges the difference value, if the command in the queue can not be completely executed at one time, the register head pointer in the RAM is updated, the corresponding queue request position in the arbitration module is still 1, and the next arbitration is participated; if the command in the queue can be executed at one time, after the register head pointer in the RAM is updated, the corresponding queue request position in the arbitration module is 0 and does not participate in the next arbitration, so as to ensure that the command in each queue is not lost.

2. An NVMe multi-queue arbitration device, characterized in that the NVMe multi-queue arbitration device is configured to perform the following:

storing the tail pointer information into a local RAM;

the NVMe multi-queue arbitration device comprises:

the independent recording module is used for storing the tail pointer information corresponding to the tail pointer of any NVMe queue updated by the host into the local RAM by adopting the NVMe controller, and storing the tail pointer information into the local FIFO queue;

the NVMe multi-queue arbitration device is further configured to perform the following:

the NVMe multi-queue arbitration device further includes:

the arbitration processing module is used for carrying out parallel arbitration processing on the arbitration requests of the NVMe queues corresponding to the independently recorded tail pointer information respectively in a grouping parallel scheduling mode by adopting the arbitration module of the NVMe controller, carrying out one-by-one arbitration at the last stage to obtain a corresponding NVMe multi-queue arbitration result and notifying an inspection updating module of the NVMe controller so that the inspection updating module reads the head and tail pointer information from the RAM and judges the difference value, and if the command in the queue can not be executed at one time, updating the register head pointer in the RAM and setting the corresponding queue request bit in the arbitration module to be 1 to participate in next arbitration; if the command in the queue can be executed at one time, after the register head pointer in the RAM is updated, the corresponding queue request position in the arbitration module is 0 and does not participate in the next arbitration, so as to ensure that the command in each queue is not lost.

3. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the NVMe multi-queue arbitration method of claim 1 when the computer program is executed by the processor.

4. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the NVMe multi-queue arbitration method of claim 1.