JPH08274615A - Signal transmission line control method and semiconductor integrated circuit device for control of signal transmission line - Google Patents

Abstract

PURPOSE: To attain the fast transition of signals on a signal transmission line, etc., of a system bus. CONSTITUTION: In an arbitration cycle mode of a bus arbiter 10, the output of an open collector gate 19 is set at a low level in response to the acknowledge signals 15 and 16. At the same time, a pull-down resistor 18 and also a resistance 20 are connected to a signal transmission line 17 of a system bus., If the line 17 is set at a high level right before an arbitration cycle, the voltage of the line 17 suddenly drops down almost to its threshold level by the function of the resistor 20. As no current flows through the resistor 20 in an operating state of a driver, the resistance value of the resistor 20 can be reduced satisfactorily smaller than the resistor 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to address / data lines in a system bus of a computer system, such as
TECHNICAL FIELD The present invention relates to a technique for accelerating signal transition when a certain driver operates after all the drivers are in a high impedance state in a signal transmission path driven by a three-state driver or the like.

[0002]

2. Description of the Related Art A signal transmission line driven by a three-state driver is generally connected with pull-up / pull-down resistors in order to regulate the voltage of the signal transmission line during the high impedance state of the driver. .

The resistance value of the pull-up / pull-down resistor is
The current flowing when the driver drives the signal transmission path is selected so as not to exceed the rating of the low level output current I0L or the high level output current I0H of the driver. When a current exceeding the rating of I0L or I0H flows during driving of the driver, the life of the driver is shortened, and in the worst case, element destruction of the driver is caused. The final steady-state voltage value of the signal transmission line when the high impedance state of the driver continues is 0 for the pull-up resistor and 0 for the pull-up resistor.
Generally, it is set to V, but the final steady voltage may be set to another voltage value by the resistance voltage division.

[0004]

The constant of the pull-up / pull-down resistor is selected to have a high resistance value so as not to exceed the I0L rating and the I0H rating of the driver. Therefore, it takes time for the signal transition immediately after the high impedance state period. There is a problem of this. This will be further described by taking address / data lines in a synchronous system bus adopted in a computer system as an example. However, the present invention is generally applicable to a signal transmission line driven by a three-state driver.

Since a plurality of I / O devices are usually connected in a synchronous system bus of a computer system, a bus arbiter arbitrates a bus right request from each I / O device. Bus arbiter has I / O
In the period from when the device releases the bus right until it receives a bus right request from a certain I / O device and gives the bus right to it (an arbitration cycle), all I
The address / data line driver of the / O device is in a high impedance state.

During the arbitration cycle, all the drivers are in a high impedance state, so that the signal transmission path gradually changes from the voltage value immediately before the arbitration cycle toward a certain final steady voltage value. The speed of this change is determined by the time constant of the signal transmission line, but the pull-up / pull-down resistance is selected to have a high resistance value as described above, so that the voltage change of the signal transmission line is slow. In a system bus that is becoming faster, the voltage of the signal transmission line does not change up to the final steady voltage value in a short arbitration cycle of about 1 to 2 clock cycles, and the signal voltage immediately before the arbitration cycle is on the signal transmission line. Will remain. This causes a delay in determining the signal voltage in the bus cycle immediately after the arbitration cycle.

For example, if the signal voltage of the cycle immediately before the arbitration cycle is high level ("1"),
During the arbitration cycle, the voltage of the signal transmission line is maintained at a substantially high level even in the case of the pull-down resistor, so the signal voltage must be set to the low level (“0”) in the bus cycle immediately after this arbitration cycle. At times, the signal amplitude substantially changes from the high level to the low level, and it takes time to determine the signal voltage.

An object of the present invention is to speed up signal transition immediately after a period in which all drivers are in a high impedance state in a signal transmission line driven by three-state drivers such as address / data lines in a system bus. Is to try.

Another object of the present invention is to provide a semiconductor integrated circuit device for easily realizing high speed operation of a system bus having a bus free period such as an arbitration cycle.

[0010]

According to the invention of claim 1, in a signal transmission line driven by a three-state driver or the like, all of the drivers detect a period in a high impedance state, and all the drivers are in a high impedance state. It is characterized in that a current for accelerating a voltage change to a specific voltage value is caused to flow through the signal transmission path through the resistance element or the like during the state period.

According to the second aspect of the invention, in a bus having a bus-free period such as an arbitration cycle in which all drivers for driving a signal transmission line are in a high impedance state, the bus-free period is detected, and the bus-free period is detected. It is characterized in that a current for accelerating a voltage change to a specific voltage value is passed through a signal transmission path of the bus through a resistance element or the like.

According to the third aspect of the present invention, the bus-free information input pin, the signal transmission line connecting pin of the bus, and the bus-free information input from the bus-free information input pin are used.
A circuit section that detects a bus-free period such as an arbitration cycle in which all drivers for driving a signal transmission line of a bus are in a high-impedance state and energizes a resistance element connected to the signal transmission line connection pin during the bus-free period And a semiconductor integrated circuit that supplies a current for accelerating a voltage change to a specific voltage value to a signal transmission line of a bus connected to the signal transmission line connection pin through the resistance element during a bus-free period. Characterized by the device.

[0013]

In the method of the present invention as defined in claim 1 or 2, the driving drivers are all in a high impedance state during a period in which a current for accelerating the voltage change is supplied to the signal transmission path.
Unlike when the driver is operating, a large acceleration current exceeding the driver current rating can be passed. Therefore, it becomes possible to rapidly change the voltage of the signal transmission path to a voltage value at which the signal transition after the high impedance state period, for example, the signal transition in the bus cycle immediately after the bus arbitration cycle becomes a high speed. .

According to the semiconductor integrated device of the third aspect, for example, the address / data line of the system bus to which the I / O bus is connected is connected to the signal transmission line connecting pin,
By simply inputting a bus acknowledge signal, etc., in response to a bus right request from the I / O device to the pin for inputting the bus-free information, the voltage of the signal transmission line is changed to the next bus cycle during the bus-free period such as the arbitration cycle. The system bus can be easily speeded up by rapidly changing to a voltage value that enables high-speed signal transition at.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic circuit diagram showing an embodiment of the present invention applied to a system bus. In FIG. 1, reference numeral 17 is a signal transmission line in the address / data line of the system bus. Although a plurality of signal transmission paths actually exist, only one signal transmission path among them is shown as a representative in order to simplify the drawing. The other signal transmission paths have the same configuration.

Reference numerals 11 and 12 are I / O units, and have three-state drivers 21 and 22 for driving the signal transmission path 17 of the system bus. When the I / O units 11 and 12 become bus masters and want to monopolize the system bus, the bus request signals 13 and 14 (REQ)
1, REQ2) to request the bus right from the bus arbiter 10.

The bus arbiter 10 arbitrates the bus right, selects one of the I / O units issuing the bus request signal, and responds to the bus acknowledge signal 1
5 or 16 (ACK1 or ACK2) is output to notify the bus right grant. I / O unit 11 with bus right
Alternatively, 12 starts the data transfer cycle after asserting the bus acknowledge signal.

Reference numeral 18 is a pull-down resistor of the signal transmission path 17 of the system bus. The resistance value of the pull-down resistor 18 is selected so that the current value of the driver that drives the signal transmission path 17 during driving does not exceed its I0H rating, and is 6.8 KΩ in this example.

Reference numeral 19 is an open collector gate for detecting the bus free period of the system bus by an acknowledge signal. In this embodiment, the arbitration cycle by the bus arbiter 10 is detected as the bus free period. Open collector gate 1 during bus-free period
The output of 9 becomes 0V (= VSS) (when the signal transmission line 17 is at the low level, the output of the open collector gate 19 is turned off).

20 is energized through the open collector gate 19 only during the bus-free period, and the signal transmission line 1
7 is a current control resistor for supplying a current for accelerating the voltage change toward the final steady voltage value of 7 (here, 0 V) to the signal transmission path 17, and in the present embodiment, the resistance value thereof is less than that of the pull-down resistor 18. It is selected as a much smaller 560Ω.

FIG. 2 is a timing chart for explaining the operation and effect of this embodiment. In FIG.
(A) shows a system clock for operating the system bus, and (b) shows an acknowledge signal (ACK1 or ACK2 in FIG. 1) output from the bus arbiter 10. (C)
Shows the signal transition on the signal transmission line 17 when the present invention is not applied, and (d) shows the signal transmission line 17 in the present embodiment.
The signal transitions above are shown. 25 is an I / O as a bus master
DMA cycle (1) by the unit, 26 is a release cycle in which the I / O unit as a bus master releases the bus right, and 27 is for giving the bus right to the I / O unit for which the bus arbiter 10 requests the bus right. Is the arbitration cycle of. 28 indicates a DMA cycle (2) which starts after the end of the arbitration cycle 27.

Next, the operation will be described. In the DMA cycle (1), the I / O unit (11 or 12) as a bus master performs data transfer (DMA transfer) by DMA on the system bus. This period, Figure 2
As shown in (b), the acknowledge signal is inactive.

It is assumed that the driver of the I / O unit operating as a bus master outputs a high level signal to the signal transmission line 17 to end the DMA cycle (1) and release the bus right. In the release cycle 26 and the next arbitration cycle 27, all the drivers on the signal transmission path 17 of the system bus are in the high impedance state.

In the release cycle 26, the case of the present embodiment and the case of not applying the present invention are substantially the same, and the voltage of the signal transmission line 17 is the final steady voltage value due to the action of the pull-down resistor 18. Low level (= 0
V). The speed of this voltage change depends on the time constant determined by the resistance value of the pull-down resistor 18 and the size of the load connected to the signal transmission line 17, and as shown in (c) and (d) of FIG. The changes are slow.

In the next arbitration cycle 27, the bus arbiter 10 will have the I / O unit (11 or 12).
As a response to the bus right request from the I / O unit (11 or 12), an acknowledge signal to the I / O unit (11 or 12) shown in FIG.
Activate as shown in (b).

When the present invention is not applied, the time constant of the signal transmission line 17 is constant even during the arbitration cycle 27, so the voltage of the signal transmission line 17 is as shown in FIG.
As can be seen in FIG. Therefore, the DMA cycle (2) after the end of the arbitration cycle 27
When it is desired to drive the signal transmission line 17 to a low level at the beginning of, the signal voltage has to transit from a high level to a low level, and the signal amplitude is large.
It takes time for signal transition.

On the other hand, in the present embodiment, during the arbitration cycle 27, the output of the open collector gate 19 for bus-free monitoring becomes low level (0V = VSS) due to the activation of the acknowledge signal, so the pull-down resistor 18 In addition, the current control resistor 20 is connected to the signal transmission line as a pull-down resistor, and the parallel connection of the resistor 20 and the pull-down resistor 18 becomes a substantial pull-down resistor, and the time constant of the signal transmission line 17 is small. As a result, as shown in FIG. 2D, the voltage of the signal transmission line 17 rapidly decreases toward the low level during the arbitration cycle 27. In other words, during the arbitration cycle, a current for accelerating the voltage drop of the signal transmission line 17 is supplied through the current control resistor 20.
Shed on.

At the end of the arbitration cycle, however, the voltage of the signal transmission line 17 drops to a voltage value close to the threshold voltage VTH of the TTL logic (that is, in the present embodiment, as shown in FIG. 2D). The resistance value of the current control resistor 20 is determined so that the voltage drops from a high level to VTH in one system clock time). Thus, when it is necessary to determine the voltage of the signal transmission line 17 at the low level at the beginning of the next DMA cycle (2), the signal voltage may be transited from VTH.
Since the signal amplitude is smaller than that in the case of (c), high-speed signal transition is possible.

Now, when the signal transmission line 17 is at the low level, the output of the open collector gate 19 is in the off state. Even if the signal transmission line 17 is at the high level, the output of the open collector gate 19 becomes the high level when the bus is free, and no current flows through the resistor 20 to the signal transmission line 17. Therefore, unlike the pull-down resistor 18 that always operates, it is not necessary to consider the I0L and I0H ratings of the driver when determining the resistance value of the current control resistor 20, and the resistance value of the current control resistor 20 is made sufficiently small. be able to.

Therefore, the arbitration cycle 2
It is also possible to set the substantial pull-down resistance value in the period of 7 to be a value much smaller than the resistance value of the pull-down resistor 18 and reduce the voltage of the signal transmission line 17 to the low level at the end point of the arbitration cycle 27. By doing so, DM immediately after the arbitration cycle
When it is desired to set the transmission line of the signal transmission line 17 to the low level at the beginning of the A cycle (2), the signal amplitude becomes almost zero, and the signal transition time becomes extremely short. However, on the other hand,
When it is desired to determine the high level at the beginning of the DMA cycle (2), there is a weak point that the transition is delayed because the signal transition of the maximum amplitude is almost from the low level to the high level. According to this embodiment, the amplitude in the case of the transition to the high level becomes smaller than the maximum amplitude by about the threshold voltage VTH, so that such a weak point can be compensated.

In the embodiment shown in FIG. 1, when the arbitration cycle becomes longer than one clock cycle, the voltage of the signal transmission line 17 drops to the final steady voltage of 0V. When the voltage of the signal transmission line immediately before the arbitration cycle is low level, the voltage of the signal transmission line after the arbitration cycle becomes low level. Therefore, in such a case, the effect of speeding up the signal transition to the high level immediately after the arbitration cycle cannot be obtained.

In order to keep the signal transmission line voltage after the arbitration cycle near the threshold voltage VTH, even when the arbitration cycle is long and the voltage of the signal transmission line 17 immediately before the arbitration cycle is low level, For example, as shown in FIG. 3, Vcc and Vss of the open collector gate 19 for bus-free monitoring are set to 2
The voltage may be raised to Vcc = 7V and VSS = 2V. However, the level shifter 31 is inserted at the input side of the open collector gate 19 in accordance with the increase of VCC and VSS by 2V, and the bus acknowledge signals ACK1 and ACK2 are set to 2 levels.
The level is shifted by V.

In this modification, the output of the open collector gate 19 becomes low level during the arbitration cycle, and the low level is 2V = VSS. As a result, the voltage value determined by the resistance voltage division by the pull-down resistor 18 connected to 0V and the current control resistor 20 connected to 2V becomes the final steady voltage value, which is almost the threshold voltage VTH. In other words, in this example, a current for accelerating the voltage change is supplied to the signal transmission line 17 through the resistor 20 so that the signal transmission line 17 has almost the threshold voltage.

In FIG. 4, a pull-up resistor 42 is used instead of the pull-down resistor 18 of the embodiment shown in FIG.
Shows an example connected to. The operation principle in this case is the same as that of the embodiment shown in FIG. However, the final steady-state voltage of the signal transmission line 17 in the bus-free state is not 0V, but the resistance voltage division between the pull-up resistor 42 connected to 5V and the resistor 20 connected to 0V = VCC through the open collector gate 19. The voltage is determined by In this example, the pull-up resistor 42 is 3.9 KΩ, and the current control resistor 20 is
Is 1 KΩ. The resistance value of the pull-up resistor 42 must be selected so that the current flowing during driving the driver does not exceed the I0L rating of the driver.

In the example described above, the method of detecting the arbitration cycle as the bus-free period by using the bus acknowledge signal from the bus arbiter to notify the granting of the bus right is adopted, but the invention is not limited to this. . For example, EISA (Extended Industria)
l In the Standard Architecture) bus, all the bus acknowledge signals are active during the DMA cycle, which is not suitable for bus-free detection. Therefore, it is necessary to detect the bus-free period by using an appropriate signal such as the START signal indicating the start of the DMA cycle.

FIG. 5 is a schematic configuration diagram showing an example of a semiconductor integrated circuit device which can be used for controlling the signal transmission path of the bus described with reference to FIGS. 1 to 4. The semiconductor integrated circuit device 50 includes a bus-free monitoring unit 51 and a current control unit 5
2. The variable resistance section 53 is integrated on a chip.
For example, a maximum of 32 signal transmission paths such as a system bus can be controlled simultaneously.

The current control section 52 comprises 32 systems, each of which is connected in series with, for example, three resistance elements R1 and R.
2, R3, the connection point between the resistance elements R1 and R2, the resistance element R
The switch element SW connects the connection point of R2 and R3 or the open end of the resistance element R3 to the corresponding transmission line connection pin 55 (32 in total). The bus-free monitoring unit 51 is also composed of 32 systems, has an open collector gate G1 for each system, and the open end of the resistance element R1 of the corresponding system in the current control unit 52 is connected to the output thereof. Bus-free monitoring unit 5
1, the ACK signal input to the plurality of ACK pins 56 by the gate G2 is used as bus-free information to detect a bus-free period such as an arbitration cycle, and the outputs of the open collector gates G of all systems are at a low level during the bus-free period. become. This low level is equal to the VSS voltage applied to VSS pin 58. The resistance variable unit 53 controls the switch element SW of each system in the current control unit 52 in accordance with a command input to the two command pins 57, for example.

When this semiconductor integrated circuit device 50 is used to control the 32-bit signal transmission line 60 of the system bus, the signal transmission line 60 is connected to the signal transmission line connection pin 55 and the bus from the bus arbiter of the system bus is connected. Connect the acknowledge signal to ACK pin 56.

If a pull-down resistor is connected to the signal transmission line 60, the same control of the signal transmission line 60 as described with reference to FIG. 1 is possible. By applying an appropriate voltage to the VSS pin 58, the same control as that described with reference to FIG. 2 is possible, but in this case, the bus acknowledge signal is appropriately level-shifted and then input to the ACK pin 56. (A level shifter therefor may be provided in the bus-free monitoring unit 51). When the pull-up resistor is connected to the signal transmission line 60, the same control of the signal transmission line 60 as described with reference to FIG. 4 is possible.

A command is given from the command pin 57 to control the switch element SW of the current control unit 52 by the resistance variable unit 53 to adjust the gradual change in the voltage of the signal transmission line 60 during the bus-free state or the final steady voltage. it can. When the connection point of the resistance elements R1 and R2 is selected by the switch element SW, only the resistance element R1 is included in the signal transmission line 60.
Since it is connected between the open collector gate G1 and the open collector gate G1, the voltage change of the signal transmission line 60 becomes the steepest.
When the pull-up resistor is connected as shown in FIG. 4, the final steady voltage is the lowest.

The open end of the resistance element R3 is the switch element SW.
When selected by, the series connection of the resistance elements R1, R2 and R3 is connected between the open collector gate G1 and the signal transmission line 60, so that the voltage change of the signal transmission line 60 becomes the slowest. When the pull-up resistor is connected as shown in FIG. 4, the final steady voltage becomes highest.

[0042]

According to the method of the first aspect of the present invention, during the period when all the drivers for driving the signal transmission line are in the high impedance state, the voltage of the signal transmission line is increased to the voltage value at which the signal transition becomes fast after the period. By changing rapidly, the delay of signal confirmation after the high impedance state period is reduced,
The signal transmission path can be speeded up.

According to the method of the invention of claim 2, for example,
During the system bus arbitration cycle, by rapidly changing the voltage of the address / data line to a voltage value that makes the signal transition of the next bus cycle faster.
The delay in signal determination in the bus cycle immediately after the arbitration cycle can be reduced, and the speed of the system bus can be increased.

According to the semiconductor integrated circuit device of the third aspect of the present invention, it is possible to simultaneously and easily increase the speed of a large number of signal transmission paths such as a system bus by the single integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a simplified configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation and effect of the present invention.

FIG. 3 is a circuit diagram showing a simplified configuration of another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a simplified configuration of another embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of an example of a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

10 bus arbiter 11, 12 I / O unit 13, 14 bus request signal (REQ1, REQ
2) 15,16 Acknowledge signal (ACK1, ACK2) 17 Signal transmission line (data / address line) 18 Pull-down resistor 19 Bus-free monitoring open collector gate 20 Current control resistor 21,22,23 Three-state driver 25 DMA cycle (1) 26 release cycle 27 arbitration cycle 28 DMA cycle (2) 31 level shifter 42 pull-up resistor 50 semiconductor integrated circuit 51 bus-free monitoring unit 52 current control unit 53 resistance variable unit 55 signal transmission line connection pin 56 ACK pin 57 command Pin 58 VSS Pin 59 VCC Pin 60 Signal Transmission Line R1, R2, R3 Resistance Element SW Switch Element G1 Open Collector Gate G2 Gate

Claims (3)

[Claims] 1. A method of controlling a signal transmission line driven by a driver, wherein the driver detects a period in a high impedance state, and the driver transmits a signal to a specific voltage value during the high impedance state. A method for controlling a signal transmission path, which comprises flowing a current for accelerating a voltage change. 2. A method of controlling a bus signal transmission line having a bus free period, in which all drivers for driving the bus signal transmission line are in a high impedance state, detecting a bus free period, and transmitting a bus signal during the bus free period. A method for controlling a signal transmission line, characterized in that a current for accelerating a voltage change to a specific voltage value is passed through the line. 3. A bus-free information input pin, a bus signal transmission line connection pin, and bus-free information input from the bus-free information input pin bring all drivers for driving the bus signal transmission line into a high-impedance state. And a circuit portion for energizing the resistance element connected to the signal transmission line connecting pin during the bus free period, the signal transmission line passing through the resistance element during the bus free period. A semiconductor integrated circuit device for signal transmission path control, wherein a current for accelerating a voltage change to a specific voltage value is passed through a signal transmission path of a bus connected to a connection pin.